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authorMartin Braun <martin.braun@ettus.com>2024-02-12 12:27:37 +0100
committerAki Tomita <121511582+atomita-ni@users.noreply.github.com>2024-02-25 16:54:12 -0600
commitc266d1f8102f30c6fed8f014d7bdf1e8861b8c3c (patch)
treebb66ddeb7b6e793607c92de6718010dd7db6b9f3
parentfpga: Update tooling to use image builder instead of make (diff)
downloaduhd-c266d1f8102f30c6fed8f014d7bdf1e8861b8c3c.tar.xz
uhd-c266d1f8102f30c6fed8f014d7bdf1e8861b8c3c.zip
ci: Use rfnoc_image_builder in FPGA pipelines
- This adds a step to install rfnoc_image_builder before doing X4x0 builds - This is now required by repeat_fpga_build.py
-rw-r--r--fpga/.ci/fpga-pipeline-pr.yml9
-rw-r--r--fpga/.ci/templates/job-build-fpga.yml22
-rw-r--r--fpga/.ci/templates/stages-fpga-pipeline.yml9
3 files changed, 39 insertions, 1 deletions
diff --git a/fpga/.ci/fpga-pipeline-pr.yml b/fpga/.ci/fpga-pipeline-pr.yml
index d8ee3955b..a0d2ba7a3 100644
--- a/fpga/.ci/fpga-pipeline-pr.yml
+++ b/fpga/.ci/fpga-pipeline-pr.yml
@@ -47,18 +47,22 @@ parameters:
displayName: X410 Targets
default:
X410_XG_100:
+ image_core: x410_200_rfnoc_image_core.yml
target_name: X410_XG_100
timeout: 720
max_attempts: 2
X410_UC_200:
+ image_core: x410_200_rfnoc_image_core.yml
target_name: X410_UC_200
timeout: 720
max_attempts: 2
X410_X4_200:
+ image_core: x410_200_rfnoc_image_core.yml
target_name: X410_X4_200
timeout: 720
max_attempts: 2
X410_CG_400:
+ image_core: x410_400_rfnoc_image_core.yml
target_name: X410_CG_400
timeout: 720
max_attempts: 2
@@ -67,22 +71,27 @@ parameters:
displayName: X440 Targets
default:
X440_CG_1600:
+ image_core: x440_1600_rfnoc_image_core.yml
target_name: X440_CG_1600
timeout: 720
max_attempts: 2
X440_CG_400:
+ image_core: x440_400_rfnoc_image_core.yml
target_name: X440_CG_400
timeout: 720
max_attempts: 2
X440_X4_1600:
+ image_core: x440_1600_d_rfnoc_image_core.yml
target_name: X440_X4_1600
timeout: 720
max_attempts: 2
X440_X4_400:
+ image_core: x440_400_d_rfnoc_image_core.yml
target_name: X440_X4_400
timeout: 720
max_attempts: 2
X440_X4_200:
+ image_core: x440_200_rfnoc_image_core.yml
target_name: X440_X4_200
timeout: 720
max_attempts: 2
diff --git a/fpga/.ci/templates/job-build-fpga.yml b/fpga/.ci/templates/job-build-fpga.yml
index 6eca9f7fe..d415ef714 100644
--- a/fpga/.ci/templates/job-build-fpga.yml
+++ b/fpga/.ci/templates/job-build-fpga.yml
@@ -74,8 +74,28 @@ jobs:
displayName: 'Populate build-ip'
- bash: |
+ mkdir -p $(Build.BinariesDirectory)/prefix
+ # hwtools hwsetup.sh will setup a venv, so we'll reuse that for the
+ # image builder! That's also why we install the image builder in the
+ # same step as building the bitfile: To avoid having to run hwsetup.sh
+ # twice.
source $(Build.SourcesDirectory)/uhddev/fpga/.ci/scripts/run_setup.sh ./
- python3 ../../tools/utils/repeat_fpga_build.py --target $(target_name) --num $(max_attempts) --seed $(($(System.JobAttempt)-1)) --persistent
+ pip3 install -U numpy mako "ruamel.yaml<0.18.0" jsonschema
+ set -o xtrace
+ # hwsetup.sh injects garbage cmake versions into PATH, so avoid that by
+ # going straight to /usr/bin/cmake
+ /usr/bin/cmake -S $(Build.SourcesDirectory)/uhddev/host \
+ -B $(Build.BinariesDirectory)/build_image_builder \
+ -DCMAKE_INSTALL_PREFIX=$(Build.BinariesDirectory)/prefix \
+ -DUHD_BOOST_REQUIRED=OFF \
+ -DENABLE_LIBUHD=OFF -DENABLE_PYMOD_UTILS=ON \
+ -DENABLE_DOXYGEN=OFF -DENABLE_MAN_PAGES=OFF -DENABLE_MANUAL=OFF
+ /usr/bin/cmake --build $(Build.BinariesDirectory)/build_image_builder
+ /usr/bin/cmake --install $(Build.BinariesDirectory)/build_image_builder
+ # rfnoc_image_builder does not currently get installed to a bin/ folder
+ # via pip, so we add it to PATH
+ export PATH=$BUILD_BINARIESDIRECTORY/prefix/bin:$VIRTUAL_ENV/bin:$PATH
+ python3 ../../tools/utils/repeat_fpga_build.py --target $(target_name) --image-core $(image_core) --num $(max_attempts) --seed $(($(System.JobAttempt)-1)) --persistent
workingDirectory: ${{ parameters.top_dir }}
env:
PATCHES_PATH: $(sdr-vivado-patches)
diff --git a/fpga/.ci/templates/stages-fpga-pipeline.yml b/fpga/.ci/templates/stages-fpga-pipeline.yml
index 5e80fdea1..96e560e0a 100644
--- a/fpga/.ci/templates/stages-fpga-pipeline.yml
+++ b/fpga/.ci/templates/stages-fpga-pipeline.yml
@@ -47,18 +47,22 @@ parameters:
type: object
default:
X410_X4_200:
+ image_core: x410_200_rfnoc_image_core.yml
target_name: X410_X4_200
timeout: 720
max_attempts: 2
X410_UC_200:
+ image_core: x410_200_rfnoc_image_core.yml
target_name: X410_UC_200
timeout: 720
max_attempts: 2
X410_X4_400:
+ image_core: x410_400_d_rfnoc_image_core.yml
target_name: X410_X4_400
timeout: 720
max_attempts: 2
X410_CG_400:
+ image_core: x410_400_rfnoc_image_core.yml
target_name: X410_CG_400
timeout: 720
max_attempts: 2
@@ -71,22 +75,27 @@ parameters:
type: object
default:
X440_CG_1600:
+ image_core: x440_1600_rfnoc_image_core.yml
target_name: X440_CG_1600
timeout: 720
max_attempts: 2
X440_CG_400:
+ image_core: x440_400_rfnoc_image_core.yml
target_name: X440_CG_400
timeout: 720
max_attempts: 2
X440_X4_1600:
+ image_core: x440_1600_d_rfnoc_image_core.yml
target_name: X440_X4_1600
timeout: 720
max_attempts: 2
X440_X4_400:
+ image_core: x440_400_d_rfnoc_image_core.yml
target_name: X440_X4_400
timeout: 720
max_attempts: 2
X440_X4_200:
+ image_core: x440_200_rfnoc_image_core.yml
target_name: X440_X4_200
timeout: 720
max_attempts: 2