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* Implement ampintcmsi(4) in ampintc(4) to support MSI. The GICv2M is anpatrick2018-07-091-3/+5
| | | | | | | | | | | | | | | | | | | extension to the GIC controller, which is represented as subnode in the device tree. There can be multiple GICv2Ms, so it makes sense to attach those to ampintc(4) as some kind of simplebus. The GICv2M is simply an interrupt generator that can be used by PCIe devices to ring the door bell. There is no need for further configuration, we only need to find out which SPIs we are allowed to use for MSI and to register an edge triggered interrupt on a (randomly) allocated SPI. Implement support for interrupt types. The GIC only seems to support level triggered active-high or egdge triggered low-to-high interrupts. We currently always configure them to be level triggered, which is a sane default for most controllers. Since MSI interupts on the GIC are edge triggered, we need to be able to parse the type information and to configure the interrupt correspondingly. ok kettenis@
* Dynamically attach agtimer(4). Since agtimer(4) also provides the delay()kettenis2016-08-101-2/+2
| | | | | | | | | | function for platforms that have it, rework the code a bit such that it can be used before agtimer(4) attaches. Introduce a new agtimer_init() function that checks whether the CPU implements the Generic Timer feature and switches to agtimer_delay() if that feature is present. Call this function from the generic platform initialization code. ok jsg@
* Dynamically attach ampintc(4) and make it register itself as an interruptkettenis2016-08-041-2/+2
| | | | | | | | | | | | | | | controller. Switch all i.MX6 devices over to the new FDT-aware interrupt establish API and enable imxgpc(4). This may break other platforms that use ampintc(4) as their interrupt controller. We will fix this as soon as possible by switching them over to the new interrupt establish API as well. This also removes the hack in fec(4) to avoid the gpio-based interrupt workaround. This commit is an essential step on the road to fix that issue properly. ok patrick@, jsg@
* Rework mainbus and implement simplebus to be able to span a tree-likepatrick2016-05-021-2/+2
| | | | | | | topology based on device tree information. Introduce a common attach args structure to be used for all fdt-capable bus devices. ok jsg@ kettenis@
* Support for the ARM Generic Timer used in the Cortex-A7 and Cortex-A15.patrick2013-09-091-1/+5
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* Add a driver for the secondary cache controller on the PandaBoard andpatrick2013-05-021-1/+5
| | | | | | | other ARM Cortex based boards. Disabled for now, until proper secondary cache flushing is done where it's needed. ok miod@
* Add a cortex bus which represents the ARM MPCore Complex.patrick2013-05-011-0/+14
It will attach only to ARM Cortex A9 and A15 SoCs. The generic interrupt controller and timer will attach to this bus, later a secondary cache controller can be added. The base address for those controllers are figured out using the periphbase register. ok bmercer@
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