| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Make it clearer where message "spurious interrupt" comes from. |   visa | 2019-09-01 | 1 | -3/+3 |
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| * | Ensure that a posted write completes when re-enabling interrupts | visa | 2019-08-04 | 1 | -3/+7 |
| | | | | | or sending an IPI. | ||||
| * | Remember to detach the event counter when disestablishing | visa | 2019-03-17 | 1 | -1/+2 |
| | | | | | an interrupt handler. | ||||
| * | Let each interrupt controller driver choose how to implement | visa | 2019-03-17 | 1 | -2/+10 |
| | | | | | | | | intr_barrier(9). With this change, the barrier should finally work properly with cnmac(4) interrupts that have been assigned to secondary cores. | ||||
| * | Fix incorrect flag. | visa | 2019-03-16 | 1 | -2/+2 |
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| * | Include header <sys/evcount.h> where event counters are used, so that | visa | 2019-03-16 | 1 | -1/+2 |
| | | | | | header <machine/intr.h> can eventually stop including it on octeon. | ||||
| * | Declare ci_ipl volatile to prevent the compiler from optimizing | visa | 2018-02-24 | 1 | -11/+1 |
| | | | | | | | | | | | | | | | | | | | or reordering accesses to the variable. Assume that the assembler preserves the correct sequence of instructions, which allows the removal of the explicit noreorder/reorder toggles from the C code. With ci_ipl being volatile, drop mips_sync() calls that follow the accesses of the variable. The sync is redundant as a compiler barrier. In addition, the MIPS64 CPU designs should not need the sync for pipeline or write buffer control. According to miod@, the use of the instruction is a carryover from code targeting early MIPS designs that lack tight integration with the cache and write buffer. Discussed with and testing help from miod@. Tested on CN5020, CN6120, CN7130, CN7360, Loongson 2F and 3A1000, R4400, R8000, R10000 and R16000. | ||||
| * | Always lock the kernel lock with non-MP-safe interrupt handlers. | visa | 2018-01-23 | 1 | -2/+2 |
| | | | | | Suggested by kettenis@ | ||||
| * | Make octeon_intr_establish() assume edge triggering with CIU3. | visa | 2017-12-27 | 1 | -2/+3 |
| | | | | | This makes the API usable with edge triggered interrupt sources. | ||||
| * | Ensure interrupt delivery is disabled when setting interrupt | visa | 2017-12-27 | 1 | -1/+3 |
| | | | | | delivery entry. | ||||
| * | Clear any pending (edge-triggered) interrupts at setup to avoid | visa | 2017-08-09 | 1 | -2/+3 |
| | | | | | spurious interrupts with newly established handlers. | ||||
| * | Add a driver for CIU3. Not quite finished yet, but good enough for now. | visa | 2017-07-30 | 1 | -0/+540 |
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index : wireguard-openbsd | |
| WireGuard implementation for the OpenBSD kernel | Matt Dunwoodie |
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