diff options
Diffstat (limited to 'arch/arm/boot')
1118 files changed, 44682 insertions, 16426 deletions
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index 54a09f9464fb..abd6a2889fd0 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile @@ -10,22 +10,16 @@ # # Copyright (C) 1995-2002 Russell King # - OBJCOPYFLAGS :=-O binary -R .comment -S -ifneq ($(MACHINE),) -include $(MACHINE)/Makefile.boot -endif - -# Note: the following conditions must always be true: # ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET) -# PARAMS_PHYS must be within 4MB of ZRELADDR -# INITRD_PHYS must be in RAM -ZRELADDR := $(zreladdr-y) -PARAMS_PHYS := $(params_phys-y) -INITRD_PHYS := $(initrd_phys-y) +ifdef CONFIG_PHYS_OFFSET +add_hex = $(shell printf 0x%x $$(( $(1) + $(2) )) ) +ZRELADDR := $(call add_hex, $(CONFIG_PHYS_OFFSET), $(TEXT_OFFSET)) +endif -export ZRELADDR INITRD_PHYS PARAMS_PHYS +PHYS_OFFSET := $(CONFIG_PHYS_OFFSET) +export ZRELADDR PARAMS_PHYS PHYS_OFFSET targets := Image zImage xipImage bootpImage uImage @@ -90,17 +84,10 @@ $(obj)/uImage: $(obj)/zImage FORCE @$(check_for_multiple_loadaddr) $(call if_changed,uimage) -$(obj)/bootp/bootp: $(obj)/zImage initrd FORCE +$(obj)/bootp/bootp: $(obj)/zImage FORCE $(Q)$(MAKE) $(build)=$(obj)/bootp $@ $(obj)/bootpImage: $(obj)/bootp/bootp FORCE $(call if_changed,objcopy) -PHONY += initrd -initrd: - @test "$(INITRD_PHYS)" != "" || \ - (echo This machine does not support INITRD; exit -1) - @test "$(INITRD)" != "" || \ - (echo You must specify INITRD; exit -1) - subdir- := bootp compressed dts diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile index 981a8d03f064..a2934e6fd89a 100644 --- a/arch/arm/boot/bootp/Makefile +++ b/arch/arm/boot/bootp/Makefile @@ -5,9 +5,40 @@ # This file is included by the global makefile so that you can add your own # architecture-specific flags and dependencies. # - GCOV_PROFILE := n +ifdef PHYS_OFFSET +add_hex = $(shell printf 0x%x $$(( $(1) + $(2) )) ) + +# If PHYS_OFFSET is set, INITRD_PHYS and PARAMS_PHYS can be derived, +# otherwise they must be passed on the command line. +# +# Note: the following conditions must always be true: +# PARAMS_PHYS must be within 4MB of ZRELADDR +# INITRD_PHYS must be in RAM + +PARAMS_PHYS := $(call add_hex, $(PHYS_OFFSET), 0x100) + +# guess an initrd location if possible +initrd_offset-$(CONFIG_ARCH_FOOTBRIDGE) += 0x00800000 +initrd_offset-$(CONFIG_ARCH_SA1100) += 0x00800000 +initrd_offset-$(CONFIG_ARCH_RPC) += 0x08000000 +INITRD_OFFSET := $(initrd_offset-y) +ifdef INITRD_OFFSET +INITRD_PHYS := $(call add_hex, $(PHYS_OFFSET), $(INITRD_OFFSET)) +endif + +endif + +PHONY += initrd +initrd: + @test "$(PARAMS_PHYS)" != "" || \ + (echo bootpImage: You must specify PHYS_OFFSET of PARAMS_PHYS ; exit -1) + @test "$(INITRD_PHYS)" != "" || \ + (echo bootpImage: You must specify INITRD_OFFSET or INITRD_PHYS ; exit -1) + @test "$(INITRD)" != "" || \ + (echo bootpImage: You must specify INITRD; exit -1) + LDFLAGS_bootp := --no-undefined -X \ --defsym initrd_phys=$(INITRD_PHYS) \ --defsym params_phys=$(PARAMS_PHYS) -T @@ -24,6 +55,6 @@ $(obj)/bootp: $(src)/bootp.lds $(addprefix $(obj)/,init.o kernel.o initrd.o) FOR $(obj)/kernel.o: arch/arm/boot/zImage FORCE -$(obj)/initrd.o: $(INITRD) FORCE +$(obj)/initrd.o: initrd $(INITRD) FORCE PHONY += $(INITRD) diff --git a/arch/arm/boot/bootp/bootp.lds b/arch/arm/boot/bootp/bootp.lds index fc54394f4340..160128186bf8 100644 --- a/arch/arm/boot/bootp/bootp.lds +++ b/arch/arm/boot/bootp/bootp.lds @@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * linux/arch/arm/boot/bootp/bootp.lds * * Copyright (C) 2000-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ OUTPUT_ARCH(arm) ENTRY(_start) diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 74d2f1401acb..41bcbb460fac 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -76,10 +76,10 @@ CPPFLAGS_vmlinux.lds += -DTEXT_OFFSET="$(TEXT_OFFSET)" CPPFLAGS_vmlinux.lds += -DMALLOC_SIZE="$(MALLOC_SIZE)" compress-$(CONFIG_KERNEL_GZIP) = gzip -compress-$(CONFIG_KERNEL_LZO) = lzo -compress-$(CONFIG_KERNEL_LZMA) = lzma -compress-$(CONFIG_KERNEL_XZ) = xzkern -compress-$(CONFIG_KERNEL_LZ4) = lz4 +compress-$(CONFIG_KERNEL_LZO) = lzo_with_size +compress-$(CONFIG_KERNEL_LZMA) = lzma_with_size +compress-$(CONFIG_KERNEL_XZ) = xzkern_with_size +compress-$(CONFIG_KERNEL_LZ4) = lz4_with_size libfdt_objs := fdt_rw.o fdt_ro.o fdt_wip.o fdt.o @@ -92,10 +92,7 @@ ifeq ($(CONFIG_USE_OF),y) OBJS += $(libfdt_objs) fdt_check_mem_start.o endif -# -fstack-protector-strong triggers protection checks in this code, -# but it is being used too early to link to meaningful stack_chk logic. -$(foreach o, $(libfdt_objs) atags_to_fdt.o fdt_check_mem_start.o, \ - $(eval CFLAGS_$(o) := -I $(srctree)/scripts/dtc/libfdt -fno-stack-protector)) +OBJS += lib1funcs.o ashldi3.o bswapsdi2.o targets := vmlinux vmlinux.lds piggy_data piggy.o \ head.o $(OBJS) @@ -103,6 +100,7 @@ targets := vmlinux vmlinux.lds piggy_data piggy.o \ KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin \ + -I$(srctree)/scripts/dtc/libfdt -fno-stack-protector \ -I$(obj) $(DISABLE_ARM_SSP_PER_TASK_PLUGIN) ccflags-remove-$(CONFIG_FUNCTION_TRACER) += -pg asflags-y := -DZIMAGE @@ -130,8 +128,6 @@ endif # Next argument is a linker script LDFLAGS_vmlinux += -T -OBJS += lib1funcs.o ashldi3.o bswapsdi2.o - # We need to prevent any GOTOFF relocs being used with references # to symbols in the .bss section since we cannot relocate them # independently from the rest at run time. This can be achieved by diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index bf79f2f78d23..9f406e9c0ea6 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -67,11 +67,7 @@ #if defined(CONFIG_ARCH_SA1100) .macro loadsp, rb, tmp1, tmp2 mov \rb, #0x80000000 @ physical base address -#ifdef CONFIG_DEBUG_LL_SER3 - add \rb, \rb, #0x00050000 @ Ser3 -#else add \rb, \rb, #0x00010000 @ Ser1 -#endif .endm #else .macro loadsp, rb, tmp1, tmp2 diff --git a/arch/arm/boot/compressed/misc-ep93xx.h b/arch/arm/boot/compressed/misc-ep93xx.h new file mode 100644 index 000000000000..3dc942589cba --- /dev/null +++ b/arch/arm/boot/compressed/misc-ep93xx.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> + */ + +#include <asm/mach-types.h> + +static inline unsigned int __raw_readl(unsigned int ptr) +{ + return *((volatile unsigned int *)ptr); +} + +static inline void __raw_writeb(unsigned char value, unsigned int ptr) +{ + *((volatile unsigned char *)ptr) = value; +} + +static inline void __raw_writel(unsigned int value, unsigned int ptr) +{ + *((volatile unsigned int *)ptr) = value; +} + +/* + * Some bootloaders don't turn off DMA from the ethernet MAC before + * jumping to linux, which means that we might end up with bits of RX + * status and packet data scribbled over the uncompressed kernel image. + * Work around this by resetting the ethernet MAC before we uncompress. + */ +#define PHYS_ETH_SELF_CTL 0x80010020 +#define ETH_SELF_CTL_RESET 0x00000001 + +static inline void ep93xx_ethernet_reset(void) +{ + unsigned int v; + + /* Reset the ethernet MAC. */ + v = __raw_readl(PHYS_ETH_SELF_CTL); + __raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL); + + /* Wait for reset to finish. */ + while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET) + ; +} + +#define TS72XX_WDT_CONTROL_PHYS_BASE 0x23800000 +#define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000 +#define TS72XX_WDT_FEED_VAL 0x05 + +static inline void __maybe_unused ts72xx_watchdog_disable(void) +{ + __raw_writeb(TS72XX_WDT_FEED_VAL, TS72XX_WDT_FEED_PHYS_BASE); + __raw_writeb(0, TS72XX_WDT_CONTROL_PHYS_BASE); +} + +static inline void ep93xx_decomp_setup(void) +{ + if (machine_is_ts72xx()) + ts72xx_watchdog_disable(); + + if (machine_is_adssphere() || + machine_is_edb9301() || + machine_is_edb9302() || + machine_is_edb9302a() || + machine_is_edb9302a() || + machine_is_edb9307() || + machine_is_edb9307a() || + machine_is_edb9307a() || + machine_is_edb9312() || + machine_is_edb9315() || + machine_is_edb9315a() || + machine_is_edb9315a() || + machine_is_gesbc9312() || + machine_is_micro9() || + machine_is_micro9l() || + machine_is_micro9m() || + machine_is_micro9s() || + machine_is_micro9m() || + machine_is_micro9l() || + machine_is_micro9s() || + machine_is_sim_one() || + machine_is_snapper_cl15() || + machine_is_ts72xx() || + machine_is_bk3() || + machine_is_vision_ep9307()) + ep93xx_ethernet_reset(); +} diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index e1e9a5dde853..abfed1aa2baa 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -23,6 +23,9 @@ unsigned int __machine_arch_type; #include <linux/types.h> #include <linux/linkage.h> #include "misc.h" +#ifdef CONFIG_ARCH_EP93XX +#include "misc-ep93xx.h" +#endif static void putstr(const char *ptr); @@ -128,13 +131,6 @@ asmlinkage void __div0(void) error("Attempting division by 0!"); } -const unsigned long __stack_chk_guard = 0x000a0dff; - -void __stack_chk_fail(void) -{ - error("stack-protector: Kernel stack is corrupted\n"); -} - extern int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); @@ -150,6 +146,9 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p, free_mem_end_ptr = free_mem_ptr_end_p; __machine_arch_type = arch_id; +#ifdef CONFIG_ARCH_EP93XX + ep93xx_decomp_setup(); +#endif arch_decomp_setup(); putstr("Uncompressing Linux..."); diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S index 1bcb68ac4b01..3fcb3e62dc56 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.S +++ b/arch/arm/boot/compressed/vmlinux.lds.S @@ -23,6 +23,7 @@ SECTIONS *(.ARM.extab*) *(.note.*) *(.rel.*) + *(.printk_index) /* * Discard any r/w data - this produces a link error if we have any, * which is required for PIC decompression. Local data generates @@ -57,6 +58,7 @@ SECTIONS *(.rodata) *(.rodata.*) *(.data.rel.ro) + *(.data.rel.ro.*) } .piggydata : { *(.piggydata) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 235ad559acb2..6aa7dc4db2fc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -61,6 +61,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d2_icp.dtb \ at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ + at91-sama5d3_eds.dtb \ at91-sama5d3_ksz9477_evb.dtb \ at91-sama5d3_xplained.dtb \ at91-dvk_som60.dtb \ @@ -79,6 +80,8 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-vinco.dtb dtb-$(CONFIG_SOC_SAMA7G5) += \ at91-sama7g5ek.dtb +dtb-$(CONFIG_SOC_SP7021) += \ + sunplus-sp7021-demo-v3.dtb dtb-$(CONFIG_ARCH_AXXIA) += \ axm5516-amarillo.dtb dtb-$(CONFIG_ARCH_BCM2835) += \ @@ -93,6 +96,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ bcm2837-rpi-cm3-io3.dtb \ + bcm2837-rpi-zero-2-w.dtb \ bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2711-rpi-cm4-io.dtb \ @@ -102,6 +106,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4708-asus-rt-ac56u.dtb \ bcm4708-asus-rt-ac68u.dtb \ bcm4708-buffalo-wzr-1750dhp.dtb \ + bcm4708-buffalo-wzr-1166dhp.dtb \ + bcm4708-buffalo-wzr-1166dhp2.dtb \ bcm4708-linksys-ea6300-v1.dtb \ bcm4708-linksys-ea6500-v2.dtb \ bcm4708-luxul-xap-1510.dtb \ @@ -132,6 +138,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm47094-luxul-xwr-3150-v1.dtb \ bcm47094-netgear-r8500.dtb \ bcm47094-phicomm-k3.dtb \ + bcm53015-meraki-mr26.dtb \ bcm53016-meraki-mr32.dtb \ bcm94708.dtb \ bcm94709.dtb \ @@ -143,8 +150,6 @@ dtb-$(CONFIG_ARCH_BCM_53573) += \ bcm47189-luxul-xap-810.dtb \ bcm47189-tenda-ac9.dtb \ bcm947189acdbmr.dtb -dtb-$(CONFIG_ARCH_BCM_63XX) += \ - bcm963138dvt.dtb dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ bcm911360_entphn.dtb \ bcm911360k.dtb \ @@ -178,6 +183,16 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2q-marvell-dmp.dtb dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb +dtb-$(CONFIG_ARCH_BCMBCA) += \ + bcm947622.dtb \ + bcm963138.dtb \ + bcm963138dvt.dtb \ + bcm963148.dtb \ + bcm963178.dtb \ + bcm96756.dtb \ + bcm96846.dtb \ + bcm96855.dtb \ + bcm96878.dtb dtb-$(CONFIG_ARCH_CLPS711X) += \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ @@ -187,6 +202,8 @@ dtb-$(CONFIG_ARCH_DAVINCI) += \ da850-lego-ev3.dtb dtb-$(CONFIG_ARCH_DIGICOLOR) += \ cx92755_equinox.dtb +dtb-$(CONFIG_ARCH_AIROHA) += \ + en7523-evb.dtb dtb-$(CONFIG_ARCH_EXYNOS3) += \ exynos3250-artik5-eval.dtb \ exynos3250-monk.dtb \ @@ -221,6 +238,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5420-arndale-octa.dtb \ exynos5420-peach-pit.dtb \ exynos5420-smdk5420.dtb \ + exynos5420-chagall-wifi.dtb \ + exynos5420-klimt-wifi.dtb \ exynos5422-odroidhc1.dtb \ exynos5422-odroidxu3.dtb \ exynos5422-odroidxu3-lite.dtb \ @@ -250,6 +269,8 @@ dtb-$(CONFIG_ARCH_HISI) += \ hi3519-demb.dtb dtb-$(CONFIG_ARCH_HIX5HD2) += \ hisi-x5hd2-dkb.dtb +dtb-$(CONFIG_ARCH_HPE_GXP) += \ + hpe-bmc-dl360gen10.dtb dtb-$(CONFIG_ARCH_INTEGRATOR) += \ integratorap.dtb \ integratorap-im-pd1.dtb \ @@ -269,7 +290,7 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp42x-dlink-dsm-g600.dtb \ intel-ixp42x-gateworks-gw2348.dtb \ intel-ixp43x-gateworks-gw2358.dtb \ - intel-ixp42x-netgear-wg302v2.dtb \ + intel-ixp42x-netgear-wg302v1.dtb \ intel-ixp42x-arcom-vulcan.dtb \ intel-ixp42x-gateway-7001.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += \ @@ -281,6 +302,7 @@ dtb-$(CONFIG_ARCH_KEYSTONE) += \ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-b3.dtb \ kirkwood-blackarmor-nas220.dtb \ + kirkwood-c200-v1.dtb \ kirkwood-cloudbox.dtb \ kirkwood-d2net.dtb \ kirkwood-db-88f6281.dtb \ @@ -452,8 +474,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos_7.dtb \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ + imx6dl-colibri-aster.dtb \ imx6dl-colibri-eval-v3.dtb \ - imx6dl-colibri-v1_1-eval-v3.dtb \ + imx6dl-colibri-iris.dtb \ + imx6dl-colibri-iris-v2.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ @@ -536,11 +560,13 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-apalis-eval.dtb \ imx6q-apalis-ixora.dtb \ imx6q-apalis-ixora-v1.1.dtb \ + imx6q-apalis-ixora-v1.2.dtb \ imx6q-apf6dev.dtb \ imx6q-arm2.dtb \ imx6q-b450v3.dtb \ imx6q-b650v3.dtb \ imx6q-b850v3.dtb \ + imx6q-bosch-acc.dtb \ imx6q-cm-fx6.dtb \ imx6q-cubox-i.dtb \ imx6q-cubox-i-emmc-som-v15.dtb \ @@ -681,9 +707,12 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-geam.dtb \ imx6ul-isiot-emmc.dtb \ imx6ul-isiot-nand.dtb \ - imx6ul-kontron-n6310-s.dtb \ - imx6ul-kontron-n6310-s-43.dtb \ + imx6ul-kontron-bl.dtb \ + imx6ul-kontron-bl-43.dtb \ imx6ul-liteboard.dtb \ + imx6ul-tqma6ul1-mba6ulx.dtb \ + imx6ul-tqma6ul2-mba6ulx.dtb \ + imx6ul-tqma6ul2l-mba6ulx.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ @@ -695,23 +724,41 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ imx6ull-14x14-evk.dtb \ + imx6ull-colibri-aster.dtb \ + imx6ull-colibri-emmc-aster.dtb \ imx6ull-colibri-emmc-eval-v3.dtb \ + imx6ull-colibri-emmc-iris.dtb \ + imx6ull-colibri-emmc-iris-v2.dtb \ imx6ull-colibri-eval-v3.dtb \ + imx6ull-colibri-iris.dtb \ + imx6ull-colibri-iris-v2.dtb \ + imx6ull-colibri-wifi-aster.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ + imx6ull-colibri-wifi-iris.dtb \ + imx6ull-colibri-wifi-iris-v2.dtb \ imx6ull-jozacp.dtb \ + imx6ull-kontron-bl.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-opos6uldev.dtb \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-phytec-tauri-emmc.dtb \ + imx6ull-phytec-tauri-nand.dtb \ + imx6ull-tqma6ull2-mba6ulx.dtb \ + imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-aster.dtb \ imx7d-colibri-emmc-aster.dtb \ + imx7d-colibri-emmc-iris.dtb \ + imx7d-colibri-emmc-iris-v2.dtb \ imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \ + imx7d-colibri-iris.dtb \ + imx7d-colibri-iris-v2.dtb \ imx7d-flex-concentrator.dtb \ imx7d-flex-concentrator-mfg.dtb \ imx7d-mba7.dtb \ @@ -726,16 +773,28 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb.dtb \ imx7d-sdb-reva.dtb \ imx7d-sdb-sht11.dtb \ + imx7d-smegw01.dtb \ imx7d-zii-rmu2.dtb \ imx7d-zii-rpu2.dtb \ imx7s-colibri-aster.dtb \ imx7s-colibri-eval-v3.dtb \ + imx7s-colibri-iris.dtb \ + imx7s-colibri-iris-v2.dtb \ imx7s-mba7.dtb \ imx7s-warp.dtb dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-com.dtb \ imx7ulp-evk.dtb +dtb-$(CONFIG_SOC_IMXRT) += \ + imxrt1050-evk.dtb +dtb-$(CONFIG_SOC_LAN966) += \ + lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \ + lan966x-kontron-kswitch-d10-mmt-8g.dtb \ + lan966x-pcb8290.dtb \ + lan966x-pcb8291.dtb \ + lan966x-pcb8309.dtb dtb-$(CONFIG_SOC_LS1021A) += \ + ls1021a-iot.dtb \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ ls1021a-tsn.dtb \ @@ -806,6 +865,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ logicpd-som-lv-37xx-devkit.dtb \ omap3430-sdp.dtb \ omap3-beagle.dtb \ + omap3-beagle-ab4.dtb \ omap3-beagle-xm.dtb \ omap3-beagle-xm-ab.dtb \ omap3-cm-t3517.dtb \ @@ -894,6 +954,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-regor-rdk.dtb \ am335x-sancloud-bbe.dtb \ am335x-sancloud-bbe-lite.dtb \ + am335x-sancloud-bbe-extended-wifi.dtb \ am335x-shc.dtb \ am335x-sbc-t335.dtb \ am335x-sl50.dtb \ @@ -967,11 +1028,12 @@ dtb-$(CONFIG_ARCH_OXNAS) += \ ox820-cloudengines-pogoplug-series-3.dtb dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8016-sbc.dtb \ + qcom-apq8026-asus-sparrow.dtb \ qcom-apq8026-lg-lenok.dtb \ qcom-apq8060-dragonboard.dtb \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ - qcom-apq8064-sony-xperia-yuga.dtb \ + qcom-apq8064-sony-xperia-lagan-yuga.dtb \ qcom-apq8064-asus-nexus7-flo.dtb \ qcom-apq8074-dragonboard.dtb \ qcom-apq8084-ifc6540.dtb \ @@ -988,14 +1050,17 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq8064-rb3011.dtb \ qcom-msm8226-samsung-s3ve3g.dtb \ qcom-msm8660-surf.dtb \ + qcom-msm8916-samsung-e5.dtb \ + qcom-msm8916-samsung-e7.dtb \ + qcom-msm8916-samsung-grandmax.dtb \ qcom-msm8916-samsung-serranove.dtb \ qcom-msm8960-cdp.dtb \ - qcom-msm8974-fairphone-fp2.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ - qcom-msm8974-samsung-klte.dtb \ - qcom-msm8974-sony-xperia-amami.dtb \ - qcom-msm8974-sony-xperia-castor.dtb \ - qcom-msm8974-sony-xperia-honami.dtb \ + qcom-msm8974-sony-xperia-rhine-amami.dtb \ + qcom-msm8974-sony-xperia-rhine-honami.dtb \ + qcom-msm8974pro-fairphone-fp2.dtb \ + qcom-msm8974pro-samsung-klte.dtb \ + qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ qcom-mdm9615-wp8548-mangoh-green.dtb \ qcom-sdx55-mtp.dtb \ qcom-sdx55-t55.dtb \ @@ -1106,7 +1171,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-torbreck.dtb dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ - socfpga_arria10_mercury_aa1.dtb \ + socfpga_arria10_chameleonv3.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ @@ -1146,10 +1211,15 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-disco.dtb \ stm32h750i-art-pi.dtb \ stm32mp135f-dk.dtb \ + stm32mp151a-prtt1a.dtb \ + stm32mp151a-prtt1c.dtb \ + stm32mp151a-prtt1s.dtb \ stm32mp153c-dhcom-drc02.dtb \ + stm32mp153c-dhcor-drc-compact.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ + stm32mp157a-dk1-scmi.dtb \ stm32mp157a-iot-box.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ @@ -1160,8 +1230,12 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dhcom-picoitx.dtb \ stm32mp157c-dk2.dtb \ + stm32mp157c-dk2-scmi.dtb \ stm32mp157c-ed1.dtb \ + stm32mp157c-ed1-scmi.dtb \ + stm32mp157c-emsbc-argon.dtb \ stm32mp157c-ev1.dtb \ + stm32mp157c-ev1-scmi.dtb \ stm32mp157c-lxa-mc1.dtb \ stm32mp157c-odyssey.dtb dtb-$(CONFIG_MACH_SUN4I) += \ @@ -1228,6 +1302,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-bananapro.dtb \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ + sun7i-a20-haoyu-marsboard.dtb \ sun7i-a20-hummingbird.dtb \ sun7i-a20-itead-ibox.dtb \ sun7i-a20-i12-tvbox.dtb \ @@ -1370,6 +1445,7 @@ dtb-$(CONFIG_ARCH_U8500) += \ ste-ux500-samsung-janice.dtb \ ste-ux500-samsung-gavini.dtb \ ste-ux500-samsung-codina.dtb \ + ste-ux500-samsung-codina-tmo.dtb \ ste-ux500-samsung-skomer.dtb \ ste-ux500-samsung-kyle.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ @@ -1415,6 +1491,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zybo.dtb \ zynq-zybo-z7.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ + armada-370-c200-v2.dtb \ armada-370-db.dtb \ armada-370-dlink-dns327l.dtb \ armada-370-mirabox.dtb \ @@ -1492,6 +1569,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_MSTARV7) += \ mstar-infinity-msc313-breadbee_crust.dtb \ + mstar-infinity2m-ssd202d-100ask-dongshanpione.dtb \ + mstar-infinity2m-ssd202d-miyoo-mini.dtb \ + mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dtb \ mstar-infinity2m-ssd202d-ssd201htv2.dtb \ mstar-infinity2m-ssd202d-unitv2.dtb \ mstar-infinity3-msc313e-breadbee.dtb \ @@ -1500,11 +1580,13 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ aspeed-ast2600-evb-a1.dtb \ aspeed-ast2600-evb.dtb \ + aspeed-bmc-amd-daytonax.dtb \ aspeed-bmc-amd-ethanolx.dtb \ aspeed-bmc-ampere-mtjade.dtb \ - aspeed-bmc-arm-centriq2400-rep.dtb \ + aspeed-bmc-ampere-mtmitchell.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ + aspeed-bmc-asrock-romed8hm3.dtb \ aspeed-bmc-bytedance-g220a.dtb \ aspeed-bmc-facebook-bletchley.dtb \ aspeed-bmc-facebook-cloudripper.dtb \ @@ -1541,7 +1623,9 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-opp-witherspoon.dtb \ aspeed-bmc-opp-zaius.dtb \ aspeed-bmc-portwell-neptune.dtb \ + aspeed-bmc-qcom-dc-scm-v1.dtb \ aspeed-bmc-quanta-q71l.dtb \ + aspeed-bmc-quanta-s6q.dtb \ aspeed-bmc-supermicro-x11spi.dtb \ aspeed-bmc-inventec-transformers.dtb \ aspeed-bmc-tyan-s7106.dtb \ diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi index 3b0675a1c460..4be9887033f9 100644 --- a/arch/arm/boot/dts/alpine.dtsi +++ b/arch/arm/boot/dts/alpine.dtsi @@ -154,7 +154,7 @@ reg = <0x0 0xfbc00000 0x0 0x100000>; interrupt-map-mask = <0xf800 0 0 7>; /* Add legacy interrupts for SATA devices only */ - interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, + interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, <0x4800 0 0 1 &gic 0 44 4>; /* 32 bit non prefetchable memory space */ diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts index daf4cb398070..75992eec830f 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts @@ -81,3 +81,147 @@ pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "NC", + "NC", + "I2C1_SDA", + "I2C1_SCL", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "UART1_CTSN", + "UART1_RTSN", + "UART1_RX", + "UART1_TX", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "NC", + "RMII1_TXD1", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "RMII1_TXD0", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "NC", + "NC", + "CONSOLE_RX", + "CONSOLE_TX", + "NC", + "NC", + "NC", + "SD_CD", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "RMII1_RXD1", + "RMII1_RXD0", + "UART1_DTR", + "UART1_DSR", + "UART1_DCD", + "UART1_RI", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "RMII1_CRS_DV", + "RMII1_RXER", + "RMII1_TXEN", + "NC", + "NC", + "NC", + "WLAN_IRQ", + "WLAN_EN", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "ModeA0", + "ModeA1", + "ModeA2", + "ModeA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts index 2123bd589484..087e084506d2 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts @@ -91,6 +91,10 @@ interrupts = <20 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&tca6416_pins>; + gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", + "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", + "ModeA0", "ModeA1", "ModeA2", "ModeA3", + "ModeB0", "ModeB1", "ModeB2", "ModeB3"; }; }; @@ -123,3 +127,147 @@ pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; }; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "UART2_RX", + "UART2_TX", + "I2C1_SDA", + "I2C1_SCL", + "WLAN_BTN", + "W_DISABLE", + "NC", + "NC", + "NC", + "NC", + "UART1_CTSN", + "UART1_RTSN", + "UART1_RX", + "UART1_TX", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "TCA6416_INT", + "RMII1_TXD1", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "RMII1_TXD0", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "NC", + "NC", + "CONSOLE_RX", + "CONSOLE_TX", + "UART2_DTR", + "UART2_DSR", + "UART2_DCD", + "UART2_RI", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SD_CD", + "SD_WP", + "RMII1_RXD1", + "RMII1_RXD0", + "UART1_DTR", + "UART1_DSR", + "UART1_DCD", + "UART1_RI", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "RMII1_CRS_DV", + "RMII1_RXER", + "RMII1_TXEN", + "3G_PWR_EN", + "UART2_CTSN", + "UART2_RTSN", + "WLAN_IRQ", + "WLAN_EN", + "NC", + "NC", + "NC", + "NC", + "USB1_DRVVBUS", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts index 2f3872dbf4f4..faeb39aab60a 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts @@ -99,6 +99,10 @@ interrupts = <20 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&tca6416_pins>; + gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", + "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", + "ModeA0", "ModeA1", "ModeA2", "ModeA3", + "ModeB0", "ModeB1", "ModeB2", "ModeB3"; }; }; @@ -147,3 +151,147 @@ pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; }; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "UART2_RX", + "UART2_TX", + "I2C1_SDA", + "I2C1_SCL", + "WLAN_BTN", + "W_DISABLE", + "NC", + "NC", + "NC", + "NC", + "UART1_CTSN", + "UART1_RTSN", + "UART1_RX", + "UART1_TX", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "TCA6416_INT", + "RMII1_TXD1", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "RMII1_TXD0", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "DCAN1_TX", + "DCAN1_RX", + "CONSOLE_RX", + "CONSOLE_TX", + "UART2_DTR", + "UART2_DSR", + "UART2_DCD", + "UART2_RI", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SD_CD", + "SD_WP", + "RMII1_RXD1", + "RMII1_RXD0", + "UART1_DTR", + "UART1_DSR", + "UART1_DCD", + "UART1_RI", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "RMII1_CRS_DV", + "RMII1_RXER", + "RMII1_TXEN", + "3G_PWR_EN", + "UART2_CTSN", + "UART2_RTSN", + "WLAN_IRQ", + "WLAN_EN", + "NC", + "NC", + "NC", + "NC", + "USB1_DRVVBUS", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index 366702630290..6161c8929a78 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -197,7 +197,7 @@ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; - ti,nand-xfer-type = "polled"; + ti,nand-xfer-type = "prefetch-dma"; gpmc,device-nand = "true"; gpmc,device-width = <1>; @@ -285,7 +285,7 @@ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; + regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 56ae5095a5b8..02e04a12a270 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -405,3 +405,7 @@ &pruss_tm { status = "okay"; }; + +&wkup_m3_ipc { + firmware-name = "am335x-bone-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts index c72b09ab8da0..207d2b63e0eb 100644 --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts +++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts @@ -19,7 +19,7 @@ regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - startup-delay-us= <70000>; + startup-delay-us = <70000>; /* WL_EN */ gpio = <&gpio3 9 0>; diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 9312197316f0..b956e2f60fe0 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -168,3 +168,7 @@ "NC", "NC"; }; + +&baseboard_eeprom { + vcc-supply = <&ldo4_reg>; +}; diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index 147c00de3795..34579e98636e 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -106,7 +106,7 @@ regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - startup-delay-us= <70000>; + startup-delay-us = <70000>; /* WL_EN */ gpio = <&gpio3 9 0>; diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts index 215f279e476b..d388cffa1a4d 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts +++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts @@ -18,7 +18,7 @@ regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - startup-delay-us= <70000>; + startup-delay-us = <70000>; /* WL_EN */ gpio = <&gpio0 26 0>; diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index d9f003d886bf..993b13420699 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -325,7 +325,7 @@ status = "okay"; tlv320aic23: codec@1a { compatible = "ti,tlv320aic23"; reg = <0x1a>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; }; @@ -491,7 +491,7 @@ status = "okay"; tx-num-evt = <1>; rx-num-evt = <1>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 659e99eabe66..25c6ac9913d2 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -92,20 +92,18 @@ 0x0201006c>; /* DOWN */ }; - gpio_keys: volume_keys0 { + gpio_keys: volume-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - switch9 { + switch-9 { label = "volume-up"; linux,code = <115>; gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; wakeup-source; }; - switch10 { + switch-10 { label = "volume-down"; linux,code = <114>; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; @@ -782,3 +780,7 @@ &pruss_tm { status = "okay"; }; + +&wkup_m3_ipc { + firmware-name = "am335x-evm-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index a2db65538e51..9c458e5a95b7 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -719,3 +719,7 @@ &pruss_tm { status = "okay"; }; + +&wkup_m3_ipc { + firmware-name = "am335x-evm-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 1918766c1f80..f6356266564c 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -29,39 +29,42 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; + guardian_buttons: gpio-keys { pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins>; + pinctrl-0 = <&guardian_button_pins>; + compatible = "gpio-keys"; + + select-button { + label = "guardian-select-button"; + linux,code = <KEY_5>; + gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + wakeup-source; + }; - button21 { + power-button { label = "guardian-power-button"; linux,code = <KEY_POWER>; - gpios = <&gpio2 21 0>; + gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; wakeup-source; }; }; - leds { - compatible = "gpio-leds"; + guardian_leds: gpio-leds { pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; + pinctrl-0 = <&guardian_led_pins>; + compatible = "gpio-leds"; - led1 { - label = "green:heartbeat"; - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + life-led { + label = "guardian:life-led"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; + }; - led2 { - label = "green:mmc0"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; }; panel { @@ -100,20 +103,36 @@ }; - pwm7: dmtimer-pwm { + guardian_beeper: dmtimer-pwm@7 { compatible = "ti,omap-dmtimer-pwm"; ti,timers = <&timer7>; pinctrl-names = "default"; - pinctrl-0 = <&dmtimer7_pins>; + pinctrl-0 = <&guardian_beeper_pins>; ti,clock-source = <0x01>; }; - vmmcsd_fixed: regulator-3v3 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + mt_keypad: mt_keypad@0 { + compatible = "gpio-mt-keypad"; + debounce-delay-ms = <10>; + col-scan-delay-us = <2>; + keypad,num-lines = <5>; + linux,no-autorepeat; + gpio-activelow; + line-gpios = < + &gpio1 24 GPIO_ACTIVE_LOW /*gpio_56*/ + &gpio1 23 GPIO_ACTIVE_LOW /*gpio_55*/ + &gpio1 22 GPIO_ACTIVE_LOW /*gpio_54*/ + &gpio1 20 GPIO_ACTIVE_LOW /*gpio_52*/ + &gpio1 16 GPIO_ACTIVE_LOW /*gpio_48*/ + >; + }; }; &elm { @@ -133,28 +152,29 @@ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; + gpmc,cs-rd-off-ns = <30>; + gpmc,cs-wr-off-ns = <30>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; + gpmc,we-off-ns = <15>; + gpmc,oe-on-ns = <1>; + gpmc,oe-off-ns = <15>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <30>; + gpmc,wr-cycle-ns = <30>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; + gpmc,wr-access-ns = <0>; gpmc,wr-data-mux-bus-ns = <0>; /* @@ -198,18 +218,33 @@ }; partition@6 { - label = "u-boot-env"; - reg = <0x300000 0x40000>; + label = "u-boot-2"; + reg = <0x300000 0x100000>; }; partition@7 { - label = "u-boot-env.backup1"; - reg = <0x340000 0x40000>; + label = "u-boot-2.backup1"; + reg = <0x400000 0x100000>; }; partition@8 { + label = "u-boot-env"; + reg = <0x500000 0x40000>; + }; + + partition@9 { + label = "u-boot-env.backup1"; + reg = <0x540000 0x40000>; + }; + + partition@10 { + label = "splash-screen"; + reg = <0x580000 0x40000>; + }; + + partition@11 { label = "UBI"; - reg = <0x380000 0x1fc80000>; + reg = <0x5c0000 0x1fa40000>; }; }; }; @@ -228,6 +263,11 @@ &lcdc { blue-and-red-wiring = "crossed"; status = "okay"; + port { + lcdc_0: endpoint@0 { + remote-endpoint = <0>; + }; + }; }; &mmc1 { @@ -242,7 +282,6 @@ &rtc { clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; - system-power-controller; }; &spi0 { @@ -255,14 +294,34 @@ #include "tps65217.dtsi" &tps { + /* + * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only + * mode") at poweroff. Most BeagleBone versions do not support RTC-only + * mode and risk hardware damage if this mode is entered. + * + * For details, see linux-omap mailing list May 2015 thread + * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller + * In particular, messages: + * http://www.spinics.net/lists/linux-omap/msg118585.html + * http://www.spinics.net/lists/linux-omap/msg118615.html + * + * You can override this later with + * &tps { /delete-property/ ti,pmic-shutdown-controller; } + * if you want to use RTC-only mode and made sure you are not affected + * by the hardware problems. (Tip: double-check by performing a current + * measurement after shutdown: it should be less than 1 mA.) + */ ti,pmic-shutdown-controller; interrupt-parent = <&intc>; interrupts = <7>; /* NMI */ backlight { isel = <1>; /* 1 - ISET1, 2 ISET2 */ - fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ - default-brightness = <100>; + fdim = <500>; /* TPS65217_BL_FDIM_500HZ */ + default-brightness = <50>; + /* 1(on) - enable current sink, while initialization */ + /* 0(off) - disable current sink, while initialization */ + isink-en = <1>; }; regulators { @@ -272,6 +331,7 @@ }; dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1351500>; @@ -280,6 +340,7 @@ }; dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <925000>; regulator-max-microvolt = <1150000>; @@ -319,171 +380,364 @@ }; }; +&gpio0 { + gpio-line-names = + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MirxWakeup", + "", + ""; +}; + +&gpio3 { + ti,gpio-always-on; + ti,no-reset-on-init; + gpio-line-names = + "", + "MirxBtReset", + "", + "CcVolAdcEn", + "MirxBlePause", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AspEn", + "", + "", + "", + "", + "", + "", + "BatVolAdcEn", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + &usb0 { dr_mode = "peripheral"; }; &usb1 { dr_mode = "host"; + /delete-property/dmas; + /delete-property/dma-names; }; &am33xx_pinmux { pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin &gpio_pins>; + pinctrl-0 = <&clkout2_pin &guardian_interface_pins>; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < + /* xdma_event_intr1.clkout2 */ AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) >; }; - dmtimer7_pins: pinmux_dmtimer7_pins { + guardian_interface_pins: pinmux_interface_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) + /* ADC_BATSENSE_EN */ + /* (A14) MCASP0_AHCLKx.gpio3[21] */ + AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* ADC_COINCELL_EN */ + /* (J16) MII1_TX_EN.gpio3[3] */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* ASP_ENABLE */ + /* (A13) MCASP0_ACLKx.gpio3[14] */ + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7) + /* (D16) uart1_rxd.uart1_rxd */ + AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7) + /* (D15) uart1_txd.uart1_txd */ + AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7) + /*SWITCH-OFF_3V6*/ + /* (M18) gpio0[1] */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7) + /* MIRACULIX */ + /* (H17) gmii1_crs.gpio3[1] */ + AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* (H18) rmii1_refclk.gpio0[29] */ + AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) + /* (J18) gmii1_txd3.gpio0[16] */ + AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7 ) + /* (J17) gmii1_rxdv.gpio3[4] */ + AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) >; }; - gpio_keys_pins: pinmux_gpio_keys_pins { + guardian_beeper_pins: pinmux_dmtimer7_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) + AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */ >; }; - gpio_pins: pinmux_gpio_pins { + guardian_button_pins: pinmux_guardian_button_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ + AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */ >; }; + i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + led_bl_pins: gpio_led_bl_pins { + pinctrl-single,pins = < + /* P9_14, gpmc_a[2].GPIO1[18] (backlight control) */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7) >; }; lcd_disen_pins: pinmux_lcd_disen_pins { pinctrl-single,pins = < + /* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */ AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) >; }; lcd_pins_default: pinmux_lcd_pins_default { pinctrl-single,pins = < + /* (U10) gpmc_ad8.lcd_data23 */ AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (T10) gpmc_ad9.lcd_data22 */ AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (T11) gpmc_ad10.lcd_data21 */ AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (U12) gpmc_ad11.lcd_data20 */ AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (T12) gpmc_ad12.lcd_data19 */ AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (R12) gpmc_ad13.lcd_data18 */ AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (V13) gpmc_ad14.lcd_data17 */ AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* (U13) gpmc_ad15.lcd_data16 */ AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) + /* lcd_data0.lcd_data0 */ AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data1.lcd_data1 */ AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data2.lcd_data2 */ AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data3.lcd_data3 */ AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data4.lcd_data4 */ AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data5.lcd_data5 */ AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data6.lcd_data6 */ AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data7.lcd_data7 */ AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data8.lcd_data8 */ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data9.lcd_data9 */ AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data10.lcd_data10 */ AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data11.lcd_data11 */ AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data12.lcd_data12 */ AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data13.lcd_data13 */ AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data14.lcd_data14 */ AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_data15.lcd_data15 */ AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_vsync.lcd_vsync */ AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_hsync.lcd_hsync */ AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_pclk.lcd_pclk */ AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + /* lcd_ac_bias_en.lcd_ac_bias_en */ AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) >; }; lcd_pins_sleep: pinmux_lcd_pins_sleep { pinctrl-single,pins = < + /* lcd_data0.lcd_data0 */ AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data1.lcd_data1 */ AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data2.lcd_data2 */ AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data3.lcd_data3 */ AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data4.lcd_data4 */ AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data5.lcd_data5 */ AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data6.lcd_data6 */ AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data7.lcd_data7 */ AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data8.lcd_data8 */ AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data9.lcd_data9 */ AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data10.lcd_data10 */ AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data11.lcd_data11 */ AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data12.lcd_data12 */ AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data13.lcd_data13 */ AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data14.lcd_data14 */ AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_data15.lcd_data15 */ AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_vsync.lcd_vsync */ AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_hsync.lcd_hsync */ AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_pclk.lcd_pclk */ AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + /* lcd_ac_bias_en.lcd_ac_bias_en */ AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) >; }; - leds_pins: pinmux_leds_pins { + guardian_led_pins: pinmux_guardian_led_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7) + AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < + /* SPI0_CLK - spi0_clk.spi */ AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + /* SPI0_MOSI - spi0_d0.spi0 */ AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) + /* SPI0_MISO - spi0_d1.spi0 */ AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) + /* SPI0_CS0 - spi */ AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < + /* uart0_rxd.uart0_rxd */ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) + /* uart0_txd.uart0_txd */ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) >; }; + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + /* K18 uart2_rxd.mirx_txd */ + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1) + /* L18 uart2_txd.mirx_rxd */ + AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) + >; + }; + nandflash_pins: pinmux_nandflash_pins { pinctrl-single,pins = < + /* (U7) gpmc_ad0.gpmc_ad0 */ AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) + /* (V7) gpmc_ad1.gpmc_ad1 */ AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) + /* (R8) gpmc_ad2.gpmc_ad2 */ AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) + /* (T8) gpmc_ad3.gpmc_ad3 */ AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) + /* (U8) gpmc_ad4.gpmc_ad4 */ AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) + /* (V8) gpmc_ad5.gpmc_ad5 */ AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) + /* (R9) gpmc_ad6.gpmc_ad6 */ AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) + /* (T9) gpmc_ad7.gpmc_ad7 */ AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) + /* (T17) gpmc_wait0.gpmc_wait0 */ AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) + /* (U17) gpmc_wpn.gpmc_wpn */ AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) + /* (V6) gpmc_csn0.gpmc_csn0 */ AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) + /* (R7) gpmc_advn_ale.gpmc_advn_ale */ AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) + /* (T7) gpmc_oen_ren.gpmc_oen_ren */ AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) + /* (U6) gpmc_wen.gpmc_wen */ AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) + /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */ AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) >; }; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi index 11e8f64b6606..7b40ca9483ca 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi @@ -166,10 +166,8 @@ &buttons { pinctrl-names = "default"; pinctrl-0 = <&push_button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + button-0 { label = "push_button"; linux,code = <0x100>; gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; @@ -182,7 +180,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - m25p80@0 { + flash@0 { compatible = "mx25l6405d"; spi-max-frequency = <40000000>; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi index a7269b90d795..e0364adb8393 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi @@ -378,10 +378,8 @@ &buttons { pinctrl-names = "default"; pinctrl-0 = <&push_button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + button-0 { label = "push_button"; linux,code = <0x100>; gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; @@ -394,7 +392,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - m25p80@0 { + flash@0 { compatible = "mx25l6405d"; spi-max-frequency = <40000000>; diff --git a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi index 245c35f41cdf..6eea18b29355 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi +++ b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi @@ -27,6 +27,13 @@ reg = <0x80000000 0x10000000>; }; + clk32k: clk32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + + #clock-cells = <0>; + }; + vdd_mod: vdd_mod_reg { compatible = "regulator-fixed"; regulator-name = "vdd-mod"; @@ -124,9 +131,6 @@ gpmc,wr-data-mux-bus-ns = <0>; ti,elm-id = <&elm>; ti,nand-ecc-opt = "bch8"; - - #address-cells = <1>; - #size-cells = <1>; }; }; @@ -149,6 +153,8 @@ }; &rtc { + clocks = <&clk32k>; + clock-names = "ext-clk"; system-power-controller; }; diff --git a/arch/arm/boot/dts/am335x-myirtech-myd.dts b/arch/arm/boot/dts/am335x-myirtech-myd.dts index 1479fd95dec2..9d81d4cc6890 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myd.dts +++ b/arch/arm/boot/dts/am335x-myirtech-myd.dts @@ -227,14 +227,20 @@ }; &nand0 { - partition@0 { - label = "MLO"; - reg = <0x00000 0x20000>; - }; + nand_parts: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@20000 { - label = "boot"; - reg = <0x20000 0x80000>; + partition@0 { + label = "MLO"; + reg = <0x00000 0x20000>; + }; + + partition@80000 { + label = "boot"; + reg = <0x80000 0x100000>; + }; }; }; diff --git a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts b/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts index 57e756b0f192..2e049489ac06 100644 --- a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts +++ b/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts @@ -85,3 +85,147 @@ status = "okay"; }; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "NC", + "NC", + "I2C1_SDA", + "I2C1_SCL", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "can_data", + "can_error", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "NC", + "NC", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "NC", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "DCAN1_TX", + "DCAN1_RX", + "CONSOLE_RX", + "CONSOLE_TX", + "NC", + "NC", + "NC", + "NC", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "WLAN_IRQ", + "WLAN_EN", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "ModeA0", + "ModeA1", + "ModeA2", + "ModeA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts b/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts index c6cc1c6218a9..6ed886c3306b 100644 --- a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts +++ b/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts @@ -93,3 +93,147 @@ ti,dual-emac-pvid = <2>; phy-handle = <&phy1>; }; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "UART2_RX", + "UART2_TX", + "I2C1_SDA", + "I2C1_SCL", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "UART1_CTSN", + "UART1_RTSN", + "UART1_RX", + "UART1_TX", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "NC", + "NC", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "NC", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "NC", + "NC", + "CONSOLE_RX", + "CONSOLE_TX", + "UART2_DTR", + "UART2_DSR", + "UART2_DCD", + "UART2_RI", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "NC", + "NC", + "UART1_DTR", + "UART1_DSR", + "UART1_DCD", + "UART1_RI", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "NC", + "NC", + "NC", + "NC", + "UART2_CTSN", + "UART2_RTSN", + "WLAN_IRQ", + "WLAN_EN", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "ModeA0", + "ModeA1", + "ModeA2", + "ModeA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts b/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts index 96dffd3ffd85..ad3adc7679f9 100644 --- a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts +++ b/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts @@ -71,6 +71,10 @@ interrupts = <20 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&tca6416_pins>; + gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", + "GP_IN4", "GP_IN5", "GP_IN6", "GP_IN7", + "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", + "GP_OUT4", "GP_OUT5", "GP_OUT6", "GP_OUT7"; }; }; @@ -86,6 +90,10 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; + gpio-line-names = "CH1_M0", "CH1_M1", "CH1_M2", "CH1_M3", + "CH2_M0", "CH2_M1", "CH2_M2", "CH2_M3", + "CH3_M0", "CH3_M1", "CH3_M2", "CH3_M3", + "CH4_M0", "CH4_M1", "CH4_M2", "CH4_M3"; }; tca6416c: gpio@21 { @@ -93,6 +101,10 @@ reg = <0x21>; gpio-controller; #gpio-cells = <2>; + gpio-line-names = "CH5_M0", "CH5_M1", "CH5_M2", "CH5_M3", + "CH6_M0", "CH6_M1", "CH6_M2", "CH6_M3", + "CH7_M0", "CH7_M1", "CH7_M2", "CH7_M3", + "CH8_M0", "CH8_M1", "CH8_M2", "CH8_M3"; }; }; @@ -113,3 +125,147 @@ ti,dual-emac-pvid = <2>; phy-handle = <&phy1>; }; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "NC", + "NC", + "I2C1_SDA", + "I2C1_SCL", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "I2C2_SDA", + "I2C2_SCL", + "NC", + "NC", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "NC", + "NC", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "NC", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "NC", + "NC", + "CONSOLE_RX", + "CONSOLE_TX", + "SW2_0_alt", + "SW2_1_alt", + "SW2_2_alt", + "SW2_3_alt", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "NC", + "NC", + "NC", + "3G_PWR_EN", + "NC", + "NC", + "WLAN_IRQ", + "WLAN_EN", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/am335x-pcm-953.dtsi index 124026fa0d09..dae448040a97 100644 --- a/arch/arm/boot/dts/am335x-pcm-953.dtsi +++ b/arch/arm/boot/dts/am335x-pcm-953.dtsi @@ -54,14 +54,14 @@ pinctrl-names = "default"; pinctrl-0 = <&user_buttons_pins>; - button@0 { + button-0 { label = "home"; linux,code = <KEY_HOME>; gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; wakeup-source; }; - button@1 { + button-1 { label = "menu"; linux,code = <KEY_MENU>; gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/am335x-pdu001.dts index b793beeab245..ce6cc2b96654 100644 --- a/arch/arm/boot/dts/am335x-pdu001.dts +++ b/arch/arm/boot/dts/am335x-pdu001.dts @@ -353,7 +353,7 @@ }; }; - mcp79400: mcp79400@6f { + mcp79400: rtc@6f { compatible = "microchip,mcp7940x"; reg = <0x6f>; }; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index b5e88e627bc1..8691eec33b61 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -596,24 +596,22 @@ &buttons { pinctrl-names = "default"; pinctrl-0 = <&user_buttons_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { + button-0 { label = "home"; linux,code = <KEY_HOME>; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; wakeup-source; }; - button1 { + button-1 { label = "menu"; linux,code = <KEY_MENU>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; wakeup-source; }; - buttons2 { + button-2 { label = "power"; linux,code = <KEY_POWER>; gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index f65cd1331315..e2cec1ffaa4c 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -331,7 +331,7 @@ pinctrl-0 = <&spi0_pins>; status = "okay"; - serial_flash: m25p80@0 { + serial_flash: flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <48000000>; reg = <0x0>; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts new file mode 100644 index 000000000000..a2676d10c24a --- /dev/null +++ b/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Sancloud Ltd + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include "am335x-sancloud-bbe-common.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "SanCloud BeagleBone Enhanced Extended WiFi"; + compatible = "sancloud,am335x-boneenhanced", + "ti,am335x-bone-black", + "ti,am335x-bone", + "ti,am33xx"; + + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + }; +}; + +&am33xx_pinmux { + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + /* gpmc_a9.gpio1_25: RADIO_EN */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_OUTPUT_PULLUP, MUX_MODE7) + + /* gpmc_ad12.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_ad13.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_ad14.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_ad15.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_clk.mmc2_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) + >; + }; + + bluetooth_pins: pinmux_bluetooth_pins { + pinctrl-single,pins = < + /* event_intr0.gpio0_19 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + /* uart1_rxd */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + + /* uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) + + /* uart1_ctsn */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + + /* uart1_rtsn */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; +}; + +&i2c2 { + status = "disabled"; +}; + +&mmc3 { + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + ti,needs-special-hs-handling; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + clock-frequency = <50000000>; + max-frequency = <50000000>; +}; + +&uart1 { + status = "okay"; + + bluetooth { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins &bluetooth_pins>; + compatible = "qcom,qca6174-bt"; + enable-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; + interrupt-parent = <&gpio0>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + }; +}; diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index 6b9877560741..c497200f9cb0 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -36,10 +36,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - back_button { + back-button { label = "Back Button"; gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; linux,code = <KEY_BACK>; @@ -47,7 +47,7 @@ wakeup-source; }; - front_button { + front-button { label = "Front Button"; gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; linux,code = <KEY_FRONT>; diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index 6516907ed579..73b5d1a024bd 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -588,7 +588,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - flash: n25q032@1 { + flash: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q032"; diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi index 673159d93a6a..f957fea8208e 100644 --- a/arch/arm/boot/dts/am335x-wega.dtsi +++ b/arch/arm/boot/dts/am335x-wega.dtsi @@ -55,7 +55,7 @@ 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */ >; tx-num-evt = <16>; - rt-num-evt = <16>; + rx-num-evt = <16>; status = "okay"; }; diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index b7b7106f2dee..d34483ae1778 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -5,251 +5,288 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &scm_clocks { - sys_clkin_ck: sys_clkin_ck@40 { + sys_clkin_ck: clock-sys-clkin-22@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin_ck"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <22>; reg = <0x0040>; }; - adc_tsc_fck: adc_tsc_fck { + adc_tsc_fck: clock-adc-tsc-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "adc_tsc_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dcan0_fck: dcan0_fck { + dcan0_fck: clock-dcan0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dcan0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dcan1_fck: dcan1_fck { + dcan1_fck: clock-dcan1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dcan1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - mcasp0_fck: mcasp0_fck { + mcasp0_fck: clock-mcasp0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mcasp0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - mcasp1_fck: mcasp1_fck { + mcasp1_fck: clock-mcasp1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mcasp1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - smartreflex0_fck: smartreflex0_fck { + smartreflex0_fck: clock-smartreflex0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - smartreflex1_fck: smartreflex1_fck { + smartreflex1_fck: clock-smartreflex1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - sha0_fck: sha0_fck { + sha0_fck: clock-sha0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sha0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - aes0_fck: aes0_fck { + aes0_fck: clock-aes0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "aes0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - rng_fck: rng_fck { + rng_fck: clock-rng-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "rng_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; - reg = <0x0664>; - }; + clock@664 { + compatible = "ti,clksel"; + reg = <0x664>; + #clock-cells = <2>; + #address-cells = <0>; - ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; - reg = <0x0664>; - }; + ehrpwm0_tbclk: clock-ehrpwm0-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <0>; + }; - ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; - reg = <0x0664>; + ehrpwm1_tbclk: clock-ehrpwm1-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <1>; + }; + + ehrpwm2_tbclk: clock-ehrpwm2-tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; + clocks = <&l4ls_gclk>; + ti,bit-shift = <2>; + }; }; }; &prcm_clocks { - clk_32768_ck: clk_32768_ck { + clk_32768_ck: clock-clk-32768 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_32768_ck"; clock-frequency = <32768>; }; - clk_rc32k_ck: clk_rc32k_ck { + clk_rc32k_ck: clock-clk-rc32k { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_rc32k_ck"; clock-frequency = <32000>; }; - virt_19200000_ck: virt_19200000_ck { + virt_19200000_ck: clock-virt-19200000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; - virt_24000000_ck: virt_24000000_ck { + virt_24000000_ck: clock-virt-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_24000000_ck"; clock-frequency = <24000000>; }; - virt_25000000_ck: virt_25000000_ck { + virt_25000000_ck: clock-virt-25000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_25000000_ck"; clock-frequency = <25000000>; }; - virt_26000000_ck: virt_26000000_ck { + virt_26000000_ck: clock-virt-26000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; - tclkin_ck: tclkin_ck { + tclkin_ck: clock-tclkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "tclkin_ck"; clock-frequency = <12000000>; }; - dpll_core_ck: dpll_core_ck@490 { + dpll_core_ck: clock@490 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; }; - dpll_core_x2_ck: dpll_core_x2_ck { + dpll_core_x2_ck: clock-dpll-core-x2 { #clock-cells = <0>; compatible = "ti,am3-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; - dpll_core_m4_ck: dpll_core_m4_ck@480 { + dpll_core_m4_ck: clock-dpll-core-m4@480 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m4_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0480>; ti,index-starts-at-one; }; - dpll_core_m5_ck: dpll_core_m5_ck@484 { + dpll_core_m5_ck: clock-dpll-core-m5@484 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m5_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0484>; ti,index-starts-at-one; }; - dpll_core_m6_ck: dpll_core_m6_ck@4d8 { + dpll_core_m6_ck: clock-dpll-core-m6@4d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m6_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x04d8>; ti,index-starts-at-one; }; - dpll_mpu_ck: dpll_mpu_ck@488 { + dpll_mpu_ck: clock@488 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { + dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; reg = <0x04a8>; ti,index-starts-at-one; }; - dpll_ddr_ck: dpll_ddr_ck@494 { + dpll_ddr_ck: clock@494 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; + clock-output-names = "dpll_ddr_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { + dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m2_ck"; clocks = <&dpll_ddr_ck>; ti,max-div = <31>; reg = <0x04a0>; ti,index-starts-at-one; }; - dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { + dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_ddr_m2_div2_ck"; clocks = <&dpll_ddr_m2_ck>; clock-mult = <1>; clock-div = <2>; }; - dpll_disp_ck: dpll_disp_ck@498 { + dpll_disp_ck: clock@498 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; + clock-output-names = "dpll_disp_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; }; - dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { + dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_disp_m2_ck"; clocks = <&dpll_disp_ck>; ti,max-div = <31>; reg = <0x04a4>; @@ -257,418 +294,484 @@ ti,set-rate-parent; }; - dpll_per_ck: dpll_per_ck@48c { + dpll_per_ck: clock@48c { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; }; - dpll_per_m2_ck: dpll_per_m2_ck@4ac { + dpll_per_m2_ck: clock-dpll-per-m2@4ac { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <31>; reg = <0x04ac>; ti,index-starts-at-one; }; - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { + dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { + dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_ck"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - clk_24mhz: clk_24mhz { + clk_24mhz: clock-clk-24mhz { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "clk_24mhz"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <8>; }; - clkdiv32k_ck: clkdiv32k_ck { + clkdiv32k_ck: clock-clkdiv32k { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "clkdiv32k_ck"; clocks = <&clk_24mhz>; clock-mult = <1>; clock-div = <732>; }; - l3_gclk: l3_gclk { + l3_gclk: clock-l3-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - pruss_ocp_gclk: pruss_ocp_gclk@530 { + pruss_ocp_gclk: clock-pruss-ocp-gclk@530 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "pruss_ocp_gclk"; clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; reg = <0x0530>; }; - mmu_fck: mmu_fck@914 { + mmu_fck: clock-mmu-fck-1@914 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "mmu_fck"; clocks = <&dpll_core_m4_ck>; ti,bit-shift = <1>; reg = <0x0914>; }; - timer1_fck: timer1_fck@528 { + timer1_fck: clock-timer1-fck@528 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer1_fck"; clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; reg = <0x0528>; }; - timer2_fck: timer2_fck@508 { + timer2_fck: clock-timer2-fck@508 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer2_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0508>; }; - timer3_fck: timer3_fck@50c { + timer3_fck: clock-timer3-fck@50c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer3_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x050c>; }; - timer4_fck: timer4_fck@510 { + timer4_fck: clock-timer4-fck@510 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer4_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0510>; }; - timer5_fck: timer5_fck@518 { + timer5_fck: clock-timer5-fck@518 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer5_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0518>; }; - timer6_fck: timer6_fck@51c { + timer6_fck: clock-timer6-fck@51c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer6_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x051c>; }; - timer7_fck: timer7_fck@504 { + timer7_fck: clock-timer7-fck@504 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer7_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0504>; }; - usbotg_fck: usbotg_fck@47c { + usbotg_fck: clock-usbotg-fck-8@47c { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usbotg_fck"; clocks = <&dpll_per_ck>; ti,bit-shift = <8>; reg = <0x047c>; }; - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { + dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_core_m4_div2_ck"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <2>; }; - ieee5000_fck: ieee5000_fck@e4 { + ieee5000_fck: clock-ieee5000-fck-1@e4 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ieee5000_fck"; clocks = <&dpll_core_m4_div2_ck>; ti,bit-shift = <1>; reg = <0x00e4>; }; - wdt1_fck: wdt1_fck@538 { + wdt1_fck: clock-wdt1-fck@538 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "wdt1_fck"; clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0538>; }; - l4_rtc_gclk: l4_rtc_gclk { + l4_rtc_gclk: clock-l4-rtc-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4_rtc_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <2>; }; - l4hs_gclk: l4hs_gclk { + l4hs_gclk: clock-l4hs-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4hs_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - l3s_gclk: l3s_gclk { + l3s_gclk: clock-l3s-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3s_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - l4fw_gclk: l4fw_gclk { + l4fw_gclk: clock-l4fw-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4fw_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - l4ls_gclk: l4ls_gclk { + l4ls_gclk: clock-l4ls-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4ls_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - sysclk_div_ck: sysclk_div_ck { + sysclk_div_ck: clock-sysclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sysclk_div_ck"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - cpsw_125mhz_gclk: cpsw_125mhz_gclk { + cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_125mhz_gclk"; clocks = <&dpll_core_m5_ck>; clock-mult = <1>; clock-div = <2>; }; - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 { + cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "cpsw_cpts_rft_clk"; clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; reg = <0x0520>; }; - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c { + gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpio0_dbclk_mux_ck"; clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x053c>; }; - lcd_gclk: lcd_gclk@534 { + lcd_gclk: clock-lcd-gclk@534 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "lcd_gclk"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; reg = <0x0534>; ti,set-rate-parent; }; - mmc_clk: mmc_clk { + mmc_clk: clock-mmc { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mmc_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <2>; }; - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; - ti,bit-shift = <1>; - reg = <0x052c>; - }; + clock@52c { + compatible = "ti,clksel"; + reg = <0x52c>; + #clock-cells = <2>; + #address-cells = <0>; - gfx_fck_div_ck: gfx_fck_div_ck@52c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&gfx_fclk_clksel_ck>; - reg = <0x052c>; - ti,max-div = <2>; - }; + gfx_fclk_clksel_ck: clock-gfx-fclk-clksel { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "gfx_fclk_clksel_ck"; + clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + }; - sysclkout_pre_ck: sysclkout_pre_ck@700 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; - reg = <0x0700>; + gfx_fck_div_ck: clock-gfx-fck-div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "gfx_fck_div_ck"; + clocks = <&gfx_fclk_clksel_ck>; + ti,max-div = <2>; + }; }; - clkout2_div_ck: clkout2_div_ck@700 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sysclkout_pre_ck>; - ti,bit-shift = <3>; - ti,max-div = <8>; - reg = <0x0700>; - }; + clock@700 { + compatible = "ti,clksel"; + reg = <0x700>; + #clock-cells = <2>; + #address-cells = <0>; - clkout2_ck: clkout2_ck@700 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout2_div_ck>; - ti,bit-shift = <7>; - reg = <0x0700>; + sysclkout_pre_ck: clock-sysclkout-pre { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "sysclkout_pre_ck"; + clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; + }; + + clkout2_div_ck: clock-clkout2-div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "clkout2_div_ck"; + clocks = <&sysclkout_pre_ck>; + ti,bit-shift = <3>; + ti,max-div = <8>; + }; + + clkout2_ck: clock-clkout2 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "clkout2_ck"; + clocks = <&clkout2_div_ck>; + ti,bit-shift = <7>; + }; }; }; &prcm { - per_cm: per-cm@0 { + per_cm: clock@0 { compatible = "ti,omap4-cm"; + clock-output-names = "per_cm"; reg = <0x0 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x400>; - l4ls_clkctrl: l4ls-clkctrl@38 { + l4ls_clkctrl: clock@38 { compatible = "ti,clkctrl"; + clock-output-names = "l4ls_clkctrl"; reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; #clock-cells = <2>; }; - l3s_clkctrl: l3s-clkctrl@1c { + l3s_clkctrl: clock@1c { compatible = "ti,clkctrl"; + clock-output-names = "l3s_clkctrl"; reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>; #clock-cells = <2>; }; - l3_clkctrl: l3-clkctrl@24 { + l3_clkctrl: clock@24 { compatible = "ti,clkctrl"; + clock-output-names = "l3_clkctrl"; reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; #clock-cells = <2>; }; - l4hs_clkctrl: l4hs-clkctrl@120 { + l4hs_clkctrl: clock@120 { compatible = "ti,clkctrl"; + clock-output-names = "l4hs_clkctrl"; reg = <0x120 0x4>; #clock-cells = <2>; }; - pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 { + pruss_ocp_clkctrl: clock@e8 { compatible = "ti,clkctrl"; + clock-output-names = "pruss_ocp_clkctrl"; reg = <0xe8 0x4>; #clock-cells = <2>; }; - cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 { + cpsw_125mhz_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "cpsw_125mhz_clkctrl"; reg = <0x0 0x18>; #clock-cells = <2>; }; - lcdc_clkctrl: lcdc-clkctrl@18 { + lcdc_clkctrl: clock@18 { compatible = "ti,clkctrl"; + clock-output-names = "lcdc_clkctrl"; reg = <0x18 0x4>; #clock-cells = <2>; }; - clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c { + clk_24mhz_clkctrl: clock@14c { compatible = "ti,clkctrl"; + clock-output-names = "clk_24mhz_clkctrl"; reg = <0x14c 0x4>; #clock-cells = <2>; }; }; - wkup_cm: wkup-cm@400 { + wkup_cm: clock@400 { compatible = "ti,omap4-cm"; + clock-output-names = "wkup_cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x400 0x100>; - l4_wkup_clkctrl: l4-wkup-clkctrl@0 { + l4_wkup_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_clkctrl"; reg = <0x0 0x10>, <0xb4 0x24>; #clock-cells = <2>; }; - l3_aon_clkctrl: l3-aon-clkctrl@14 { + l3_aon_clkctrl: clock@14 { compatible = "ti,clkctrl"; + clock-output-names = "l3_aon_clkctrl"; reg = <0x14 0x4>; #clock-cells = <2>; }; - l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 { + l4_wkup_aon_clkctrl: clock@b0 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_aon_clkctrl"; reg = <0xb0 0x4>; #clock-cells = <2>; }; }; - mpu_cm: mpu-cm@600 { + mpu_cm: clock@600 { compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; - mpu_clkctrl: mpu-clkctrl@0 { + mpu_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; reg = <0x0 0x8>; #clock-cells = <2>; }; }; - l4_rtc_cm: l4-rtc-cm@800 { + l4_rtc_cm: clock@800 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_rtc_cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x800 0x100>; - l4_rtc_clkctrl: l4-rtc-clkctrl@0 { + l4_rtc_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "l4_rtc_clkctrl"; reg = <0x0 0x4>; #clock-cells = <2>; }; }; - gfx_l3_cm: gfx-l3-cm@900 { + gfx_l3_cm: clock@900 { compatible = "ti,omap4-cm"; + clock-output-names = "gfx_l3_cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x900 0x100>; - gfx_l3_clkctrl: gfx-l3-clkctrl@0 { + gfx_l3_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "gfx_l3_clkctrl"; reg = <0x0 0x8>; #clock-cells = <2>; }; }; - l4_cefuse_cm: l4-cefuse-cm@a00 { + l4_cefuse_cm: clock@a00 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_cefuse_cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xa00 0x100>; - l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 { + l4_cefuse_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "l4_cefuse_clkctrl"; reg = <0x0 0x24>; #clock-cells = <2>; }; diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index c9629cb5ccd1..7e50fe633d8a 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -263,6 +263,8 @@ compatible = "ti,am3359-tscadc"; reg = <0x0 0x1000>; interrupts = <16>; + clocks = <&adc_tsc_fck>; + clock-names = "fck"; status = "disabled"; dmas = <&edma 53 0>, <&edma 57 0>; dma-names = "fifo0", "fifo1"; @@ -1500,8 +1502,7 @@ mmc1: mmc@0 { compatible = "ti,am335-sdhci"; ti,needs-special-reset; - dmas = <&edma_xbar 24 0 0 - &edma_xbar 25 0 0>; + dmas = <&edma 24 0>, <&edma 25 0>; dma-names = "tx", "rx"; interrupts = <64>; reg = <0x0 0x1000>; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index f6ec85d58dd1..32d397b3950b 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for AM33XX SoC * * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h> @@ -461,8 +458,11 @@ interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <30>; + dma-channels = <30>; #dma-requests = <256>; + dma-requests = <256>; }; }; diff --git a/arch/arm/boot/dts/am3517-evm-ui.dtsi b/arch/arm/boot/dts/am3517-evm-ui.dtsi index 7d8f32bf70db..75ad42179aee 100644 --- a/arch/arm/boot/dts/am3517-evm-ui.dtsi +++ b/arch/arm/boot/dts/am3517-evm-ui.dtsi @@ -70,61 +70,61 @@ compatible = "gpio-keys-polled"; poll-interval = <100>; - record { + key-record { label = "Record"; /* linux,code = <BTN_0>; */ gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>; }; - play { + key-play { label = "Play"; linux,code = <KEY_PLAY>; gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>; }; - Stop { + key-stop { label = "Stop"; linux,code = <KEY_STOP>; gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>; }; - fwd { + key-fwd { label = "FWD"; linux,code = <KEY_FASTFORWARD>; gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>; }; - rwd { + key-rwd { label = "RWD"; linux,code = <KEY_REWIND>; gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>; }; - shift { + key-shift { label = "Shift"; linux,code = <KEY_LEFTSHIFT>; gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>; }; - Mode { + key-mode { label = "Mode"; linux,code = <BTN_MODE>; gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>; }; - Menu { + key-menu { label = "Menu"; linux,code = <KEY_MENU>; gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>; }; - Up { + key-up { label = "Up"; linux,code = <KEY_UP>; gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>; }; - Down { + key-down { label = "Down"; linux,code = <KEY_DOWN>; gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>; @@ -137,14 +137,14 @@ tlv320aic23_1: codec@1a { compatible = "ti,tlv320aic23"; reg = <0x1a>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; tlv320aic23_2: codec@1b { compatible = "ti,tlv320aic23"; reg = <0x1b>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; }; @@ -154,7 +154,7 @@ tlv320aic23_3: codec@1a { compatible = "ti,tlv320aic23"; reg = <0x1a>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index 0d2fac98ce7d..35b653014f2b 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -37,55 +37,55 @@ compatible = "gpio-keys-polled"; poll-interval = <100>; - user_pb { + button-user { label = "User Push Button"; linux,code = <BTN_0>; gpios = <&tca6416 5 GPIO_ACTIVE_LOW>; }; - user_sw_1 { + switch-1 { label = "User Switch 1"; linux,code = <BTN_1>; gpios = <&tca6416 8 GPIO_ACTIVE_LOW>; }; - user_sw_2 { + switch-2 { label = "User Switch 2"; linux,code = <BTN_2>; gpios = <&tca6416 9 GPIO_ACTIVE_LOW>; }; - user_sw_3 { + switch-3 { label = "User Switch 3"; linux,code = <BTN_3>; gpios = <&tca6416 10 GPIO_ACTIVE_LOW>; }; - user_sw_4 { + switch-4 { label = "User Switch 4"; linux,code = <BTN_4>; gpios = <&tca6416 11 GPIO_ACTIVE_LOW>; }; - user_sw_5 { + switch-5 { label = "User Switch 5"; linux,code = <BTN_5>; gpios = <&tca6416 12 GPIO_ACTIVE_LOW>; }; - user_sw_6 { + switch-6 { label = "User Switch 6"; linux,code = <BTN_6>; gpios = <&tca6416 13 GPIO_ACTIVE_LOW>; }; - user_sw_7 { + switch-7 { label = "User Switch 7"; linux,code = <BTN_7>; gpios = <&tca6416 14 GPIO_ACTIVE_LOW>; }; - user_sw_8 { + switch-8 { label = "User Switch 8"; linux,code = <BTN_8>; gpios = <&tca6416 15 GPIO_ACTIVE_LOW>; @@ -161,6 +161,8 @@ /* HS USB Host PHY on PORT 1 */ hsusb1_phy: hsusb1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_rst_pins>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ #phy-cells = <0>; @@ -168,7 +170,9 @@ }; &davinci_emac { - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; + status = "okay"; }; &davinci_mdio { @@ -193,6 +197,8 @@ }; &i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; clock-frequency = <400000>; /* User DIP swithes [1:8] / User LEDS [1:2] */ tca6416: gpio@21 { @@ -205,6 +211,8 @@ }; &i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; clock-frequency = <400000>; }; @@ -223,6 +231,8 @@ }; &usbhshost { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_pins>; port1-mode = "ehci-phy"; }; @@ -231,8 +241,35 @@ }; &omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_rst_pins>; + + ethernet_pins: pinmux_ethernet_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */ + OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */ + OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd0 */ + OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd1 */ + OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_crs_dv */ + OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_rxer */ + OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd0 */ + OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd1 */ + OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN |MUX_MODE0) /* rmii_txen */ + OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; leds_pins: pinmux_leds_pins { pinctrl-single,pins = < @@ -300,8 +337,6 @@ }; &omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_pins>; hsusb1_pins: pinmux_hsusb1_pins { pinctrl-single,pins = < diff --git a/arch/arm/boot/dts/am3517-som.dtsi b/arch/arm/boot/dts/am3517-som.dtsi index 8b669e2eafec..f7b680f6c48a 100644 --- a/arch/arm/boot/dts/am3517-som.dtsi +++ b/arch/arm/boot/dts/am3517-som.dtsi @@ -69,6 +69,8 @@ }; &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; s35390a: s35390a@30 { @@ -179,6 +181,13 @@ &omap3_pmx_core { + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */ diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index de33c4f89f33..cb316135bc7c 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for am3517 SoC * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "omap3.dtsi" diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi index 220d0a52797e..0ee7afaa0e8e 100644 --- a/arch/arm/boot/dts/am35xx-clocks.dtsi +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -62,12 +62,27 @@ }; }; &cm_clocks { - ipss_ick: ipss_ick@a10 { - #clock-cells = <0>; - compatible = "ti,am35xx-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + ipss_ick: clock-ipss-ick { + #clock-cells = <0>; + compatible = "ti,am35xx-interface-clock"; + clock-output-names = "ipss_ick"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + uart4_ick_am35xx: clock-uart4-ick-am35xx { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart4_ick_am35xx"; + clocks = <&core_l4_ick>; + ti,bit-shift = <23>; + }; }; rmii_ck: rmii_ck { @@ -82,20 +97,19 @@ clock-frequency = <27000000>; }; - uart4_ick_am35xx: uart4_ick_am35xx@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; - uart4_fck_am35xx: uart4_fck_am35xx@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; + uart4_fck_am35xx: clock-uart4-fck-am35xx { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart4_fck_am35xx"; + clocks = <&core_48m_fck>; + ti,bit-shift = <23>; + }; }; }; diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts index 9423e9feaa10..d039af879367 100644 --- a/arch/arm/boot/dts/am3874-iceboard.dts +++ b/arch/arm/boot/dts/am3874-iceboard.dts @@ -213,7 +213,7 @@ u48: pca9575@22 { compatible = "nxp,pca9575"; - reg=<0x22>; + reg = <0x22>; gpio-controller; #gpio-cells = <2>; @@ -232,7 +232,7 @@ u59: pca9575@23 { compatible = "nxp,pca9575"; - reg=<0x23>; + reg = <0x23>; gpio-controller; #gpio-cells = <2>; gpio-line-names = @@ -434,7 +434,7 @@ }; &mcspi1 { - s25fl256@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 61a1d88f9df6..8613355bbd5e 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for AM4372 SoC * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h> diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index 3e3354780db8..0861e868b75a 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -302,7 +302,7 @@ &edma 17 0>; dma-names = "tx0", "rx0"; - flash: w25q64cvzpig@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 4416ddb559e4..46d5361fe876 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -1127,6 +1127,11 @@ cpu0-supply = <&dcdc2>; }; +&wkup_m3_ipc { + ti,set-io-isolation; + firmware-name = "am43x-evm-scale-data.bin"; +}; + &pruss1_mdio { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 53f64e3ce735..123a95f87554 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -98,14 +98,12 @@ vin-supply = <&v1_5dreg>; }; - gpio_keys: gpio_keys { + gpio_keys: gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pins_default>; - #address-cells = <1>; - #size-cells = <0>; - switch0 { + switch-0 { label = "power-button"; linux,code = <KEY_POWER>; gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; @@ -437,7 +435,7 @@ pinctrl-1 = <&qspi_pins_sleep>; spi-max-frequency = <48000000>; - m25p80@0 { + flash@0 { compatible = "mx66l51235l"; spi-max-frequency = <48000000>; reg = <0>; diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index 8f2268c02778..415210b034ef 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -2407,7 +2407,7 @@ adc { #io-channel-cells = <1>; - compatible ="ti,am4372-adc"; + compatible = "ti,am4372-adc"; }; }; }; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 20a34d2d85df..036f3831dc26 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -746,7 +746,7 @@ pinctrl-0 = <&qspi_pins>; spi-max-frequency = <48000000>; - m25p80@0 { + flash@0 { compatible = "mx66l51235l"; spi-max-frequency = <48000000>; reg = <0>; @@ -893,6 +893,10 @@ }; }; +&wkup_m3_ipc { + firmware-name = "am43x-evm-scale-data.bin"; +}; + &pruss1_mdio { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 2f4d2e4e9b3e..27f4ce855549 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -11,7 +11,7 @@ #include <dt-bindings/pinctrl/am43xx.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pwm/pwm.h> -#include <dt-bindings/sound/tlv320aic31xx-micbias.h> +#include <dt-bindings/sound/tlv320aic31xx.h> / { model = "TI AM43x EPOS EVM"; @@ -902,7 +902,7 @@ pinctrl-1 = <&qspi1_pins_sleep>; spi-max-frequency = <48000000>; - m25p80@0 { + flash@0 { compatible = "mx66l51235l"; spi-max-frequency = <48000000>; reg = <0>; @@ -1019,6 +1019,10 @@ cpu0-supply = <&dcdc2>; }; +&wkup_m3_ipc { + firmware-name = "am43x-evm-scale-data.bin"; +}; + &pruss1_mdio { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 66e892fa3398..9a5437b3d6a8 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -5,217 +5,246 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &scm_clocks { - sys_clkin_ck: sys_clkin_ck@40 { + sys_clkin_ck: clock-sys-clkin-31@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin_ck"; clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; ti,bit-shift = <31>; reg = <0x0040>; }; - crystal_freq_sel_ck: crystal_freq_sel_ck@40 { + crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "crystal_freq_sel_ck"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <29>; reg = <0x0040>; }; - sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { + sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sysboot_freq_sel_ck"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <22>; reg = <0x0040>; }; - adc_tsc_fck: adc_tsc_fck { + adc_tsc_fck: clock-adc-tsc-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "adc_tsc_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dcan0_fck: dcan0_fck { + dcan0_fck: clock-dcan0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dcan0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dcan1_fck: dcan1_fck { + dcan1_fck: clock-dcan1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dcan1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - mcasp0_fck: mcasp0_fck { + mcasp0_fck: clock-mcasp0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mcasp0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - mcasp1_fck: mcasp1_fck { + mcasp1_fck: clock-mcasp1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mcasp1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - smartreflex0_fck: smartreflex0_fck { + smartreflex0_fck: clock-smartreflex0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - smartreflex1_fck: smartreflex1_fck { + smartreflex1_fck: clock-smartreflex1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "smartreflex1_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - sha0_fck: sha0_fck { + sha0_fck: clock-sha0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sha0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - aes0_fck: aes0_fck { + aes0_fck: clock-aes0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "aes0_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - rng_fck: rng_fck { + rng_fck: clock-rng-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "rng_fck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk@664 { + ehrpwm0_tbclk: clock-ehrpwm0-tbclk-0@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <0>; reg = <0x0664>; }; - ehrpwm1_tbclk: ehrpwm1_tbclk@664 { + ehrpwm1_tbclk: clock-ehrpwm1-tbclk-1@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <1>; reg = <0x0664>; }; - ehrpwm2_tbclk: ehrpwm2_tbclk@664 { + ehrpwm2_tbclk: clock-ehrpwm2-tbclk-2@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <2>; reg = <0x0664>; }; - ehrpwm3_tbclk: ehrpwm3_tbclk@664 { + ehrpwm3_tbclk: clock-ehrpwm3-tbclk-4@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm3_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <4>; reg = <0x0664>; }; - ehrpwm4_tbclk: ehrpwm4_tbclk@664 { + ehrpwm4_tbclk: clock-ehrpwm4-tbclk-5@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm4_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <5>; reg = <0x0664>; }; - ehrpwm5_tbclk: ehrpwm5_tbclk@664 { + ehrpwm5_tbclk: clock-ehrpwm5-tbclk-6@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm5_tbclk"; clocks = <&l4ls_gclk>; ti,bit-shift = <6>; reg = <0x0664>; }; }; &prcm_clocks { - clk_32768_ck: clk_32768_ck { + clk_32768_ck: clock-clk-32768 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_32768_ck"; clock-frequency = <32768>; }; - clk_rc32k_ck: clk_rc32k_ck { + clk_rc32k_ck: clock-clk-rc32k { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_rc32k_ck"; clock-frequency = <32768>; }; - virt_19200000_ck: virt_19200000_ck { + virt_19200000_ck: clock-virt-19200000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; - virt_24000000_ck: virt_24000000_ck { + virt_24000000_ck: clock-virt-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_24000000_ck"; clock-frequency = <24000000>; }; - virt_25000000_ck: virt_25000000_ck { + virt_25000000_ck: clock-virt-25000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_25000000_ck"; clock-frequency = <25000000>; }; - virt_26000000_ck: virt_26000000_ck { + virt_26000000_ck: clock-virt-26000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; - tclkin_ck: tclkin_ck { + tclkin_ck: clock-tclkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "tclkin_ck"; clock-frequency = <26000000>; }; - dpll_core_ck: dpll_core_ck@2d20 { + dpll_core_ck: clock@2d20 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; }; - dpll_core_x2_ck: dpll_core_x2_ck { + dpll_core_x2_ck: clock-dpll-core-x2 { #clock-cells = <0>; compatible = "ti,am3-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; - dpll_core_m4_ck: dpll_core_m4_ck@2d38 { + dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m4_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -224,9 +253,10 @@ ti,invert-autoidle-bit; }; - dpll_core_m5_ck: dpll_core_m5_ck@2d3c { + dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m5_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -235,9 +265,10 @@ ti,invert-autoidle-bit; }; - dpll_core_m6_ck: dpll_core_m6_ck@2d40 { + dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m6_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -246,16 +277,18 @@ ti,invert-autoidle-bit; }; - dpll_mpu_ck: dpll_mpu_ck@2d60 { + dpll_mpu_ck: clock@2d60 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { + dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -264,24 +297,27 @@ ti,invert-autoidle-bit; }; - mpu_periphclk: mpu_periphclk { + mpu_periphclk: clock-mpu-periphclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_periphclk"; clocks = <&dpll_mpu_m2_ck>; clock-mult = <1>; clock-div = <2>; }; - dpll_ddr_ck: dpll_ddr_ck@2da0 { + dpll_ddr_ck: clock@2da0 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_ddr_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { + dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m2_ck"; clocks = <&dpll_ddr_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -290,16 +326,18 @@ ti,invert-autoidle-bit; }; - dpll_disp_ck: dpll_disp_ck@2e20 { + dpll_disp_ck: clock@2e20 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_disp_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; }; - dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { + dpll_disp_m2_ck: clock-dpll-disp-m2-8@2e30 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_disp_m2_ck"; clocks = <&dpll_disp_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -309,16 +347,18 @@ ti,set-rate-parent; }; - dpll_per_ck: dpll_per_ck@2de0 { + dpll_per_ck: clock@2de0 { #clock-cells = <0>; compatible = "ti,am3-dpll-j-type-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; }; - dpll_per_m2_ck: dpll_per_m2_ck@2df0 { + dpll_per_m2_ck: clock-dpll-per-m2-8@2df0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -327,119 +367,135 @@ ti,invert-autoidle-bit; }; - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { + dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { + dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_per_m2_div4_ck"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - clk_24mhz: clk_24mhz { + clk_24mhz: clock-clk-24mhz { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "clk_24mhz"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <8>; }; - clkdiv32k_ck: clkdiv32k_ck { + clkdiv32k_ck: clock-clkdiv32k { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "clkdiv32k_ck"; clocks = <&clk_24mhz>; clock-mult = <1>; clock-div = <732>; }; - clkdiv32k_ick: clkdiv32k_ick@2a38 { + clkdiv32k_ick: clock-clkdiv32k-ick-8@2a38 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "clkdiv32k_ick"; clocks = <&clkdiv32k_ck>; ti,bit-shift = <8>; reg = <0x2a38>; }; - sysclk_div: sysclk_div { + sysclk_div: clock-sysclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sysclk_div"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - pruss_ocp_gclk: pruss_ocp_gclk@4248 { + pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "pruss_ocp_gclk"; clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; reg = <0x4248>; }; - clk_32k_tpm_ck: clk_32k_tpm_ck { + clk_32k_tpm_ck: clock-clk-32k-tpm { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_32k_tpm_ck"; clock-frequency = <32768>; }; - timer1_fck: timer1_fck@4200 { + timer1_fck: clock-timer1-fck@4200 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer1_fck"; clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4200>; }; - timer2_fck: timer2_fck@4204 { + timer2_fck: clock-timer2-fck@4204 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer2_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4204>; }; - timer3_fck: timer3_fck@4208 { + timer3_fck: clock-timer3-fck@4208 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer3_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4208>; }; - timer4_fck: timer4_fck@420c { + timer4_fck: clock-timer4-fck@420c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer4_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x420c>; }; - timer5_fck: timer5_fck@4210 { + timer5_fck: clock-timer5-fck@4210 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer5_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4210>; }; - timer6_fck: timer6_fck@4214 { + timer6_fck: clock-timer6-fck@4214 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer6_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4214>; }; - timer7_fck: timer7_fck@4218 { + timer7_fck: clock-timer7-fck@4218 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer7_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4218>; }; - wdt1_fck: wdt1_fck@422c { + wdt1_fck: clock-wdt1-fck@422c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "wdt1_fck"; clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; reg = <0x422c>; }; @@ -451,125 +507,141 @@ reg = <0x424c>; }; - l3_gclk: l3_gclk { + l3_gclk: clock-l3-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { + dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_core_m4_div2_ck"; clocks = <&sysclk_div>; clock-mult = <1>; clock-div = <2>; }; - l4hs_gclk: l4hs_gclk { + l4hs_gclk: clock-l4hs-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4hs_gclk"; clocks = <&dpll_core_m4_ck>; clock-mult = <1>; clock-div = <1>; }; - l3s_gclk: l3s_gclk { + l3s_gclk: clock-l3s-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3s_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - l4ls_gclk: l4ls_gclk { + l4ls_gclk: clock-l4ls-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4ls_gclk"; clocks = <&dpll_core_m4_div2_ck>; clock-mult = <1>; clock-div = <1>; }; - cpsw_125mhz_gclk: cpsw_125mhz_gclk { + cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_125mhz_gclk"; clocks = <&dpll_core_m5_ck>; clock-mult = <1>; clock-div = <2>; }; - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 { + cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@4238 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "cpsw_cpts_rft_clk"; clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; reg = <0x4238>; }; - dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 { + dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_clksel_mac_clk"; clocks = <&dpll_core_m5_ck>; reg = <0x4234>; ti,bit-shift = <2>; ti,dividers = <2>, <5>; }; - clk_32k_mosc_ck: clk_32k_mosc_ck { + clk_32k_mosc_ck: clock-clk-32k-mosc { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "clk_32k_mosc_ck"; clock-frequency = <32768>; }; - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 { + gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@4240 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpio0_dbclk_mux_ck"; clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; reg = <0x4240>; }; - mmc_clk: mmc_clk { + mmc_clk: clock-mmc { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mmc_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <2>; }; - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c { + gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gfx_fclk_clksel_ck"; clocks = <&sysclk_div>, <&dpll_per_m2_ck>; ti,bit-shift = <1>; reg = <0x423c>; }; - gfx_fck_div_ck: gfx_fck_div_ck@423c { + gfx_fck_div_ck: clock-gfx-fck-div@423c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "gfx_fck_div_ck"; clocks = <&gfx_fclk_clksel_ck>; reg = <0x423c>; ti,max-div = <2>; }; - disp_clk: disp_clk@4244 { + disp_clk: clock-disp@4244 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "disp_clk"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; reg = <0x4244>; ti,set-rate-parent; }; - dpll_extdev_ck: dpll_extdev_ck@2e60 { + dpll_extdev_ck: clock@2e60 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; + clock-output-names = "dpll_extdev_ck"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; }; - dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { + dpll_extdev_m2_ck: clock-dpll-extdev-m2-8@2e70 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_extdev_m2_ck"; clocks = <&dpll_extdev_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -578,66 +650,75 @@ ti,invert-autoidle-bit; }; - mux_synctimer32k_ck: mux_synctimer32k_ck@4230 { + mux_synctimer32k_ck: clock-mux-synctimer32k@4230 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "mux_synctimer32k_ck"; clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; reg = <0x4230>; }; - timer8_fck: timer8_fck@421c { + timer8_fck: clock-timer8-fck@421c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer8_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x421c>; }; - timer9_fck: timer9_fck@4220 { + timer9_fck: clock-timer9-fck@4220 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer9_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4220>; }; - timer10_fck: timer10_fck@4224 { + timer10_fck: clock-timer10-fck@4224 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer10_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4224>; }; - timer11_fck: timer11_fck@4228 { + timer11_fck: clock-timer11-fck@4228 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "timer11_fck"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4228>; }; - cpsw_50m_clkdiv: cpsw_50m_clkdiv { + cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_50m_clkdiv"; clocks = <&dpll_core_m5_ck>; clock-mult = <1>; clock-div = <1>; }; - cpsw_5m_clkdiv: cpsw_5m_clkdiv { + cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "cpsw_5m_clkdiv"; clocks = <&cpsw_50m_clkdiv>; clock-mult = <1>; clock-div = <10>; }; - dpll_ddr_x2_ck: dpll_ddr_x2_ck { + dpll_ddr_x2_ck: clock-dpll-ddr-x2 { #clock-cells = <0>; compatible = "ti,am3-dpll-x2-clock"; + clock-output-names = "dpll_ddr_x2_ck"; clocks = <&dpll_ddr_ck>; }; - dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 { + dpll_ddr_m4_ck: clock-dpll-ddr-m4-8@2db8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m4_ck"; clocks = <&dpll_ddr_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -646,9 +727,10 @@ ti,invert-autoidle-bit; }; - dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 { + dpll_per_clkdcoldo: clock-dpll-per-clkdcoldo-8@2e14 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; + clock-output-names = "dpll_per_clkdcoldo"; clocks = <&dpll_per_ck>; ti,clock-mult = <1>; ti,clock-div = <1>; @@ -657,91 +739,102 @@ ti,invert-autoidle-bit; }; - dll_aging_clk_div: dll_aging_clk_div@4250 { + dll_aging_clk_div: clock-dll-aging-clk-div@4250 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dll_aging_clk_div"; clocks = <&sys_clkin_ck>; reg = <0x4250>; ti,dividers = <8>, <16>, <32>; }; - div_core_25m_ck: div_core_25m_ck { + div_core_25m_ck: clock-div-core-25m { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "div_core_25m_ck"; clocks = <&sysclk_div>; clock-mult = <1>; clock-div = <8>; }; - func_12m_clk: func_12m_clk { + func_12m_clk: clock-func-12m { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <16>; }; - vtp_clk_div: vtp_clk_div { + vtp_clk_div: clock-vtp-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "vtp_clk_div"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <2>; }; - usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 { + usbphy_32khz_clkmux: clock-usbphy-32khz-clkmux@4260 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "usbphy_32khz_clkmux"; clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4260>; }; - usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 { + usb_phy0_always_on_clk32k: clock-usb-phy0-always-on-clk32k-8@2a40 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy0_always_on_clk32k"; clocks = <&usbphy_32khz_clkmux>; ti,bit-shift = <8>; reg = <0x2a40>; }; - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 { + usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@2a48 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy1_always_on_clk32k"; clocks = <&usbphy_32khz_clkmux>; ti,bit-shift = <8>; reg = <0x2a48>; }; - clkout1_osc_div_ck: clkout1-osc-div-ck { + clkout1_osc_div_ck: clock-clkout1-osc-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "clkout1_osc_div_ck"; clocks = <&sys_clkin_ck>; ti,bit-shift = <20>; ti,max-div = <4>; reg = <0x4100>; }; - clkout1_src2_mux_ck: clkout1-src2-mux-ck { + clkout1_src2_mux_ck: clock-clkout1-src2-mux-ck { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkout1_src2_mux_ck"; clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, <&dpll_mpu_m2_ck>; reg = <0x4100>; }; - clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck { + clkout1_src2_pre_div_ck: clock-clkout1-src2-pre-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "clkout1_src2_pre_div_ck"; clocks = <&clkout1_src2_mux_ck>; ti,bit-shift = <4>; ti,max-div = <8>; reg = <0x4100>; }; - clkout1_src2_post_div_ck: clkout1-src2-post-div-ck { + clkout1_src2_post_div_ck: clock-clkout1-src2-post-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "clkout1_src2_post_div_ck"; clocks = <&clkout1_src2_pre_div_ck>; ti,bit-shift = <8>; ti,max-div = <32>; @@ -749,18 +842,20 @@ reg = <0x4100>; }; - clkout1_mux_ck: clkout1-mux-ck { + clkout1_mux_ck: clock-clkout1-mux-ck { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkout1_mux_ck"; clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; ti,bit-shift = <16>; reg = <0x4100>; }; - clkout1_ck: clkout1-ck { + clkout1_ck: clock-clkout1-ck { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "clkout1_ck"; clocks = <&clkout1_mux_ck>; ti,bit-shift = <23>; reg = <0x4100>; @@ -768,120 +863,138 @@ }; &prcm { - wkup_cm: wkup-cm@2800 { + wkup_cm: clock@2800 { compatible = "ti,omap4-cm"; + clock-output-names = "wkup_cm"; reg = <0x2800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2800 0x400>; - l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 { + l3s_tsc_clkctrl: clock@120 { compatible = "ti,clkctrl"; + clock-output-names = "l3s_tsc_clkctrl"; reg = <0x120 0x4>; #clock-cells = <2>; }; - l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 { + l4_wkup_aon_clkctrl: clock@228 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_aon_clkctrl"; reg = <0x228 0xc>; #clock-cells = <2>; }; - l4_wkup_clkctrl: l4-wkup-clkctrl@220 { + l4_wkup_clkctrl: clock@220 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_clkctrl"; reg = <0x220 0x4>, <0x328 0x44>; #clock-cells = <2>; }; }; - mpu_cm: mpu-cm@8300 { + mpu_cm: clock@8300 { compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; reg = <0x8300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8300 0x100>; - mpu_clkctrl: mpu-clkctrl@20 { + mpu_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - gfx_l3_cm: gfx-l3-cm@8400 { + gfx_l3_cm: clock@8400 { compatible = "ti,omap4-cm"; + clock-output-names = "gfx_l3_cm"; reg = <0x8400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8400 0x100>; - gfx_l3_clkctrl: gfx-l3-clkctrl@20 { + gfx_l3_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "gfx_l3_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - l4_rtc_cm: l4-rtc-cm@8500 { + l4_rtc_cm: clock@8500 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_rtc_cm"; reg = <0x8500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8500 0x100>; - l4_rtc_clkctrl: l4-rtc-clkctrl@20 { + l4_rtc_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_rtc_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - per_cm: per-cm@8800 { + per_cm: clock@8800 { compatible = "ti,omap4-cm"; + clock-output-names = "per_cm"; reg = <0x8800 0xc00>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8800 0xc00>; - l3_clkctrl: l3-clkctrl@20 { + l3_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_clkctrl"; reg = <0x20 0x3c>, <0x78 0x2c>; #clock-cells = <2>; }; - l3s_clkctrl: l3s-clkctrl@68 { + l3s_clkctrl: clock@68 { compatible = "ti,clkctrl"; + clock-output-names = "l3s_clkctrl"; reg = <0x68 0xc>, <0x220 0x4c>; #clock-cells = <2>; }; - pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 { + pruss_ocp_clkctrl: clock@320 { compatible = "ti,clkctrl"; + clock-output-names = "pruss_ocp_clkctrl"; reg = <0x320 0x4>; #clock-cells = <2>; }; - l4ls_clkctrl: l4ls-clkctrl@420 { + l4ls_clkctrl: clock@420 { compatible = "ti,clkctrl"; + clock-output-names = "l4ls_clkctrl"; reg = <0x420 0x1a4>; #clock-cells = <2>; }; - emif_clkctrl: emif-clkctrl@720 { + emif_clkctrl: clock@720 { compatible = "ti,clkctrl"; + clock-output-names = "emif_clkctrl"; reg = <0x720 0x4>; #clock-cells = <2>; }; - dss_clkctrl: dss-clkctrl@a20 { + dss_clkctrl: clock@a20 { compatible = "ti,clkctrl"; + clock-output-names = "dss_clkctrl"; reg = <0xa20 0x4>; #clock-cells = <2>; }; - cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 { + cpsw_125mhz_clkctrl: clock@b20 { compatible = "ti,clkctrl"; + clock-output-names = "cpsw_125mhz_clkctrl"; reg = <0xb20 0x4>; #clock-cells = <2>; }; diff --git a/arch/arm/boot/dts/am5748.dtsi b/arch/arm/boot/dts/am5748.dtsi index c260aa1a85bd..a1f029e9d1f3 100644 --- a/arch/arm/boot/dts/am5748.dtsi +++ b/arch/arm/boot/dts/am5748.dtsi @@ -25,6 +25,10 @@ status = "disabled"; }; +&usb4_tm { + status = "disabled"; +}; + &atl_tm { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts index 6dff3660bf09..47b9174d2353 100644 --- a/arch/arm/boot/dts/am574x-idk.dts +++ b/arch/arm/boot/dts/am574x-idk.dts @@ -18,7 +18,7 @@ &qspi { spi-max-frequency = <96000000>; - m25p80@0 { + flash@0 { spi-max-frequency = <96000000>; }; }; diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 2e94f32d9dfc..2fc9a5d5e0c0 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -491,7 +491,7 @@ spi-max-frequency = <48000000>; - spi_flash: spi_flash@0 { + spi_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spansion,m25p80", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index 9fcb8944aa3e..c06eda817242 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -526,7 +526,7 @@ status = "okay"; spi-max-frequency = <76800000>; - m25p80@0 { + flash@0 { compatible = "s25fl256s1", "jedec,spi-nor"; spi-max-frequency = <76800000>; reg = <0>; diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 7da718abbd85..29936bfbeeb7 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -168,26 +168,24 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - keyswitch_in { + key-switch-in { label = "keyswitch_in"; gpios = <&pioB 1 GPIO_ACTIVE_HIGH>; linux,code = <28>; wakeup-source; }; - error_in { + key-error-in { label = "error_in"; gpios = <&pioB 2 GPIO_ACTIVE_HIGH>; linux,code = <29>; wakeup-source; }; - btn { + key-s { label = "btn"; gpios = <&pioC 23 GPIO_ACTIVE_HIGH>; linux,code = <31>; diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi index 2dfb32bf9d48..fbb2258b451f 100644 --- a/arch/arm/boot/dts/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm-realview-eb.dtsi @@ -399,7 +399,7 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x1000d000 0x1000>; clocks = <&sspclk>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; }; wdog: watchdog@10010000 { diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts index 06b8723b09eb..efed325af88d 100644 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -410,7 +410,7 @@ interrupt-parent = <&intc_dc1176>; interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&sspclk>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; }; pb1176_serial0: serial@1010c000 { diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 295aef448123..89103d54ecc1 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -555,7 +555,7 @@ interrupt-parent = <&intc_pb11mp>; interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&sspclk>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; }; watchdog@1000f000 { diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi index 6f61f968d689..ec1507c5147c 100644 --- a/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi @@ -390,7 +390,7 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x1000d000 0x1000>; clocks = <&sspclk>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; }; wdog0: watchdog@1000f000 { diff --git a/arch/arm/boot/dts/armada-370-c200-v2.dts b/arch/arm/boot/dts/armada-370-c200-v2.dts new file mode 100644 index 000000000000..84d40e1d70ef --- /dev/null +++ b/arch/arm/boot/dts/armada-370-c200-v2.dts @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device Tree file for Ctera C200-V2 + * + * Copyright (C) 2022 Pawel Dembicki <paweldembicki@gmail.com> + */ + +/dts-v1/; + +#include "armada-370.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Ctera C200 V2"; + compatible = "ctera,c200-v2", "marvell,armada370", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1024 MB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 + MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 + MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; + }; + + thermal-zones { + ethphy-thermal { + polling-delay = <20000>; + polling-delay-passive = <2000>; + + thermal-sensors = <ðphy0>; + + trips { + ethphy_alert1: trip1 { + temperature = <65000>; + hysteresis = <4000>; + type = "passive"; + }; + + ethphy_crit: trip2 { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + beeper { + compatible = "pwm-beeper"; + pinctrl-0 = <&pmx_beeper>; + pinctrl-names = "default"; + pwms = <&gpio1 31 4000>; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_poweroff>; + pinctrl-names = "default"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + + button-power { + label = "Power Button"; + linux,code = <KEY_POWER>; + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + + button-reset { + label = "Reset Button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + }; + + button-usb1 { + label = "USB1 Button"; + linux,code = <BTN_0>; + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + }; + + button-usb2 { + label = "USB2 Button"; + linux,code = <BTN_1>; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds1 &pmx_leds2>; + pinctrl-names = "default"; + + led-0 { + function = LED_FUNCTION_USB; + function-enumerator = <2>; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + + led-1 { + function = LED_FUNCTION_USB; + function-enumerator = <2>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + + led-2 { + function = LED_FUNCTION_USB; + function-enumerator = <1>; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + led-3 { + function = LED_FUNCTION_USB; + function-enumerator = <1>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + }; + + led-4 { + function = LED_FUNCTION_DISK; + function-enumerator = <2>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + led-5 { + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + }; + + led-6 { + function = LED_FUNCTION_DISK; + function-enumerator = <2>; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + }; + + led-7 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + }; + + led-8 { + function = LED_FUNCTION_DISK_ERR; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + }; + + led-9 { + function = LED_FUNCTION_DISK_ERR; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + }; + + led-10 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + }; + + led-11 { + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + + led-12 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&coherencyfab { + broken-idle; +}; + +ð1 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-handle = <ðphy0>; + phy-connection-type = "rgmii-id"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + hwmon@2a { + compatible = "nuvoton,nct7802"; + reg = <0x2a>; + }; + + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + #thermal-sensor-cells = <0>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x200000>; + read-only; + }; + + partition@200000 { + label = "certificate"; + reg = <0x0200000 0x100000>; + read-only; + }; + + partition@300000 { + label = "preset_cfg"; + reg = <0x0300000 0x100000>; + read-only; + }; + + partition@400000 { + label = "dev_params"; + reg = <0x0400000 0x100000>; + read-only; + }; + partition@500000 { + label = "active_bank"; + reg = <0x0500000 0x0100000>; + }; + + partition@600000 { + label = "magic"; + reg = <0x0600000 0x0100000>; + read-only; + }; + + partition@700000 { + label = "bank1"; + reg = <0x0700000 0x2800000>; + }; + + partition@2f00000 { + label = "bank2"; + reg = <0x2f00000 0x2800000>; + }; + + /* 0x5700000-0x5a00000 undefined in vendor firmware */ + + partition@5a00000 { + label = "reserved"; + reg = <0x5a00000 0x2000000>; + }; + + partition@7a00000 { + label = "rootfs"; + reg = <0x7a00000 0x8600000>; + }; + }; + }; +}; + +&pciec { + status = "okay"; + + pcie@1,0 { /* Renesas uPD720202 USB 3.0 controller */ + pinctrl-0 = <&pmx_pcie>; + pinctrl-names = "default"; + status = "okay"; + reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + pmx_poweroff: pmx-poweroff { + marvell,pins = "mpp7"; + marvell,function = "gpo"; + }; + + pmx_power_cpu: pmx-power-cpu { + marvell,pins = "mpp4"; + marvell,function = "vdd"; + }; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp6", "mpp10", "mpp14", "mpp32"; + marvell,function = "gpio"; + }; + + pmx_leds1: pmx-leds1 { + marvell,pins = "mpp47"; + marvell,function = "gpo"; + }; + + pmx_leds2: pmx-leds2 { + marvell,pins = "mpp12", "mpp13", "mpp15", "mpp16", "mpp50", "mpp51", + "mpp52", "mpp53", "mpp55", "mpp56", "mpp57", "mpp58"; + marvell,function = "gpio"; + }; + + pmx_pcie: pmx-pcie { + marvell,pins = "mpp59"; + marvell,function = "gpio"; + }; + + pmx_beeper: pmx-beeper { + marvell,pins = "mpp63"; + marvell,function = "gpio"; + }; +}; + +&pmsu { + pinctrl-0 = <&pmx_power_cpu>; + pinctrl-names = "default"; +}; + +&rtc { + status = "disabled"; +}; + +&sata { + nr-ports = <2>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + hdd0_temp: sata-port@0 { + reg = <0>; + #thermal-sensor-cells = <0>; + }; + + hdd1_temp: sata-port@1 { + reg = <1>; + #thermal-sensor-cells = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 77261a2fb949..a7dc4c04d10b 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -203,7 +203,7 @@ pinctrl-names = "default"; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "mx25l25635e", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index c910d157a686..6ba7699b69ed 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -84,8 +84,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; button { label = "Software Button"; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi index b52634ecf1d9..866b8630d407 100644 --- a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi +++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi @@ -108,22 +108,20 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - power { + button-power { label = "Power button"; linux,code = <KEY_POWER>; gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - backup { + button-backup { label = "Backup button"; linux,code = <KEY_OPTION>; gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - reset { + button-reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi index a624b2371fb6..702a85af2078 100644 --- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi +++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi @@ -83,22 +83,20 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - power { + button-power { label = "Power button"; linux,code = <KEY_POWER>; gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; debounce-interval = <100>; }; - reset { + button-reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - button { + button-usb { label = "USB VBUS error"; linux,code = <KEY_UNKNOWN>; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; @@ -159,7 +157,7 @@ pinctrl-0 = <&spi0_pins2>; pinctrl-names = "default"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; /* MX25L8006E */ diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts index 64f2ce254fb6..e72b8ed4b997 100644 --- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts +++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts @@ -258,7 +258,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q064", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 46e6d3ed8f35..9dc928859ad3 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -60,16 +60,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie2: pcie@2,0 { @@ -78,16 +88,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 62>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 9>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts index 0e679465cbb5..4c4092790a20 100644 --- a/arch/arm/boot/dts/armada-375-db.dts +++ b/arch/arm/boot/dts/armada-375-db.dts @@ -64,7 +64,7 @@ status = "disabled"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 7f2f24a29e6c..929deaf312a5 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -568,16 +568,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie1: pcie@2,0 { @@ -586,16 +596,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; clocks = <&gateclk 6>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi index cff1269f3fbf..ce1dddb2269b 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi @@ -64,16 +64,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -83,16 +93,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -102,16 +122,26 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts index 0a961116a1f9..095df5567c93 100644 --- a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts +++ b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts @@ -24,7 +24,7 @@ pinctrl-0 = <&front_button_pins>; pinctrl-names = "default"; - factory_default { + key-factory-default { label = "Factory Default"; gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_RESTART>; @@ -242,7 +242,7 @@ pinctrl-names = "default"; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-385-atl-x530.dts b/arch/arm/boot/dts/armada-385-atl-x530.dts index ed3f41c7df71..241f5d7c80e9 100644 --- a/arch/arm/boot/dts/armada-385-atl-x530.dts +++ b/arch/arm/boot/dts/armada-385-atl-x530.dts @@ -168,7 +168,7 @@ pinctrl-0 = <&spi1_pins>; status = "okay"; - spi-flash@1 { + flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi index 624bbcae68c0..d1452a04e904 100644 --- a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi +++ b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi @@ -256,14 +256,14 @@ pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>; pinctrl-names = "default"; - button_0 { + button-0 { label = "Rear Button"; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; linux,can-disable; linux,code = <BTN_0>; }; - button_1 { + button-1 { label = "Front Button"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; linux,can-disable; @@ -365,7 +365,7 @@ pinctrl-names = "default"; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <0>; compatible = "w25q32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts b/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts index 7881df3b28a0..389d9c75d546 100644 --- a/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts +++ b/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts @@ -126,7 +126,7 @@ pinctrl-0 = <&spi1_pins>; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts index 0e4613bb56ee..332f8fce77dc 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -192,7 +192,7 @@ pinctrl-0 = <&spi1_pins>; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p128", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index fb9c8a0b241c..116aca5e688f 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -53,13 +53,13 @@ pinctrl-0 = <&gpio_keys_pins>; pinctrl-names = "default"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Factory Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/armada-385-synology-ds116.dts index d8769956cbfc..2622af73c9da 100644 --- a/arch/arm/boot/dts/armada-385-synology-ds116.dts +++ b/arch/arm/boot/dts/armada-385-synology-ds116.dts @@ -223,7 +223,7 @@ pinctrl-0 = <&spi0_pins>; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "macronix,mx25l6405d", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 5bd6a66d2c2b..72ac807cae25 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -71,16 +71,19 @@ pcie@1,0 { /* Port 0, Lane 0 */ status = "okay"; + slot-power-limit-milliwatt = <10000>; }; pcie@2,0 { /* Port 1, Lane 0 */ status = "okay"; + slot-power-limit-milliwatt = <10000>; }; pcie@3,0 { /* Port 2, Lane 0 */ status = "okay"; + slot-power-limit-milliwatt = <10000>; }; }; }; @@ -102,6 +105,33 @@ */ status = "disabled"; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&audio_controller 1>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&audio_controller { + /* Pin header U16, GPIO51 in SPDIFO mode */ + pinctrl-0 = <&spdif_pins>; + pinctrl-names = "default"; + spdif-mode; + status = "okay"; }; &bm { @@ -163,6 +193,7 @@ buffer-manager = <&bm>; bm,pool-long = <2>; bm,pool-short = <3>; + label = "wan"; }; &i2c0 { @@ -188,15 +219,13 @@ reg = <0x2b>; #address-cells = <1>; #size-cells = <0>; + status = "okay"; /* * LEDs are controlled by MCU (STM32F0) at * address 0x2b. * - * The driver does not support HW control mode - * for the LEDs yet. Disable the LEDs for now. - * - * Also LED functions are not stable yet: + * LED functions are not stable yet: * - there are 3 LEDs connected via MCU to PCIe * ports. One of these ports supports mSATA. * There is no mSATA nor PCIe function. @@ -207,7 +236,6 @@ * B. Again there is no such function defined. * For now we use LED_FUNCTION_INDICATOR */ - status = "disabled"; multi-led@0 { reg = <0x0>; @@ -345,7 +373,11 @@ #size-cells = <0>; reg = <5>; - /* ATSHA204A at address 0x64 */ + /* ATSHA204A-MAHDA-T crypto module */ + crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; }; i2c@6 { @@ -390,7 +422,8 @@ phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - marvell,reg-init = <3 18 0 0x4985>; + marvell,reg-init = <3 18 0 0x4985>, + <3 16 0xfff0 0x0001>; /* irq is connected to &pcawan pin 7 */ }; @@ -471,7 +504,7 @@ marvell,function = "spi0"; }; - spi0cs1_pins: spi0cs1-pins { + spi0cs2_pins: spi0cs2-pins { marvell,pins = "mpp26"; marvell,function = "spi0"; }; @@ -482,7 +515,7 @@ pinctrl-0 = <&spi0_pins &spi0cs0_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "spansion,s25fl164k", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -506,7 +539,7 @@ }; }; - /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ + /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ }; &uart0 { diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index f0022d10c715..83392b92dae2 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -69,16 +69,25 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; status = "disabled"; + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -88,16 +97,25 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -107,16 +125,25 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; status = "disabled"; + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* @@ -129,16 +156,25 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; clocks = <&gateclk 7>; status = "disabled"; + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/armada-388-clearfog-base.dts index 53b4bd35522a..f7daa3bc707e 100644 --- a/arch/arm/boot/dts/armada-388-clearfog-base.dts +++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts @@ -19,7 +19,7 @@ pinctrl-0 = <&rear_button_pins>; pinctrl-names = "default"; - button_0 { + button-0 { /* The rear SW3 button */ label = "Rear Button"; gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts index 4140a5303b48..95299167dcf5 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/armada-388-clearfog.dts @@ -35,7 +35,7 @@ pinctrl-0 = <&rear_button_pins>; pinctrl-names = "default"; - button_0 { + button-0 { /* The rear SW3 button */ label = "Rear Button"; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts index a2bec07bf4c5..2bcec5419b66 100644 --- a/arch/arm/boot/dts/armada-388-db.dts +++ b/arch/arm/boot/dts/armada-388-db.dts @@ -36,6 +36,11 @@ i2c@11000 { status = "okay"; clock-frequency = <100000>; + audio_codec: audio-codec@4a { + #sound-dai-cells = <0>; + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + }; }; i2c@11100 { @@ -99,6 +104,12 @@ no-1-8-v; }; + audio-controller@e8000 { + pinctrl-0 = <&i2s_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + usb3@f0000 { status = "okay"; }; @@ -128,12 +139,70 @@ }; }; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Armada 385 DB Audio"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Headphone", "Out Jack", + "Line", "In Jack"; + simple-audio-card,routing = + "Out Jack", "HPL", + "Out Jack", "HPR", + "AIN1L", "In Jack", + "AIN1R", "In Jack"; + status = "disabled"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 0>; + }; + + codec { + sound-dai = <&audio_codec>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 1>; + }; + + codec { + sound-dai = <&spdif_out>; + }; + }; + + simple-audio-card,dai-link@2 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 1>; + }; + + codec { + sound-dai = <&spdif_in>; + }; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; + + spdif_in: spdif-in { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dir"; + }; }; &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "w25q32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts index 9d873257ac45..e2ba50520b6b 100644 --- a/arch/arm/boot/dts/armada-388-gp.dts +++ b/arch/arm/boot/dts/armada-388-gp.dts @@ -395,7 +395,7 @@ pinctrl-0 = <&spi0_pins>; status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p128", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts index 328a4d6afd2c..c0efafd45b33 100644 --- a/arch/arm/boot/dts/armada-388-rd.dts +++ b/arch/arm/boot/dts/armada-388-rd.dts @@ -97,7 +97,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p128", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi index 363ac4238859..2c64bc6e5a17 100644 --- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi @@ -101,7 +101,7 @@ /* The microsom has an optional W25Q32 on board, connected to CS0 */ pinctrl-0 = <&spi1_pins>; - w25q32: spi-flash@0 { + w25q32: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "w25q32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index df3c8d1d8f64..446861b6b17b 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -289,6 +289,18 @@ marvell,pins = "mpp44"; marvell,function = "sata3"; }; + + i2s_pins: i2s-pins { + marvell,pins = "mpp48", "mpp49", + "mpp50", "mpp51", + "mpp52", "mpp53"; + marvell,function = "audio"; + }; + + spdif_pins: spdif-pins { + marvell,pins = "mpp51"; + marvell,function = "audio"; + }; }; gpio0: gpio@18100 { @@ -298,6 +310,7 @@ reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; #gpio-cells = <2>; #pwm-cells = <2>; interrupt-controller; @@ -316,6 +329,7 @@ reg-names = "gpio", "pwm"; ngpios = <28>; gpio-controller; + gpio-ranges = <&pinctrl 0 32 28>; #gpio-cells = <2>; #pwm-cells = <2>; interrupt-controller; @@ -618,6 +632,18 @@ status = "disabled"; }; + audio_controller: audio-controller@e8000 { + #sound-dai-cells = <1>; + compatible = "marvell,armada-380-audio"; + reg = <0xe8000 0x4000>, <0x18410 0xc>, + <0x18204 0x4>; + reg-names = "i2s_regs", "pll_regs", "soc_ctrl"; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 0>; + clock-names = "internal"; + status = "disabled"; + }; + usb3_0: usb3@f0000 { compatible = "marvell,armada-380-xhci"; reg = <0xf0000 0x4000>,<0xf4000 0x4000>; diff --git a/arch/arm/boot/dts/armada-390-db.dts b/arch/arm/boot/dts/armada-390-db.dts index 0e29474ae9a2..792d0a0184e8 100644 --- a/arch/arm/boot/dts/armada-390-db.dts +++ b/arch/arm/boot/dts/armada-390-db.dts @@ -81,7 +81,7 @@ pinctrl-0 = <&spi1_pins>; pinctrl-names = "default"; - spi-flash@1 { + flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts index fc28308e5bc5..ec6cdbeedde7 100644 --- a/arch/arm/boot/dts/armada-398-db.dts +++ b/arch/arm/boot/dts/armada-398-db.dts @@ -79,7 +79,7 @@ pinctrl-0 = <&spi1_pins>; pinctrl-names = "default"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <0>; compatible = "n25q128a13", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index e0b7c2099831..923b035a3ab3 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -438,16 +438,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -457,16 +467,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -476,16 +496,26 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* @@ -498,16 +528,26 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; clocks = <&gateclk 7>; status = "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index 38a052a0312d..b21ffb819b1d 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -76,16 +76,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index 606fd3476a59..5a74197be0ad 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -69,14 +69,12 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&keys_pin>; pinctrl-names = "default"; - reset { + button-reset { label = "Factory Reset Button"; linux,code = <KEY_SETUP>; gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; @@ -134,7 +132,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts b/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts index a022c68dc943..c28e140b4afc 100644 --- a/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts +++ b/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts @@ -15,7 +15,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi index 32fb21b2bf6a..47b003a81bd4 100644 --- a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi +++ b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi @@ -80,7 +80,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts b/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts index 21f442afab1f..20ba5c823bb2 100644 --- a/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts +++ b/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts @@ -15,7 +15,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi index f3e1a25ca5f2..cab99d8e2911 100644 --- a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi +++ b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi @@ -80,7 +80,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts index e05aee6cdc04..2caa3980fdf6 100644 --- a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts +++ b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts @@ -15,7 +15,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi index c8b1355ce15e..7028482ce4b2 100644 --- a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi +++ b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi @@ -80,7 +80,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts index 8a3aa616bbd0..02bef8dc4270 100644 --- a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts +++ b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts @@ -93,7 +93,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p64"; diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts index 4ec0ae01b61d..d1b61dad0c46 100644 --- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts +++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts @@ -89,7 +89,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p64"; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index 5d04dc68cf57..75318fd0fc11 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -235,7 +235,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p64", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index b4cca507cf13..d1d348b91c0a 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -220,7 +220,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts index 87dcb502f72d..0dad95ea26c2 100644 --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts @@ -164,7 +164,7 @@ }; }; - spi3 { + spi-3 { compatible = "spi-gpio"; status = "okay"; gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index 8480a16919a0..622ac40dd164 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -172,20 +172,18 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&keys_pin>; pinctrl-names = "default"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Factory Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; @@ -255,7 +253,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "everspin,mr25h256"; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 8558bf6bb54c..bf9360f41e0a 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -83,16 +83,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie2: pcie@2,0 { @@ -101,16 +111,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 59>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; clocks = <&gateclk 6>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie3: pcie@3,0 { @@ -119,16 +139,26 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 60>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <2>; clocks = <&gateclk 7>; status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie4: pcie@4,0 { @@ -137,16 +167,26 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 61>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <3>; clocks = <&gateclk 8>; status = "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie5: pcie@5,0 { @@ -155,16 +195,26 @@ reg = <0x2800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 62>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie5_intc 0>, + <0 0 0 2 &pcie5_intc 1>, + <0 0 0 3 &pcie5_intc 2>, + <0 0 0 4 &pcie5_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 9>; status = "disabled"; + + pcie5_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 2d85fe8ac327..0714af52e607 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -98,16 +98,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie2: pcie@2,0 { @@ -116,16 +126,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 59>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; clocks = <&gateclk 6>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie3: pcie@3,0 { @@ -134,16 +154,26 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 60>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <2>; clocks = <&gateclk 7>; status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie4: pcie@4,0 { @@ -152,16 +182,26 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 61>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <3>; clocks = <&gateclk 8>; status = "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie5: pcie@5,0 { @@ -170,16 +210,26 @@ reg = <0x2800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 62>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie5_intc 0>, + <0 0 0 2 &pcie5_intc 1>, + <0 0 0 3 &pcie5_intc 2>, + <0 0 0 4 &pcie5_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 9>; status = "disabled"; + + pcie5_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie6: pcie@6,0 { @@ -188,16 +238,26 @@ reg = <0x3000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 63>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 63>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie6_intc 0>, + <0 0 0 2 &pcie6_intc 1>, + <0 0 0 3 &pcie6_intc 2>, + <0 0 0 4 &pcie6_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <1>; clocks = <&gateclk 10>; status = "disabled"; + + pcie6_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie7: pcie@7,0 { @@ -206,16 +266,26 @@ reg = <0x3800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 64>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 64>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie7_intc 0>, + <0 0 0 2 &pcie7_intc 1>, + <0 0 0 3 &pcie7_intc 2>, + <0 0 0 4 &pcie7_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <2>; clocks = <&gateclk 11>; status = "disabled"; + + pcie7_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie8: pcie@8,0 { @@ -224,16 +294,26 @@ reg = <0x4000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 65>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 65>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie8_intc 0>, + <0 0 0 2 &pcie8_intc 1>, + <0 0 0 3 &pcie8_intc 2>, + <0 0 0 4 &pcie8_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <3>; clocks = <&gateclk 12>; status = "disabled"; + + pcie8_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie9: pcie@9,0 { @@ -242,16 +322,26 @@ reg = <0x4800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 99>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie9_intc 0>, + <0 0 0 2 &pcie9_intc 1>, + <0 0 0 3 &pcie9_intc 2>, + <0 0 0 4 &pcie9_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 26>; status = "disabled"; + + pcie9_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 230a3fd36b30..16185edf9aa5 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -119,16 +119,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie2: pcie@2,0 { @@ -137,16 +147,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 59>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; clocks = <&gateclk 6>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie3: pcie@3,0 { @@ -155,16 +175,26 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 60>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <2>; clocks = <&gateclk 7>; status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie4: pcie@4,0 { @@ -173,16 +203,26 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 61>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <3>; clocks = <&gateclk 8>; status = "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie5: pcie@5,0 { @@ -191,16 +231,26 @@ reg = <0x2800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 62>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie5_intc 0>, + <0 0 0 2 &pcie5_intc 1>, + <0 0 0 3 &pcie5_intc 2>, + <0 0 0 4 &pcie5_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 9>; status = "disabled"; + + pcie5_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie6: pcie@6,0 { @@ -209,16 +259,26 @@ reg = <0x3000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 63>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 63>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie6_intc 0>, + <0 0 0 2 &pcie6_intc 1>, + <0 0 0 3 &pcie6_intc 2>, + <0 0 0 4 &pcie6_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <1>; clocks = <&gateclk 10>; status = "disabled"; + + pcie6_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie7: pcie@7,0 { @@ -227,16 +287,26 @@ reg = <0x3800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 64>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 64>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie7_intc 0>, + <0 0 0 2 &pcie7_intc 1>, + <0 0 0 3 &pcie7_intc 2>, + <0 0 0 4 &pcie7_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <2>; clocks = <&gateclk 11>; status = "disabled"; + + pcie7_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie8: pcie@8,0 { @@ -245,16 +315,26 @@ reg = <0x4000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 65>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 65>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie8_intc 0>, + <0 0 0 2 &pcie8_intc 1>, + <0 0 0 3 &pcie8_intc 2>, + <0 0 0 4 &pcie8_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <3>; clocks = <&gateclk 12>; status = "disabled"; + + pcie8_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie9: pcie@9,0 { @@ -263,16 +343,26 @@ reg = <0x4800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 99>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie9_intc 0>, + <0 0 0 2 &pcie9_intc 1>, + <0 0 0 3 &pcie9_intc 2>, + <0 0 0 4 &pcie9_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 26>; status = "disabled"; + + pcie9_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie10: pcie@a,0 { @@ -281,16 +371,26 @@ reg = <0x5000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 103>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 0x81000000 0 0 0x81000000 0xa 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 103>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie10_intc 0>, + <0 0 0 2 &pcie10_intc 1>, + <0 0 0 3 &pcie10_intc 2>, + <0 0 0 4 &pcie10_intc 3>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; clocks = <&gateclk 27>; status = "disabled"; + + pcie10_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 0efcc166dabf..1ecf72a61bca 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -97,12 +97,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - init { + button-init { label = "Init Button"; linux,code = <KEY_POWER>; gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts index 809e821d7399..5551bac1962c 100644 --- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts @@ -274,7 +274,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q064", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts index d20d95359b28..042a9cc920c6 100644 --- a/arch/arm/boot/dts/artpec6-devboard.dts +++ b/arch/arm/boot/dts/artpec6-devboard.dts @@ -1,10 +1,5 @@ -/* - * Axis ARTPEC-6 development board. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Axis ARTPEC-6 development board. /dts-v1/; #include "artpec6.dtsi" diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index 1d24b394ea4c..a497dd135491 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -5,7 +5,7 @@ / { model = "AST2500 EVB"; - compatible = "aspeed,ast2500"; + compatible = "aspeed,ast2500-evb", "aspeed,ast2500"; aliases { serial4 = &uart5; diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts index dd7148060c4a..f34a2b1ec2f0 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts @@ -5,6 +5,7 @@ / { model = "AST2600 A1 EVB"; + compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600-evb", "aspeed,ast2600"; /delete-node/regulator-vcc-sdhci0; /delete-node/regulator-vcc-sdhci1; diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index b7eb552640cb..de83c0eb1d6e 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -8,7 +8,7 @@ / { model = "AST2600 EVB"; - compatible = "aspeed,ast2600"; + compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; aliases { serial4 = &uart5; @@ -23,6 +23,26 @@ reg = <0x80000000 0x80000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: video { + size = <0x04000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + vcc_sdhci0: regulator-vcc-sdhci0 { compatible = "regulator-fixed"; regulator-name = "SDHCI0 Vcc"; @@ -103,7 +123,7 @@ &mac0 { status = "okay"; - phy-mode = "rgmii"; + phy-mode = "rgmii-rxid"; phy-handle = <ðphy0>; pinctrl-names = "default"; @@ -114,7 +134,7 @@ &mac1 { status = "okay"; - phy-mode = "rgmii"; + phy-mode = "rgmii-rxid"; phy-handle = <ðphy1>; pinctrl-names = "default"; @@ -162,6 +182,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; + spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #include "openbmc-flash-layout-64.dtsi" }; @@ -176,6 +197,7 @@ status = "okay"; m25p,fast-read; label = "pnor"; + spi-rx-bus-width = <4>; spi-max-frequency = <100000000>; }; }; @@ -187,11 +209,6 @@ &i2c0 { status = "okay"; - - temp@2e { - compatible = "adi,adt7490"; - reg = <0x2e>; - }; }; &i2c1 { @@ -220,10 +237,26 @@ &i2c7 { status = "okay"; + + temp@2e { + compatible = "adi,adt7490"; + reg = <0x2e>; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; }; &i2c8 { status = "okay"; + + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; }; &i2c9 { @@ -300,3 +333,18 @@ vqmmc-supply = <&vccq_sdhci1>; clk-phase-sd-hs = <7>, <200>; }; + +&vhub { + status = "okay"; + pinctrl-names = "default"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts b/arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts new file mode 100644 index 000000000000..64bb9bf92de2 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "AMD DaytonaX BMC"; + compatible = "amd,daytonax-bmc", "aspeed,ast2500"; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + aliases { + serial0 = &uart1; + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200"; + }; + + leds { + compatible = "gpio-leds"; + + led-fault { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + + led-identify { + gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, + <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, + <&adc 10>, <&adc 11>, <&adc 12>, <&adc 13>, <&adc 14>, + <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + #include "openbmc-flash-layout.dtsi" + }; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&uart1 { + //Host Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + //BMC Console + status = "okay"; +}; + +&vuart { + status = "okay"; + aspeed,lpc-io-reg = <0x3f8>; + aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "","","led-fault","led-identify","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "id-button","","","","","","","", + /*D0-D7*/ "","","ASSERT_BMC_READY","","","","","", + /*E0-E7*/ "reset-button","reset-control","power-button","power-control","", + "power-good","power-ok","", + /*F0-F7*/ "","","","","","","BATTERY_DETECT","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "FM_BMC_READ_SPD_TEMP","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>, <0x81>; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + + fan@8 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@9 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; + + fan@10 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a>; + }; + + fan@11 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0b>; + }; + + fan@12 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c>; + }; + + fan@13 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0d>; + }; + + fan@14 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0e>; + }; + + fan@15 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0f>; + }; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&vhub { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 4c3c3f1a12ea..d127cbcc7998 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -97,101 +97,6 @@ }; }; - gpio-keys { - compatible = "gpio-keys"; - - shutdown_ack { - label = "SHUTDOWN_ACK"; - gpios = <&gpio ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(G, 2)>; - }; - - reboot_ack { - label = "REBOOT_ACK"; - gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(J, 3)>; - }; - - S0_overtemp { - label = "S0_OVERTEMP"; - gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(G, 3)>; - }; - - S0_hightemp { - label = "S0_HIGHTEMP"; - gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(J, 0)>; - }; - - S0_cpu_fault { - label = "S0_CPU_FAULT"; - gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>; - linux,code = <ASPEED_GPIO(J, 1)>; - }; - - S0_scp_auth_fail { - label = "S0_SCP_AUTH_FAIL"; - gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(J, 2)>; - }; - - S1_scp_auth_fail { - label = "S1_SCP_AUTH_FAIL"; - gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(Z, 5)>; - }; - - S1_overtemp { - label = "S1_OVERTEMP"; - gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(Z, 6)>; - }; - - S1_hightemp { - label = "S1_HIGHTEMP"; - gpios = <&gpio ASPEED_GPIO(AB, 0) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(AB, 0)>; - }; - - S1_cpu_fault { - label = "S1_CPU_FAULT"; - gpios = <&gpio ASPEED_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; - linux,code = <ASPEED_GPIO(Z, 1)>; - }; - - id_button { - label = "ID_BUTTON"; - gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(Q, 5)>; - }; - - psu1_vin_good { - label = "PSU1_VIN_GOOD"; - gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(H, 4)>; - }; - - psu2_vin_good { - label = "PSU2_VIN_GOOD"; - gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(H, 5)>; - }; - - psu1_present { - label = "PSU1_PRESENT"; - gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(I, 0)>; - }; - - psu2_present { - label = "PSU2_PRESENT"; - gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(I, 1)>; - }; - - }; - gpioA0mux: mux-controller { compatible = "gpio-mux"; #mux-control-cells = <0>; @@ -339,17 +244,8 @@ <&adc10mux 0>, <&adc10mux 1>, <&adc11mux 0>, <&adc11mux 1>, <&adc12mux 0>, <&adc12mux 1>, - <&adc13mux 0>, <&adc13mux 1>; - }; - - iio-hwmon-adc14 { - compatible = "iio-hwmon"; - io-channels = <&adc 14>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 15>; + <&adc13mux 0>, <&adc13mux 1>, + <&adc 14>, <&adc 15>; }; }; @@ -362,6 +258,13 @@ /* spi-max-frequency = <50000000>; */ #include "openbmc-flash-layout-64.dtsi" }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; +#include "openbmc-flash-layout-64-alt.dtsi" + }; }; &spi1 { @@ -853,7 +756,7 @@ /*E0-E7*/ "","","","","","","","", /*F0-F7*/ "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD", "S1_DDR_SAVE","","", - /*G0-G7*/ "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","", + /*G0-G7*/ "host0-ready","SHD_REQ_L","","S0_OVERTEMP_L","","", "","", /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","", /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT", @@ -869,7 +772,7 @@ /*Q0-Q7*/ "","","","","","UID_BUTTON","","", /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", "OCP_MAIN_PWREN","RESET_BUTTON","","", - /*S0-S7*/ "","","","","RTC_BAT_SEN_EN","","","", + /*S0-S7*/ "","","","","rtc-battery-voltage-read-enable","","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", /*V0-V7*/ "","","","","","","","", @@ -884,7 +787,7 @@ /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", "BMC_OCP_PG"; - i2c4_o_en { + i2c4-o-en-hog { gpio-hog; gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts new file mode 100644 index 000000000000..606cd4be245a --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts @@ -0,0 +1,546 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2022, Ampere Computing LLC + +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "Ampere Mt.Mitchell BMC"; + compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600"; + + chosen { + stdout-path = &uart5; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: video { + size = <0x04000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + vga_memory: region@bf000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; + }; + + voltage_mon_reg: voltage-mon-regulator { + compatible = "regulator-fixed"; + regulator-name = "ltc2497_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + gpioI5mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + mux-gpios = <&gpio0 ASPEED_GPIO(I, 5) GPIO_ACTIVE_HIGH>; + }; + + adc0mux: adc0mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 0>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc1mux: adc1mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 1>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc2mux: adc2mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 2>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc3mux: adc3mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 3>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc4mux: adc4mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 4>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc5mux: adc5mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 5>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc6mux: adc6mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 6>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc7mux: adc7mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 7>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc8mux: adc8mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 0>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc9mux: adc9mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 1>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc10mux: adc10mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 2>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc11mux: adc11mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 3>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc12mux: adc12mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 4>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc13mux: adc13mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 5>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc14mux: adc14mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 6>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc15mux: adc15mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 7>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0mux 0>, <&adc0mux 1>, + <&adc1mux 0>, <&adc1mux 1>, + <&adc2mux 0>, <&adc2mux 1>, + <&adc3mux 0>, <&adc3mux 1>, + <&adc4mux 0>, <&adc4mux 1>, + <&adc5mux 0>, <&adc5mux 1>, + <&adc6mux 0>, <&adc6mux 1>, + <&adc7mux 0>, <&adc7mux 1>, + <&adc8mux 0>, <&adc8mux 1>, + <&adc9mux 0>, <&adc9mux 1>, + <&adc10mux 0>, <&adc10mux 1>, + <&adc11mux 0>, <&adc11mux 1>, + <&adc12mux 0>, <&adc12mux 1>, + <&adc13mux 0>, <&adc13mux 1>, + <&adc14mux 0>, <&adc14mux 1>, + <&adc15mux 0>, <&adc15mux 1>, + <&adc_i2c 0>, <&adc_i2c 1>, + <&adc_i2c 2>, <&adc_i2c 3>, + <&adc_i2c 4>, <&adc_i2c 5>, + <&adc_i2c 6>, <&adc_i2c 7>, + <&adc_i2c 8>, <&adc_i2c 9>, + <&adc_i2c 10>, <&adc_i2c 11>, + <&adc_i2c 12>, <&adc_i2c 13>, + <&adc_i2c 14>, <&adc_i2c 15>; + }; +}; + +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mac0 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default>; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <20000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + temperature-sensor@2e { + compatible = "adi,adt7490"; + reg = <0x2e>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + psu@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + psu@59 { + compatible = "pmbus"; + reg = <0x59>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + adc_i2c: adc@16 { + compatible = "lltc,ltc2497"; + reg = <0x16>; + vref-supply = <&voltage_mon_reg>; + #io-channel-cells = <1>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-mux@70 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c4_bus70_chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + outlet_temp1: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + psu1_inlet_temp2: temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + }; + + i2c4_bus70_chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + pcie_zone_temp1: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + psu0_inlet_temp2: temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + }; + + i2c4_bus70_chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + pcie_zone_temp2: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + outlet_temp2: temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + }; + + i2c4_bus70_chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + mb_inlet_temp1: temperature-sensor@7c { + compatible = "microchip,emc1413"; + reg = <0x7c>; + }; + mb_inlet_temp2: temperature-sensor@4c { + compatible = "microchip,emc1413"; + reg = <0x4c>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c6 { + status = "okay"; + rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + bmc_ast2600_cpu: temperature-sensor@35 { + compatible = "ti,tmp175"; + reg = <0x35>; + }; +}; + +&adc0 { + ref_voltage = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + ref_voltage = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","i2c2-reset-n","i2c6-reset-n","i2c4-reset-n", + /*B0-B7*/ "","","","","host0-sysreset-n","host0-pmin-n","","", + /*C0-C7*/ "s0-vrd-fault-n","s1-vrd-fault-n","","", + "irq-n","","vrd-sel","spd-sel", + /*D0-D7*/ "presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n", + "","bmc-ncsi-txen","","", + /*E0-E7*/ "","","clk50m-bmc-ncsi","","","","","", + /*F0-F7*/ "s0-pcp-oc-warn-n","s1-pcp-oc-warn-n","power-chassis-control", + "cpu-bios-recover","s0-heartbeat","hs-csout-prochot", + "s0-vr-hot-n","s1-vr-hot-n", + /*G0-G7*/ "","","hsc-12vmain-alt1-n","","","","","", + /*H0-H7*/ "","","wd-disable-n","power-chassis-good","","","","", + /*I0-I7*/ "","","","","","adc-sw","power-button","rtc-battery-voltage-read-enable", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","s0-ddr-save","soc-spi-nor-access","presence-cpu0", + "s0-rtc-lock","","","", + /*N0-N7*/ "hpm-fw-recovery","hpm-stby-rst-n","jtag-sel-s0","led-sw-hb", + "jtag-dbgr-prsnt-n","s1-heartbeat","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "ps0-ac-loss-n","ps1-ac-loss-n","","", + "led-fault","cpld-user-mode","jtag-srst-n","led-bmc-hb", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","identify-button","led-identify", + "s1-ddr-save","spi-nor-access","sys-pgood","presence-cpu1", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n", + "host0-reboot-ack-n","host0-ready","host0-shd-req-n", + "host0-shd-ack-n","s0-overtemp-n", + /*W0-W7*/ "ocp-aux-pwren","ocp-main-pwren","ocp-pgood","", + "bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel", + /*X0-X7*/ "i2c-backup-sel","s1-fault-alert","s1-fw-boot-ok", + "s1-hightemp-n","s0-spi-auth-fail-n","s1-sys-auth-failure-n", + "s1-overtemp-n","s1-spi-auth-fail-n", + /*Y0-Y7*/ "","","","","","","","host0-special-boot", + /*Z0-Z7*/ "reset-button","ps0-pgood","ps1-pgood","","","","",""; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","","","s0-soc-pgood","", + /*18C0-18C7*/ "uart1-mode0","uart1-mode1","uart2-mode0","uart2-mode1", + "uart3-mode0","uart3-mode1","uart4-mode0","uart4-mode1", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "","","",""; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts deleted file mode 100644 index 3395de96ee11..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include <dt-bindings/gpio/aspeed-gpio.h> - -/ { - model = "Qualcomm Centriq 2400 REP AST2520"; - compatible = "qualcomm,centriq2400-rep-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 7>; - }; - - leds { - compatible = "gpio-leds"; - - uid_led { - label = "UID_LED"; - gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - }; - - ras_error_led { - label = "RAS_ERROR_LED"; - gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; - }; - - system_fault { - label = "System_fault"; - gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - }; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2ck_default - &pinctrl_spi2miso_default - &pinctrl_spi2mosi_default - &pinctrl_spi2cs0_default>; -}; - -&uart3 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; - current-speed = <115200>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - tmp421@1e { - compatible = "ti,tmp421"; - reg = <0x1e>; - }; - tmp421@2a { - compatible = "ti,tmp421"; - reg = <0x2a>; - }; - tmp421@4e { - compatible = "ti,tmp421"; - reg = <0x4e>; - }; - tmp421@1c { - compatible = "ti,tmp421"; - reg = <0x1c>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - tmp421@1d { - compatible = "ti,tmp421"; - reg = <0x1d>; - }; - tmp421@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; - tmp421@4d { - compatible = "ti,tmp421"; - reg = <0x4d>; - }; - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - nvt210@4c { - compatible = "nvt210"; - reg = <0x4c>; - }; - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - pagesize = <128>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; - - pca9641@70 { - compatible = "nxp,pca9641"; - reg = <0x70>; - i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - tmp421@1d { - compatible = "tmp421"; - reg = <0x1d>; - }; - adm1278@12 { - compatible = "adi,adm1278"; - reg = <0x12>; - Rsense = <500>; - }; - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - ds1100@58 { - compatible = "ds1100"; - reg = <0x58>; - }; - }; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&gpio { - pin_gpio_c7 { - gpio-hog; - gpios = <ASPEED_GPIO(C, 7) GPIO_ACTIVE_HIGH>; - output; - line-name = "BIOS_SPI_MUX_S"; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts new file mode 100644 index 000000000000..ff4c07c69af1 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/{ + model = "ASRock ROMED8HM3 BMC v1.00"; + compatible = "asrock,romed8hm3-bmc", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + system-fault { + gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; + panic-indicator; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <100000000>; /* 100 MHz */ +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&uart5 { + status = "okay"; +}; + +&vuart { + status = "okay"; + aspeed,lpc-io-reg = <0x2f8>; + aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&i2c0 { + status = "okay"; + + /* inlet temp sensor */ + w83773g@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + /* IPB temp sensor */ + w83773g@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; + + /* IPB PMIC */ + lm25066@40 { + compatible = "lm25066"; + reg = <0x40>; + shunt-resistor-micro-ohms = <1000>; + }; + + /* 12VSB PMIC */ + lm25066@41 { + compatible = "lm25066"; + reg = <0x41>; + shunt-resistor-micro-ohms = <10000>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + + /* Baseboard FRU eeprom */ + eeprom@50 { + compatible = "st,24c128", "atmel,24c128"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&video { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0b>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0c>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0d>; + }; + + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0e>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /* A */ "LOCATORLED_STATUS_N", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI", + "", "", "", "", + /* B */ "POST_COMPLETE_N", "", "", "", "", "", "", "", + /* C */ "", "", "", "", "PCIE_HP_SEL_N", "PCIE_SATA_SEL_N", "LOCATORBTN", "", + /* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON", + "", "", "", "PSU_FAN_FAIL_N", + /* E */ "", "", "", "", "", "", "", "", + /* F */ "NIC_PWR_GOOD", "PRSNTB0", "PRSNTB1", "PRSNTB2", + "PRSNTB3", "", "3VSB_PCIE1_PG", "12V_PCIE1_PG", + /* G */ "HWM_BAT_EN", "CHASSIS_ID0", "CHASSIS_ID1", "CHASSIS_ID2", + "BMC_ALERT1_N_R", "BMC_ALERT2_N_R", "BMC_ALERT3_N", "BMC_ALERT4_N", + /* H */ "X24_C1_PRSNT", "X24_C2_PRSNT", "X24_C3_PRSNT", "FM_MEM_THERM_EVENT_BMC_R_N", + "FACMODE", "BMC_RTCRST", "BMC_HB_LED_N", "BMC_CASEOPEN", + /* I */ "", "", "", "", "", "", "", "", + /* J */ "BMC_READY", "BMC_PCH_BIOS_CS_N", "", "P0_MA_DDR_QS_CS_N", + "", "", "", "", + /* K */ "", "", "", "", "", "", "", "", + /* L */ "", "", "", "", "", "", "", "", + /* M */ "", "", "MEZZ_PWRBRK_N", "OCP_HP_RST_EN", + "MAIN_PWR_EN_G", "BMC_MAIN_EN", "AUX_PWR_EN_G", "BMC_AUX_EN", + /* N */ "", "", "", "", "", "", "", "", + /* O */ "", "", "", "", "", "", "", "", + /* P */ "", "", "", "", "", "", "", "", + /* Q */ "", "", "", "", + "BMC_SMB_PRESENT_1_N", "BMC_SMB_PRESENT_2_N", + "BMC_SMB_PRESENT_3_N", "BMC_PCIE_WAKE_N", + /* R */ "", "", "THERMALTRIP_CLEAR_N", "", "", "", "", "", + /* S */ "", "", "", "", "", "", "", "", + /* T */ "", "", "", "", "", "", "", "", + /* U */ "", "", "", "", "", "", "", "", + /* V */ "", "", "", "", "", "", "", "", + /* W */ "", "", "", "", "", "", "", "", + /* X */ "", "", "", "", "", "", "", "", + /* Y */ "SLP_S3", "SLP_S4_S5", "NODE_ID_1", "NODE_ID_2", "", "", "", "", + /* Z */ "", "", "SYSTEM_FAULT_LED_N", "FAST_THROTTLE_N", + "", "", "", "", + /* AA */ "FM_CPU0_IBMC_THERMTRIP_N", "", "PROCHOT_L_G", "", + "", "", "", "", + /* AB */ "BMC_FORCE_SELFREFRESH", "PWRGD_OUT", "", "IRQ_BMC_PCH_SMI_LPC_N", + "", "", "", "", + /* AC */ "", "", "", "", "", "", "", ""; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts index 0d1fb5ccfd36..f75cad41ae6f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts +++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts @@ -100,7 +100,7 @@ gpio-keys { compatible = "gpio-keys"; - burn-in-signal { + event-burn-in-signal { label = "burn-in"; gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(R, 5)>; @@ -111,139 +111,139 @@ compatible = "gpio-keys-polled"; poll-interval = <1000>; - rear-riser1-presence { + event-rear-riser1-presence { label = "rear-riser1-presence"; gpios = <&pca0 1 GPIO_ACTIVE_LOW>; linux,code = <1>; }; - alrt-pvddq-cpu0 { + event-alrt-pvddq-cpu0 { label = "alrt-pvddq-cpu0"; gpios = <&pca0 8 GPIO_ACTIVE_LOW>; linux,code = <2>; }; - rear-riser0-presence { + event-rear-riser0-presence { label = "rear-riser0-presence"; gpios = <&pca0 9 GPIO_ACTIVE_LOW>; linux,code = <3>; }; - fault-pvddq-cpu0 { + event-fault-pvddq-cpu0 { label = "fault-pvddq-cpu0"; gpios = <&pca0 10 GPIO_ACTIVE_LOW>; linux,code = <4>; }; - alrt-pvddq-cpu1 { + event-alrt-pvddq-cpu1 { label = "alrt-pvddq-cpu1"; gpios = <&pca0 11 GPIO_ACTIVE_LOW>; linux,code = <5>; }; - fault-pvddq-cpu1 { + event-fault-pvddq-cpu1 { label = "alrt-pvddq-cpu1"; gpios = <&pca0 12 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - fault-pvccin-cpu1 { + event-fault-pvccin-cpu1 { label = "fault-pvccin-cpuq"; gpios = <&pca0 13 GPIO_ACTIVE_LOW>; linux,code = <7>; }; - bmc-rom0-wp { + event-bmc-rom0-wp { label = "bmc-rom0-wp"; gpios = <&pca1 0 GPIO_ACTIVE_LOW>; linux,code = <8>; }; - bmc-rom1-wp { + event-bmc-rom1-wp { label = "bmc-rom1-wp"; gpios = <&pca1 1 GPIO_ACTIVE_LOW>; linux,code = <9>; }; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca1 2 GPIO_ACTIVE_LOW>; linux,code = <10>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca1 3 GPIO_ACTIVE_LOW>; linux,code = <11>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca1 4 GPIO_ACTIVE_LOW>; linux,code = <12>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca1 5 GPIO_ACTIVE_LOW>; linux,code = <13>; }; - fan4-presence { + event-fan4-presence { label = "fan4-presence"; gpios = <&pca1 6 GPIO_ACTIVE_LOW>; linux,code = <14>; }; - fan5-presence { + event-fan5-presence { label = "fan5-presence"; gpios = <&pca1 7 GPIO_ACTIVE_LOW>; linux,code = <15>; }; - front-bp1-presence { + event-front-bp1-presence { label = "front-bp1-presence"; gpios = <&pca1 8 GPIO_ACTIVE_LOW>; linux,code = <16>; }; - rear-bp-presence { + event-rear-bp-presence { label = "rear-bp-presence"; gpios = <&pca1 9 GPIO_ACTIVE_LOW>; linux,code = <17>; }; - fault-pvccin-cpu0 { + event-fault-pvccin-cpu0 { label = "fault-pvccin-cpu0"; gpios = <&pca1 10 GPIO_ACTIVE_LOW>; linux,code = <18>; }; - alrt-p1v05-pvcc { + event-alrt-p1v05-pvcc { label = "alrt-p1v05-pvcc1"; gpios = <&pca1 11 GPIO_ACTIVE_LOW>; linux,code = <19>; }; - fault-p1v05-pvccio { + event-fault-p1v05-pvccio { label = "alrt-p1v05-pvcc1"; gpios = <&pca1 12 GPIO_ACTIVE_LOW>; linux,code = <20>; }; - alrt-p1v8-pvccio { + event-alrt-p1v8-pvccio { label = "alrt-p1v8-pvccio"; gpios = <&pca1 13 GPIO_ACTIVE_LOW>; linux,code = <21>; }; - fault-p1v8-pvccio { + event-fault-p1v8-pvccio { label = "fault-p1v8-pvccio"; gpios = <&pca1 14 GPIO_ACTIVE_LOW>; linux,code = <22>; }; - front-bp0-presence { + event-front-bp0-presence { label = "front-bp0-presence"; gpios = <&pca1 15 GPIO_ACTIVE_LOW>; linux,code = <23>; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index f973ea883b97..1fc3e7cbf0d1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -5,6 +5,9 @@ #include "aspeed-g6.dtsi" #include <dt-bindings/gpio/aspeed-gpio.h> #include <dt-bindings/usb/pd.h> +#include <dt-bindings/leds/leds-pca955x.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/i2c/i2c.h> / { model = "Facebook Bletchley BMC"; @@ -31,7 +34,7 @@ <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; }; - spi_gpio: spi-gpio { + spi1_gpio: spi1-gpio { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; @@ -53,115 +56,141 @@ // Fixed link }; - leds { + front_gpio_leds { compatible = "gpio-leds"; - sys_log_id { - retain-state-shutdown; - default-state = "keep"; + default-state = "off"; gpios = <&front_leds 0 GPIO_ACTIVE_HIGH>; }; + }; + + fan_gpio_leds { + compatible = "gpio-leds"; fan0_blue { retain-state-shutdown; default-state = "on"; - gpios = <&fan_ioexp 8 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 8 GPIO_ACTIVE_HIGH>; }; fan1_blue { retain-state-shutdown; default-state = "on"; - gpios = <&fan_ioexp 9 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 9 GPIO_ACTIVE_HIGH>; }; fan2_blue { retain-state-shutdown; default-state = "on"; - gpios = <&fan_ioexp 10 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 10 GPIO_ACTIVE_HIGH>; }; fan3_blue { retain-state-shutdown; default-state = "on"; - gpios = <&fan_ioexp 11 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 11 GPIO_ACTIVE_HIGH>; }; fan0_amber { retain-state-shutdown; default-state = "off"; - gpios = <&fan_ioexp 12 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 12 GPIO_ACTIVE_HIGH>; }; fan1_amber { retain-state-shutdown; default-state = "off"; - gpios = <&fan_ioexp 13 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 13 GPIO_ACTIVE_HIGH>; }; fan2_amber { retain-state-shutdown; default-state = "off"; - gpios = <&fan_ioexp 14 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 14 GPIO_ACTIVE_HIGH>; }; fan3_amber { retain-state-shutdown; default-state = "off"; - gpios = <&fan_ioexp 15 GPIO_ACTIVE_HIGH>; - }; - sled0_amber { - retain-state-shutdown; - default-state = "off"; - gpios = <&sled0_leds 0 GPIO_ACTIVE_LOW>; - }; - sled0_blue { - retain-state-shutdown; - default-state = "off"; - gpios = <&sled0_leds 1 GPIO_ACTIVE_LOW>; + gpios = <&fan_leds 15 GPIO_ACTIVE_HIGH>; }; + }; + + sled1_gpio_leds { + compatible = "gpio-leds"; sled1_amber { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled1_leds 0 GPIO_ACTIVE_LOW>; }; sled1_blue { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled1_leds 1 GPIO_ACTIVE_LOW>; }; + }; + + sled2_gpio_leds { + compatible = "gpio-leds"; sled2_amber { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled2_leds 0 GPIO_ACTIVE_LOW>; }; sled2_blue { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled2_leds 1 GPIO_ACTIVE_LOW>; }; + }; + + sled3_gpio_leds { + compatible = "gpio-leds"; sled3_amber { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled3_leds 0 GPIO_ACTIVE_LOW>; }; sled3_blue { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled3_leds 1 GPIO_ACTIVE_LOW>; }; + }; + + sled4_gpio_leds { + compatible = "gpio-leds"; sled4_amber { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled4_leds 0 GPIO_ACTIVE_LOW>; }; sled4_blue { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled4_leds 1 GPIO_ACTIVE_LOW>; }; + }; + + sled5_gpio_leds { + compatible = "gpio-leds"; sled5_amber { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled5_leds 0 GPIO_ACTIVE_LOW>; }; sled5_blue { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled5_leds 1 GPIO_ACTIVE_LOW>; }; }; + + sled6_gpio_leds { + compatible = "gpio-leds"; + sled6_amber { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled6_leds 0 GPIO_ACTIVE_LOW>; + }; + sled6_blue { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled6_leds 1 GPIO_ACTIVE_LOW>; + }; + }; }; &mac2 { @@ -177,10 +206,6 @@ }; }; -&rtc { - status = "okay"; -}; - &fmc { status = "okay"; flash@0 { @@ -190,6 +215,12 @@ spi-max-frequency = <50000000>; #include "openbmc-flash-layout-128.dtsi" }; + flash@1 { + status = "okay"; + m25p,fast-read; + label = "flash1"; + spi-max-frequency = <50000000>; + }; }; &spi2 { @@ -201,13 +232,17 @@ status = "okay"; m25p,fast-read; label = "pnor"; - spi-max-frequency = <100000000>; + spi-max-frequency = <50000000>; }; }; &i2c0 { status = "okay"; - /* TODO: Add ADC INA230 */ + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; mp5023@40 { compatible = "mps,mp5023"; @@ -219,7 +254,18 @@ reg = <0x4f>; }; - sled0_ioexp: pca9539@76 { + sled1_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED1_SWD_MUX", "SLED1_XRES_SWD_N", + "SLED1_CLKREQ_N", "SLED1_PCIE_PWR_EN"; + }; + + sled1_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; #address-cells = <1>; @@ -227,14 +273,17 @@ gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(M, 0) IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = - "SLED0_MS_DETECT1","SLED0_VBUS_BMC_EN","SLED0_INA230_ALERT","SLED0_P12V_STBY_ALERT", - "SLED0_SSD_ALERT","SLED0_MS_DETECT0","SLED0_RST_CCG5","SLED0_FUSB302_INT", - "SLED0_MD_STBY_RESET","SLED0_MD_IOEXP_EN_FAULT","SLED0_MD_DIR","SLED0_MD_DECAY", - "SLED0_MD_MODE1","SLED0_MD_MODE2","SLED0_MD_MODE3","power-host0"; + "SLED1_MS_DETECT1","SLED1_VBUS_BMC_EN","SLED1_INA230_ALERT","SLED1_P12V_STBY_ALERT", + "SLED1_SSD_ALERT","SLED1_MS_DETECT0","SLED1_RST_CCG5","SLED1_FUSB302_INT", + "SLED1_MD_STBY_RESET","SLED1_MD_IOEXP_EN_FAULT","SLED1_MD_DIR","SLED1_MD_DECAY", + "SLED1_MD_MODE1","SLED1_MD_MODE2","SLED1_MD_MODE3","power-host1"; }; - sled0_leds: pca9552@67 { + sled1_leds: pca9552@67 { compatible = "nxp,pca9552"; reg = <0x67>; #address-cells = <1>; @@ -243,13 +292,13 @@ #gpio-cells = <2>; gpio-line-names = - "led-sled0-amber","led-sled0-blue","SLED0_RST_IOEXP","", + "led-sled1-amber","led-sled1-blue","SLED1_RST_IOEXP","SLED1_MD_REF_PWM", "","","","", "","","","", "","","",""; }; - sled0_fusb302: typec-portc@22 { + sled1_fusb302: typec-portc@22 { compatible = "fcs,fusb302"; reg = <0x22>; @@ -266,11 +315,20 @@ op-sink-microwatt = <10000000>; }; }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; }; &i2c1 { status = "okay"; - /* TODO: Add ADC INA230 */ + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; mp5023@40 { compatible = "mps,mp5023"; @@ -282,7 +340,18 @@ reg = <0x4f>; }; - sled1_ioexp: pca9539@76 { + sled2_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED2_SWD_MUX", "SLED2_XRES_SWD_N", + "SLED2_CLKREQ_N", "SLED2_PCIE_PWR_EN"; + }; + + sled2_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; #address-cells = <1>; @@ -290,14 +359,17 @@ gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(M, 1) IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = - "SLED1_MS_DETECT1","SLED1_VBUS_BMC_EN","SLED1_INA230_ALERT","SLED1_P12V_STBY_ALERT", - "SLED1_SSD_ALERT","SLED1_MS_DETECT0","SLED1_RST_CCG5","SLED1_FUSB302_INT", - "SLED1_MD_STBY_RESET","SLED1_MD_IOEXP_EN_FAULT","SLED1_MD_DIR","SLED1_MD_DECAY", - "SLED1_MD_MODE1","SLED1_MD_MODE2","SLED1_MD_MODE3","power-host1"; + "SLED2_MS_DETECT1","SLED2_VBUS_BMC_EN","SLED2_INA230_ALERT","SLED2_P12V_STBY_ALERT", + "SLED2_SSD_ALERT","SLED2_MS_DETECT0","SLED2_RST_CCG5","SLED2_FUSB302_INT", + "SLED2_MD_STBY_RESET","SLED2_MD_IOEXP_EN_FAULT","SLED2_MD_DIR","SLED2_MD_DECAY", + "SLED2_MD_MODE1","SLED2_MD_MODE2","SLED2_MD_MODE3","power-host2"; }; - sled1_leds: pca9552@67 { + sled2_leds: pca9552@67 { compatible = "nxp,pca9552"; reg = <0x67>; #address-cells = <1>; @@ -306,13 +378,13 @@ #gpio-cells = <2>; gpio-line-names = - "led-sled1-amber","led-sled1-blue","SLED1_RST_IOEXP","", + "led-sled2-amber","led-sled2-blue","SLED2_RST_IOEXP","SLED2_MD_REF_PWM", "","","","", "","","","", "","","",""; }; - sled1_fusb302: typec-portc@22 { + sled2_fusb302: typec-portc@22 { compatible = "fcs,fusb302"; reg = <0x22>; @@ -329,15 +401,20 @@ op-sink-microwatt = <10000000>; }; }; -}; -&i2c1 { - status = "okay"; + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; }; &i2c2 { status = "okay"; - /* TODO: Add ADC INA230 */ + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; mp5023@40 { compatible = "mps,mp5023"; @@ -349,7 +426,18 @@ reg = <0x4f>; }; - sled2_ioexp: pca9539@76 { + sled3_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED3_SWD_MUX", "SLED3_XRES_SWD_N", + "SLED3_CLKREQ_N", "SLED3_PCIE_PWR_EN"; + }; + + sled3_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; #address-cells = <1>; @@ -357,14 +445,17 @@ gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(M, 2) IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = - "SLED2_MS_DETECT1","SLED2_VBUS_BMC_EN","SLED2_INA230_ALERT","SLED2_P12V_STBY_ALERT", - "SLED2_SSD_ALERT","SLED2_MS_DETECT0","SLED2_RST_CCG5","SLED2_FUSB302_INT", - "SLED2_MD_STBY_RESET","SLED2_MD_IOEXP_EN_FAULT","SLED2_MD_DIR","SLED2_MD_DECAY", - "SLED2_MD_MODE1","SLED2_MD_MODE2","SLED2_MD_MODE3","power-host2"; + "SLED3_MS_DETECT1","SLED3_VBUS_BMC_EN","SLED3_INA230_ALERT","SLED3_P12V_STBY_ALERT", + "SLED3_SSD_ALERT","SLED3_MS_DETECT0","SLED3_RST_CCG5","SLED3_FUSB302_INT", + "SLED3_MD_STBY_RESET","SLED3_MD_IOEXP_EN_FAULT","SLED3_MD_DIR","SLED3_MD_DECAY", + "SLED3_MD_MODE1","SLED3_MD_MODE2","SLED3_MD_MODE3","power-host3"; }; - sled2_leds: pca9552@67 { + sled3_leds: pca9552@67 { compatible = "nxp,pca9552"; reg = <0x67>; #address-cells = <1>; @@ -373,13 +464,13 @@ #gpio-cells = <2>; gpio-line-names = - "led-sled2-amber","led-sled2-blue","SLED2_RST_IOEXP","", + "led-sled3-amber","led-sled3-blue","SLED3_RST_IOEXP","SLED3_MD_REF_PWM", "","","","", "","","","", "","","",""; }; - sled2_fusb302: typec-portc@22 { + sled3_fusb302: typec-portc@22 { compatible = "fcs,fusb302"; reg = <0x22>; @@ -396,11 +487,20 @@ op-sink-microwatt = <10000000>; }; }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; }; &i2c3 { status = "okay"; - /* TODO: Add ADC INA230 */ + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; mp5023@40 { compatible = "mps,mp5023"; @@ -412,7 +512,18 @@ reg = <0x4f>; }; - sled3_ioexp: pca9539@76 { + sled4_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED4_SWD_MUX", "SLED4_XRES_SWD_N", + "SLED4_CLKREQ_N", "SLED4_PCIE_PWR_EN"; + }; + + sled4_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; #address-cells = <1>; @@ -420,14 +531,17 @@ gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(M, 3) IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = - "SLED3_MS_DETECT1","SLED3_VBUS_BMC_EN","SLED3_INA230_ALERT","SLED3_P12V_STBY_ALERT", - "SLED3_SSD_ALERT","SLED3_MS_DETECT0","SLED3_RST_CCG5","SLED3_FUSB302_INT", - "SLED3_MD_STBY_RESET","SLED3_MD_IOEXP_EN_FAULT","SLED3_MD_DIR","SLED3_MD_DECAY", - "SLED3_MD_MODE1","SLED3_MD_MODE2","SLED3_MD_MODE3","power-host3"; + "SLED4_MS_DETECT1","SLED4_VBUS_BMC_EN","SLED4_INA230_ALERT","SLED4_P12V_STBY_ALERT", + "SLED4_SSD_ALERT","SLED4_MS_DETECT0","SLED4_RST_CCG5","SLED4_FUSB302_INT", + "SLED4_MD_STBY_RESET","SLED4_MD_IOEXP_EN_FAULT","SLED4_MD_DIR","SLED4_MD_DECAY", + "SLED4_MD_MODE1","SLED4_MD_MODE2","SLED4_MD_MODE3","power-host4"; }; - sled3_leds: pca9552@67 { + sled4_leds: pca9552@67 { compatible = "nxp,pca9552"; reg = <0x67>; #address-cells = <1>; @@ -436,13 +550,13 @@ #gpio-cells = <2>; gpio-line-names = - "led-sled3-amber","led-sled3-blue","SLED3_RST_IOEXP","", + "led-sled4-amber","led-sled4-blue","SLED4_RST_IOEXP","SLED4_MD_REF_PWM", "","","","", "","","","", "","","",""; }; - sled3_fusb302: typec-portc@22 { + sled4_fusb302: typec-portc@22 { compatible = "fcs,fusb302"; reg = <0x22>; @@ -459,11 +573,20 @@ op-sink-microwatt = <10000000>; }; }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; }; &i2c4 { status = "okay"; - /* TODO: Add ADC INA230 */ + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; mp5023@40 { compatible = "mps,mp5023"; @@ -475,7 +598,18 @@ reg = <0x4f>; }; - sled4_ioexp: pca9539@76 { + sled5_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED5_SWD_MUX", "SLED5_XRES_SWD_N", + "SLED5_CLKREQ_N", "SLED5_PCIE_PWR_EN"; + }; + + sled5_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; #address-cells = <1>; @@ -483,14 +617,17 @@ gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(M, 4) IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = - "SLED4_MS_DETECT1","SLED4_VBUS_BMC_EN","SLED4_INA230_ALERT","SLED4_P12V_STBY_ALERT", - "SLED4_SSD_ALERT","SLED4_MS_DETECT0","SLED4_RST_CCG5","SLED4_FUSB302_INT", - "SLED4_MD_STBY_RESET","SLED4_MD_IOEXP_EN_FAULT","SLED4_MD_DIR","SLED4_MD_DECAY", - "SLED4_MD_MODE1","SLED4_MD_MODE2","SLED4_MD_MODE3","power-host4"; + "SLED5_MS_DETECT1","SLED5_VBUS_BMC_EN","SLED5_INA230_ALERT","SLED5_P12V_STBY_ALERT", + "SLED5_SSD_ALERT","SLED5_MS_DETECT0","SLED5_RST_CCG5","SLED5_FUSB302_INT", + "SLED5_MD_STBY_RESET","SLED5_MD_IOEXP_EN_FAULT","SLED5_MD_DIR","SLED5_MD_DECAY", + "SLED5_MD_MODE1","SLED5_MD_MODE2","SLED5_MD_MODE3","power-host5"; }; - sled4_leds: pca9552@67 { + sled5_leds: pca9552@67 { compatible = "nxp,pca9552"; reg = <0x67>; #address-cells = <1>; @@ -499,13 +636,13 @@ #gpio-cells = <2>; gpio-line-names = - "led-sled4-amber","led-sled4-blue","SLED4_RST_IOEXP","", + "led-sled5-amber","led-sled5-blue","SLED5_RST_IOEXP","SLED5_MD_REF_PWM", "","","","", "","","","", "","","",""; }; - sled4_fusb302: typec-portc@22 { + sled5_fusb302: typec-portc@22 { compatible = "fcs,fusb302"; reg = <0x22>; @@ -522,11 +659,20 @@ op-sink-microwatt = <10000000>; }; }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; }; &i2c5 { status = "okay"; - /* TODO: Add ADC INA230 */ + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; mp5023@40 { compatible = "mps,mp5023"; @@ -538,7 +684,18 @@ reg = <0x4f>; }; - sled5_ioexp: pca9539@76 { + sled6_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED6_SWD_MUX", "SLED6_XRES_SWD_N", + "SLED6_CLKREQ_N", "SLED6_PCIE_PWR_EN"; + }; + + sled6_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; #address-cells = <1>; @@ -546,14 +703,17 @@ gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(M, 5) IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = - "SLED5_MS_DETECT1","SLED5_VBUS_BMC_EN","SLED5_INA230_ALERT","SLED5_P12V_STBY_ALERT", - "SLED5_SSD_ALERT","SLED5_MS_DETECT0","SLED5_RST_CCG5","SLED5_FUSB302_INT", - "SLED5_MD_STBY_RESET","SLED5_MD_IOEXP_EN_FAULT","SLED5_MD_DIR","SLED5_MD_DECAY", - "SLED5_MD_MODE1","SLED5_MD_MODE2","SLED5_MD_MODE3","power-host5"; + "SLED6_MS_DETECT1","SLED6_VBUS_BMC_EN","SLED6_INA230_ALERT","SLED6_P12V_STBY_ALERT", + "SLED6_SSD_ALERT","SLED6_MS_DETECT0","SLED6_RST_CCG5","SLED6_FUSB302_INT", + "SLED6_MD_STBY_RESET","SLED6_MD_IOEXP_EN_FAULT","SLED6_MD_DIR","SLED6_MD_DECAY", + "SLED6_MD_MODE1","SLED6_MD_MODE2","SLED6_MD_MODE3","power-host6"; }; - sled5_leds: pca9552@67 { + sled6_leds: pca9552@67 { compatible = "nxp,pca9552"; reg = <0x67>; #address-cells = <1>; @@ -562,13 +722,13 @@ #gpio-cells = <2>; gpio-line-names = - "led-sled5-amber","led-sled5-blue","SLED5_RST_IOEXP","", + "led-sled6-amber","led-sled6-blue","SLED6_RST_IOEXP","SLED6_MD_REF_PWM", "","","","", "","","","", "","","",""; }; - sled5_fusb302: typec-portc@22 { + sled6_fusb302: typec-portc@22 { compatible = "fcs,fusb302"; reg = <0x22>; @@ -585,6 +745,11 @@ op-sink-microwatt = <10000000>; }; }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; }; &i2c6 { @@ -596,6 +761,7 @@ }; rtc@51 { + /* in-chip rtc disabled, use external rtc (battery-backed) */ compatible = "nxp,pcf85263"; reg = <0x51>; }; @@ -627,11 +793,6 @@ reg = <0x4f>; }; - hdc1080@40 { - compatible = "ti,hdc1080"; - reg = <0x40>; - }; - front_leds: pca9552@67 { compatible = "nxp,pca9552"; reg = <0x67>; @@ -655,6 +816,9 @@ adm1278@11 { compatible = "adi,adm1278"; reg = <0x11>; + shunt-resistor-micro-ohms = <300>; + adi,volt-curr-sample-average = <128>; + adi,power-sample-average = <128>; }; tmp421@4c { @@ -667,7 +831,7 @@ reg = <0x4d>; }; - fan_ioexp: pca9552@67 { + fan_leds: pca9552@67 { compatible = "nxp,pca9552"; reg = <0x67>; #address-cells = <1>; @@ -689,47 +853,68 @@ multi-master; aspeed,hw-timeout-ms = <1000>; status = "okay"; + + //USB Debug Connector + ipmb13@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; }; &gpio0 { gpio-line-names = /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "","","SEL_SPI2_MUX","SPI2_MUX1", - "SPI2_MUX2","SPI2_MUX3","","", + /*B0-B7*/ "FUSB302_SLED1_INT_N","FUSB302_SLED2_INT_N", + "SEL_SPI2_MUX","SPI2_MUX1", + "SPI2_MUX2","SPI2_MUX3", + "","FUSB302_SLED3_INT_N", /*C0-C7*/ "","","","","","","","", /*D0-D7*/ "","","","","","","","", /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","","","","","","", - /*G0-G7*/ "","SWITCH_FRU_MUX","","","","","","", + /*F0-F7*/ "BMC_SLED1_STCK","BMC_SLED2_STCK", + "BMC_SLED3_STCK","BMC_SLED4_STCK", + "BMC_SLED5_STCK","BMC_SLED6_STCK", + "","", + /*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","FM_SOL_UART_CH_SEL", + "PWRGD_P1V05_VDDCORE","PWRGD_P1V5_VDD","","", /*H0-H7*/ "presence-riser1","presence-riser2", - "presence-sled0","presence-sled1", - "presence-sled2","presence-sled3", - "presence-sled4","presence-sled5", - /*I0-I7*/ "REV_ID0","","REV_ID1","REV_ID2", - "","","","", + "presence-sled1","presence-sled2", + "presence-sled3","presence-sled4", + "presence-sled5","presence-sled6", + /*I0-I7*/ "REV_ID0","", + "REV_ID1","REV_ID2", + "","BSM_FLASH_WP_STATUS", + "BMC_TPM_PRES_N","FUSB302_SLED6_INT_N", /*J0-J7*/ "","","","","","","","", /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "ALERT_SLED0","ALERT_SLED1", - "ALERT_SLED2","ALERT_SLED3", - "ALERT_SLED4","ALERT_SLED5", - "P12V_AUX_ALERT1","", - /*N0-N7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","BMC_RTC_INT","","", + /*M0-M7*/ "ALERT_SLED1_N","ALERT_SLED2_N", + "ALERT_SLED3_N","ALERT_SLED4_N", + "ALERT_SLED5_N","ALERT_SLED6_N", + "","", + /*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1", + "LED_POSTCODE_2","LED_POSTCODE_3", + "LED_POSTCODE_4","LED_POSTCODE_5", + "LED_POSTCODE_5","LED_POSTCODE_7", /*O0-O7*/ "","","","", "","BOARD_ID0","BOARD_ID1","BOARD_ID2", - /*P0-P7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","BMC_HEARTBEAT", /*Q0-Q7*/ "","","","","","","","", /*R0-R7*/ "","","","","","","","", /*S0-S7*/ "","","","BAT_DETECT", - "BMC_BT_WP0","BMC_BT_WP1","","", + "BMC_BT_WP0_N","BMC_BT_WP1_N","","FUSB302_SLED4_INT_N", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","RST_BMC_MVL","","", + /*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL_N", + "P12V_AUX_ALERT1_N","PSU_PRSNT", "USB2_SEL0_A","USB2_SEL1_A", "USB2_SEL0_B","USB2_SEL1_B", - /*W0-W7*/ "RST_FRONT_IOEXP","","","","","","","", + /*W0-W7*/ "RST_FRONT_IOEXP_N","","","","","","","", /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","BSM_FLASH_LATCH","","","","","", + /*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT_N", + "BSM_FLASH_LATCH_N","FUSB302_SLED5_INT_N", + "","","","", /*Z0-Z7*/ "","","","","","","",""; }; @@ -754,3 +939,17 @@ &pinctrl_adc12_default &pinctrl_adc13_default &pinctrl_adc14_default &pinctrl_adc15_default>; }; + +&mdio0 { + status = "okay"; + /* TODO: Add Marvell 88E6191X */ +}; + +&mdio3 { + status = "okay"; + /* TODO: Add Marvell 88X3310 */ +}; + +&ehci0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts index 27b43fe099f1..8e1a1d1b282d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts @@ -183,3 +183,21 @@ &i2c11 { status = "okay"; }; + +/* + * BMC's "mac3" controller is connected to BCM53134P's IMP_RGMII port + * directly (fixed link, no PHY in between). + * Note: BMC's "mdio0" controller is connected to BCM53134P's MDIO + * interface, and the MDIO channel will be enabled in dts later, when + * BCM53134 is added to "bcm53xx" DSA driver. + */ +&mac3 { + status = "okay"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts index 8864e9c312a8..6bf2ff85a40e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts @@ -207,11 +207,16 @@ &i2c12 { status = "okay"; - //MEZZ_FRU - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - pagesize = <32>; +}; + +&i2c13 { + status = "okay"; + // Debug Card + multi-master; + ipmb13@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 22c06ff7a7ed..a6a2bc3b855c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -171,9 +171,10 @@ /* 48MB region from the end of flash to start of vga memory */ ramoops@bc000000 { compatible = "ramoops"; - reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ + reg = <0xbc000000 0x200000>; /* 16 * (4 * 0x8000) */ record-size = <0x8000>; console-size = <0x8000>; + ftrace-size = <0x8000>; pmsg-size = <0x8000>; max-reason = <3>; /* KMSG_DUMP_EMERG */ }; @@ -188,29 +189,27 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca0 15 GPIO_ACTIVE_LOW>; linux,code = <15>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca0 14 GPIO_ACTIVE_LOW>; linux,code = <14>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca0 13 GPIO_ACTIVE_LOW>; linux,code = <13>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca0 12 GPIO_ACTIVE_LOW>; linux,code = <12>; @@ -269,9 +268,7 @@ /*C0-C7*/ "","","","","","","","", /*D0-D7*/ "","","","","","","","", /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "PIN_HOLE_RESET_IN_N","","", - "PIN_HOLE_RESET_OUT_N","","", - "factory-reset-toggle","", + /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","factory-reset-toggle","", /*G0-G7*/ "","","","","","","","", /*H0-H7*/ "led-rtc-battery","led-bmc","led-rear-enc-id0","led-rear-enc-fault0","","","","", /*I0-I7*/ "","","","","","","bmc-secure-boot","", @@ -284,7 +281,7 @@ /*P0-P7*/ "","","","","led-pcieslot-power","","","", /*Q0-Q7*/ "","","regulator-standby-faulted","","","","","", /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","", - /*S0-S7*/ "","","","","","","","", + /*S0-S7*/ "","","","","power-ffs-sync-history","","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", /*V0-V7*/ "","BMC_3RESTART_ATTEMPT_P","","","","","","", @@ -2394,6 +2391,10 @@ status = "okay"; }; +&uhci { + status = "okay"; +}; + &emmc_controller { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index c47974219832..bf59a9962379 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -102,9 +102,10 @@ ramoops@bc000000 { compatible = "ramoops"; - reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ + reg = <0xbc000000 0x200000>; /* 16 * (4 * 0x8000) */ record-size = <0x8000>; console-size = <0x8000>; + ftrace-size = <0x8000>; pmsg-size = <0x8000>; max-reason = <3>; /* KMSG_DUMP_EMERG */ }; @@ -178,41 +179,39 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca0 6 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca0 7 GPIO_ACTIVE_LOW>; linux,code = <7>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca0 8 GPIO_ACTIVE_LOW>; linux,code = <8>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca0 9 GPIO_ACTIVE_LOW>; linux,code = <9>; }; - fan4-presence { + event-fan4-presence { label = "fan4-presence"; gpios = <&pca0 10 GPIO_ACTIVE_LOW>; linux,code = <10>; }; - fan5-presence { + event-fan5-presence { label = "fan5-presence"; gpios = <&pca0 11 GPIO_ACTIVE_LOW>; linux,code = <11>; @@ -239,6 +238,10 @@ status = "okay"; }; +&uhci { + status = "okay"; +}; + &gpio0 { gpio-line-names = /*A0-A7*/ "","","","","","","","", @@ -246,7 +249,7 @@ /*C0-C7*/ "","","","","","","","", /*D0-D7*/ "","","","","","","","", /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","","","","","factory-reset-toggle","", + /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","factory-reset-toggle","", /*G0-G7*/ "","","","","","","","", /*H0-H7*/ "","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","", /*I0-I7*/ "","","","","","","bmc-secure-boot","", @@ -260,7 +263,7 @@ /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","", /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","", /*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3", - "","","","", + "power-ffs-sync-history","","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", /*V0-V7*/ "","","","","","","","", @@ -2360,30 +2363,6 @@ use-ncsi; }; -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-128.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; - }; -}; - &wdt1 { aspeed,reset-type = "none"; aspeed,external-signal; diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts index 60a39ea10ab1..208b0f094ed9 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts @@ -73,19 +73,19 @@ gpio-keys { compatible = "gpio-keys"; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(B, 3)>; }; - ps0-presence { + event-ps0-presence { label = "ps0-presence"; gpios = <&gpio ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 0)>; }; - ps1-presence { + event-ps1-presence { label = "ps1-presence"; gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 1)>; @@ -97,49 +97,49 @@ compatible = "gpio-keys-polled"; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca1 0 GPIO_ACTIVE_LOW>; linux,code = <1>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca1 1 GPIO_ACTIVE_LOW>; linux,code = <2>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca1 2 GPIO_ACTIVE_LOW>; linux,code = <3>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca1 3 GPIO_ACTIVE_LOW>; linux,code = <4>; }; - fan4-presence { + event-fan4-presence { label = "fan4-presence"; gpios = <&pca1 4 GPIO_ACTIVE_LOW>; linux,code = <5>; }; - fan5-presence { + event-fan5-presence { label = "fan5-presence"; gpios = <&pca1 5 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - fan6-presence { + event-fan6-presence { label = "fan6-presence"; gpios = <&pca1 6 GPIO_ACTIVE_LOW>; linux,code = <7>; }; - fan7-presence { + event-fan7-presence { label = "fan7-presence"; gpios = <&pca1 7 GPIO_ACTIVE_LOW>; linux,code = <8>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts index a52a289cee85..48776fb663fb 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts @@ -92,30 +92,31 @@ gpio-keys { compatible = "gpio-keys"; - air-water { + event-air-water { label = "air-water"; gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 6)>; }; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; }; - ps0-presence { + event-ps0-presence { label = "ps0-presence"; gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(Z, 2)>; }; - ps1-presence { + event-ps1-presence { label = "ps1-presence"; gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(Z, 0)>; }; - id-button { + + button-id { label = "id-button"; gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 1)>; @@ -126,37 +127,37 @@ compatible = "gpio-keys-polled"; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; linux,code = <9>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; linux,code = <10>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; linux,code = <11>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; linux,code = <12>; }; - fan4-presence { + event-fan4-presence { label = "fan4-presence"; gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; linux,code = <13>; }; - fan5-presence { + event-fan5-presence { label = "fan5-presence"; gpios = <&pca9552 14 GPIO_ACTIVE_LOW>; linux,code = <14>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts index 7d38d121ec6d..31ff19ef87a0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts @@ -46,31 +46,31 @@ gpio-keys { compatible = "gpio-keys"; - air-water { + event-air-water { label = "air-water"; gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 6)>; }; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; }; - ps0-presence { + event-ps0-presence { label = "ps0-presence"; gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(Z, 2)>; }; - ps1-presence { + event-ps1-presence { label = "ps1-presence"; gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(Z, 0)>; }; - id-button { + button-id { label = "id-button"; gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 1)>; @@ -81,31 +81,31 @@ compatible = "gpio-keys-polled"; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; linux,code = <9>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; linux,code = <10>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; linux,code = <11>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; linux,code = <12>; }; - fan4-presence { + event-fan4-presence { label = "fan4-presence"; gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; linux,code = <13>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts index 3d4bdad27c2d..ac0d666ca10e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts @@ -96,7 +96,7 @@ gpio-keys { compatible = "gpio-keys"; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index cd660c1ff3f5..45631b47a7b3 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -73,7 +73,7 @@ gpio-keys { compatible = "gpio-keys"; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(P, 5)>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 084f54866f38..893e621ecab1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -87,7 +87,7 @@ gpio-keys { compatible = "gpio-keys"; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts index 4816486c0c9e..bbf864f84d37 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts @@ -38,37 +38,37 @@ gpio-keys { compatible = "gpio-keys"; - air-water { + event-air-water { label = "air-water"; gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(B, 5)>; }; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; }; - ps0-presence { + event-ps0-presence { label = "ps0-presence"; gpios = <&gpio ASPEED_GPIO(R, 7) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(R, 7)>; }; - ps1-presence { + event-ps1-presence { label = "ps1-presence"; gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(N, 0)>; }; - oppanel-presence { + event-oppanel-presence { label = "oppanel-presence"; gpios = <&gpio ASPEED_GPIO(A, 7) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(A, 7)>; }; - opencapi-riser-presence { + event-opencapi-riser-presence { label = "opencapi-riser-presence"; gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(I, 0)>; @@ -84,55 +84,55 @@ compatible = "gpio-keys-polled"; poll-interval = <1000>; - scm0-presence { + event-scm0-presence { label = "scm0-presence"; gpios = <&pca9552 6 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - scm1-presence { + event-scm1-presence { label = "scm1-presence"; gpios = <&pca9552 7 GPIO_ACTIVE_LOW>; linux,code = <7>; }; - cpu0vrm-presence { + event-cpu0vrm-presence { label = "cpu0vrm-presence"; gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; linux,code = <12>; }; - cpu1vrm-presence { + event-cpu1vrm-presence { label = "cpu1vrm-presence"; gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; linux,code = <13>; }; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca0 5 GPIO_ACTIVE_LOW>; linux,code = <5>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca0 6 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca0 7 GPIO_ACTIVE_LOW>; linux,code = <7>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca0 8 GPIO_ACTIVE_LOW>; linux,code = <8>; }; - fanboost-presence { + event-fanboost-presence { label = "fanboost-presence"; gpios = <&pca0 9 GPIO_ACTIVE_LOW>; linux,code = <9>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index e39f310d55eb..3f6010ef2b86 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -50,13 +50,13 @@ gpio-keys { compatible = "gpio-keys"; - ps0-presence { + event-ps0-presence { label = "ps0-presence"; gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(H, 3)>; }; - ps1-presence { + event-ps1-presence { label = "ps1-presence"; gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(E, 5)>; @@ -65,29 +65,27 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca0 4 GPIO_ACTIVE_LOW>; linux,code = <4>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca0 5 GPIO_ACTIVE_LOW>; linux,code = <5>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca0 6 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca0 7 GPIO_ACTIVE_LOW>; linux,code = <7>; @@ -197,7 +195,6 @@ fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>; cfam@0,0 { reg = <0 0>; @@ -877,3 +874,14 @@ status = "okay"; memory-region = <&vga_memory>; }; + +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8 0xcac>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts index 328ef472c479..8a7fb55ab489 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts @@ -63,13 +63,13 @@ gpio-keys { compatible = "gpio-keys"; - button_checkstop { + event-checkstop { label = "checkstop"; linux,code = <74>; gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; }; - button_identify { + event-identify { label = "identify"; linux,code = <152>; gpios = <&gpio ASPEED_GPIO(O, 7) GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 230f3584bcab..a20a532fc280 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -51,25 +51,25 @@ gpio-keys { compatible = "gpio-keys"; - air-water { + event-air-water { label = "air-water"; gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(B, 5)>; }; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; }; - ps0-presence { + event-ps0-presence { label = "ps0-presence"; gpios = <&gpio ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(P, 7)>; }; - ps1-presence { + event-ps1-presence { label = "ps1-presence"; gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(N, 0)>; @@ -85,25 +85,25 @@ compatible = "gpio-keys-polled"; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca0 4 GPIO_ACTIVE_LOW>; linux,code = <4>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca0 5 GPIO_ACTIVE_LOW>; linux,code = <5>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca0 6 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca0 7 GPIO_ACTIVE_LOW>; linux,code = <7>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index 7ae4ea0d2931..0cb7b20ff3ab 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -58,13 +58,13 @@ gpio-keys { compatible = "gpio-keys"; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 7)>; }; - pcie-e2b-present{ + event-pcie-e2b-present{ label = "pcie-e2b-present"; gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(E, 7)>; diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts index 61bc74b423cf..a5e64ccc2b3a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts +++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts @@ -24,17 +24,17 @@ leds { compatible = "gpio-leds"; postcode0 { - label="BMC_UP"; + label = "BMC_UP"; gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>; default-state = "on"; }; postcode1 { - label="BMC_HB"; + label = "BMC_HB"; gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; postcode2 { - label="FAULT"; + label = "FAULT"; gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; }; // postcode3-7 are GPIOH3-H7 diff --git a/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts b/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts new file mode 100644 index 000000000000..259ef3f54c5c --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + +/dts-v1/; + +#include "aspeed-g6.dtsi" + +/ { + model = "Qualcomm DC-SCM V1 BMC"; + compatible = "qcom,dc-scm-v1-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&mdio3 { + status = "okay"; + + ethphy3: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mac2 { + status = "okay"; + + /* Bootloader sets up the MAC to insert delay */ + phy-mode = "rgmii"; + phy-handle = <ðphy3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; +}; + +&mac3 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + + use-ncsi; +}; + +&rtc { + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <133000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <133000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <133000000>; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "BMC_FLASH_MUX_SEL","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","", + /*O0-O7*/ "JTAG_MUX_A","JTAG_MUX_B","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","SCMFPGA_SPARE_GPIO1_3V3", + "SCMFPGA_SPARE_GPIO2_3V3","SCMFPGA_SPARE_GPIO3_3V3", + "SCMFPGA_SPARE_GPIO4_3V3","SCMFPGA_SPARE_GPIO5_3V3", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&gpio1 { + gpio-line-names = + /*A0-A7*/ "GPI_1_BMC_1V8","","","","","", + "SCMFPGA_SPARE_GPIO1_1V8","SCMFPGA_SPARE_GPIO2_1V8", + /*B0-B7*/ "SCMFPGA_SPARE_GPIO3_1V8","SCMFPGA_SPARE_GPIO4_1V8", + "SCMFPGA_SPARE_GPIO5_1V8","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","BMC_SPI1_RST_N","BIOS_FLASH_MUX_SEL","", + "","TPM2_PIRQ_N","TPM2_RST_N","", + /*E0-E7*/ "","","","","","","",""; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts new file mode 100644 index 000000000000..46cbba6305b8 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2022 Quanta Corp. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/i2c/i2c.h> + +/ { + model = "Quanta S6Q BMC"; + compatible = "quanta,s6q-bmc", "aspeed,ast2600"; + + aliases { + // bus 0 + i2c20 = &SMB_HOST_DB2000_3V3AUX_SCL; + i2c21 = &U12_PCA9546_CH1; + i2c22 = &SMB_HOST_DB800_B_SCL; + i2c23 = &SMB_HOST_DB800_C_SCL; + + // bus 1 + i2c24 = &SMB_M2_P0_1V8AUX_SCL; + i2c25 = &SMB_M2_P1_1V8AUX_SCL; + i2c26 = &SMB_CPU_PIROM_3V3AUX_SCL; + i2c27 = &SMB_TEMP_3V3AUX_SCL; + i2c28 = &SMB_IPMB_3V3AUX_SSDSB_SCL; + i2c29 = &SMB_IPMB_3V3AUX_SCL; + i2c31 = &SMB_FB_SCL; + + // bus 1 - Fan board + i2c32 = &SMB_IOEXP_SCL; + i2c33 = &SMB_PROGRAM_SCL; + i2c34 = &SMB_FB_SCL_CH2; + i2c35 = &SMB_FAN_SENSE_SCL; + + // bus 6 + i2c36 = &U197_PCA9546_CH0; + i2c37 = &U197_PCA9546_CH1; + i2c38 = &U197_PCA9546_CH2; + i2c39 = &U197_PCA9546_CH3; + + //bus 7 + i2c40 = &SMB_OCP_SFF_3V3AUX_SCL; //OCP1 + i2c41 = &SMB_OCP_LFF_3V3AUX_SCL; //OCP2 + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + leds { + compatible = "gpio-leds"; + + BMC_HEARTBEAT_N { + label = "BMC_HEARTBEAT_N"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + BMC_LED_STATUS_AMBER_N { + label = "BMC_LED_STATUS_AMBER_N"; + gpios = <&gpio0 ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + FM_ID_LED_N { + label = "FM_ID_LED_N"; + gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0 - A7*/ "", "", "", "", "", "", "", "", + /*B0 - B7*/ "", "", "", "", "", "", "", "", + /*C0 - C7*/ "", "", "", "", "", "", "", "", + /*D0 - D7*/ "", "", "", "", "", "", "", "", + /*E0 - E7*/ "", "", "", "", "", "", "", "", + /*F0 - F7*/ "PLTRST_N", "", "PWR_DEBUG_N", "", "", "", "", "", + /*G0 - G7*/ "", "", "", "", "", "", "", "", + /*H0 - H7*/ "", "", "", "", "", "", "", "", + /*I0 - I7*/ "", "", "", "", "", "", "", "", + /*J0 - J7*/ "", "", "", "", "", "", "", "", + /*K0 - K7*/ "", "", "", "", "", "", "", "", + /*L0 - L7*/ "", "", "", "", "PREQ_N", "TCK_MUX_SEL", "", "", + /*M0 - M7*/ "", "", "", "PWRGD_SYS_PWROK", "", "PRDY_N", "", "", + /*N0 - N7*/ "", "", "", "", "", "", "", "", + /*O0 - O7*/ "", "", "", "", "", "", "", "", + /*P0 - P7*/ "SYS_BMC_PWRBTN_R_N", "SYS_PWRBTN_N", "FM_MB_RST_BTN", "RST_BMC_RSTBTN_OUT_N", "", "", "", "", + /*Q0 - Q7*/ "", "", "", "", "", "", "", "", + /*R0 - R7*/ "", "", "", "", "", "", "", "", + /*S0 - S7*/ "", "", "", "FP_ID_BTN_SCM_N", "", "", "", "", + /*T0 - T7*/ "", "", "", "", "", "", "", "", + /*U0 - U7*/ "", "", "", "", "", "", "", "", + /*V0 - V7*/ "", "", "", "", "", "SMI", "", "", + /*W0 - W7*/ "", "", "", "", "", "", "", "", + /*X0 - X7*/ "", "", "", "", "", "", "", "", + /*Y0 - Y7*/ "", "", "", "", "", "", "", "", + /*Z0 - Z7*/ "FM_BMC_READY_N", "", "", "", "", "", "", "", + /*AA0 - AA7*/ "", "", "", "", "", "", "", "", + /*AB0 - AB7*/ "", "", "", "", "", "", "", "", + /*AC0 - AC7*/ "", "", "", "", "", "", "", ""; +}; + +&sgpiom0 { + status = "okay"; + ngpios = <128>; + bus-frequency = <48000>; + gpio-line-names = + /* SGPIO input lines */ + /*IOA0-IOA7*/ "","", "SIO_POWER_GOOD","OA1", "XDP_PRST_N","", "","", "FM_SLPS3_PLD_N","", "FM_SLPS4_PLD_N","", "FM_BIOS_POST_CMPLT_BMC_N","", "FM_ADR_TRIGGER_N","OA7", + /*IOB0-IOB7*/ "FM_ADR_COMPLETE","", "FM_PMBUS_ALERT_B_EN","", "PSU0_PRESENT_N","", "PSU1_PRESENT_N","", "PSU0_VIN_BUF_GOOD","", "PSU01_VIN_BUF_GOOD","", "PWRGD_PS0_PWROK_R","", "PWRGD_PS1_PWROK_R","", + /*IOC0-IOC7*/ "PWRGD_PS_PWROK_PLD_R","", "CHASSIS_INTRUSION","", "BMC_MFG_MODE","", "FM_BMC_EN_DET_R","", "FM_ME_BT_DONE","", "CPU1_PRESENCE","", "CPU2_PRESENCE","", "IRQ_PSYS_CRIT_N","", + /*IOD0-IOD7*/ "","", "CPU1_THERMTRIP","", "CPU2_THERMTRIP","", "CPU1_MEM_THERM_EVENT","", "CPU2_MEM_THERM_EVENT","", "CPU1_VRHOT","", "CPU2_VRHOT","", "","", + /*IOE0-IOE7*/ "","", "CPU1_MEM_VRHOT","", "CPU2_MEM_VRHOT","", "","", "PCH_BMC_THERMTRIP","", "","", "","", "","", + /*IOF0-IOF7*/ "CPU_ERR0","", "CPU_ERR1","", "CPU_ERR2","", "","", "","", "CPU_CATERR","", "","", "","", + /*IOG0-IOG7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOH0-IOH7*/ "","", "FP_ID_BTN_R1_N","", "FP_RST_BTN_N","", "","", "","", "FP_PWR_BTN_PLD_N_R","", "","", "","", + /*IOI0-IOI7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOJ0-IOJ7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOK0-IOK7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOL0-IOL7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOM0-IOM7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*ION0-ION7*/ "","BMC_SW_HEARTBEAT_N_R", "","FP_LED_FAULT_N", "","FP_ID_LED_N", "","FM_BMC_RSTBTN_OUT_N", "","FM_THERMTRIP_DLY_LVC1_R_N", "","", "","RST_PCA9548_SENSOR_PLD_N", "","USB_OC1_REAR_N", + /*IOO0-IOO7*/ "","IRQ_TPM_SPI_N", "","", "","IRQ_PCH_SCI_WHEA_R_N", "","IRQ_BMC_PCH_NMI_R", "","H_CPU_NMI_LVC1_R_N", "","", "","", "","FM_JTAG_BMC_PLD_MUX_SEL", + /*IOP0-IOP7*/ "IP0","OP0", "","", "","", "","", "","", "","", "","", "IP7","OP7"; +}; + +&adc0 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&mdio2 { + status = "okay"; + + ethphy2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mac2 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; +}; + +&mac3 { + status = "okay"; + + phy-mode = "rmii"; + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default + &pinctrl_spi2cs2_default>; + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "spi2:0"; + spi-max-frequency = <50000000>; + }; +}; + +&kcs1 { + status = "okay"; + aspeed,lpc-io-reg = <0xCA0>; +}; + +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0xCA8>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xCA2>; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + non-removable; + bus-width = <4>; + max-frequency = <100000000>; +}; + +&vhub { + status = "okay"; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + U34_PWR_ADC@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + U35_PWR_ADC@4b { + compatible = "ti,ads7830"; + reg = <0x4b>; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + SMB_HOST_DB2000_3V3AUX_SCL: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + U12_PCA9546_CH1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + SMB_HOST_DB800_B_SCL: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + SMB_HOST_DB800_C_SCL: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + i2c-switch@59 { + compatible = "nxp,pca9848"; + reg = <0x59>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + SMB_M2_P0_1V8AUX_SCL: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + SMB_M2_P1_1V8AUX_SCL: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + SMB_CPU_PIROM_3V3AUX_SCL: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + SMB_TEMP_3V3AUX_SCL: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + U163_tmp75@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + U114_tmp75@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + }; + + SMB_IPMB_3V3AUX_SSDSB_SCL: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + U4_tmp75@4c { + compatible = "ti,tmp75"; + reg = <0x4c>; + }; + U73_tmp75@4d { + compatible = "ti,tmp75"; + reg = <0x4d>; + }; + }; + + SMB_IPMB_3V3AUX_SCL: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + U190_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; + }; + + SMB_FB_SCL: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + i2c-switch@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + SMB_IOEXP_SCL: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + SMB_PROGRAM_SCL: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + SMB_FB_SCL_CH2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + SMB_FAN_SENSE_SCL: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + Current_Meter_U2@45 { + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <1000>; /* = 1 mOhm */ + }; + + Current_Meter_U3@44 { + compatible = "ti,ina219"; + reg = <0x44>; + shunt-resistor = <1000>; /* = 1 mOhm */ + }; + + TEMP_sensor_U2@4b { + compatible = "ti,tmp75"; + reg = <0x4b>; + }; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + bus-frequency = <400000>; + + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c3 { + status = "okay"; + + /* MB FRU (U173) @ 0xA2 */ + mb_fru: mb_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; + + /* FP_U1 Inlet */ + FP_U1_tmp75@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + }; + + FP_U4_fru@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + U197_PCA9546_CH0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + U197_PCA9546_CH1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + cpu0_pvccin@60 { + compatible = "isil,raa229004"; + reg = <0x60>; + }; + + cpu0_pvccinfaon@61 { + compatible = "isil,isl69260"; + reg = <0x61>; + }; + + cpu0_pvccd_hv@63 { + compatible = "isil,isl69260"; + reg = <0x63>; + }; + }; + + U197_PCA9546_CH2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + cpu1_pvccin@72 { + compatible = "isil,raa229004"; + reg = <0x72>; + }; + + cpu1_pvccinfaon@74 { + compatible = "isil,isl69260"; + reg = <0x74>; + }; + + cpu1_pvccd_hv@76 { + compatible = "isil,isl69260"; + reg = <0x76>; + }; + }; + + U197_PCA9546_CH3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c7 { + status = "okay"; + + i2c-switch@75 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + SMB_OCP_SFF_3V3AUX_SCL: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + SMB_OCP_LFF_3V3AUX_SCL: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; + + /* SCM FRU (U19) @ 0xA2 */ + scm_fru: scm_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; + + scm_tmp75_u4@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + }; +}; + +&i2c15 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index f14dace34c5a..530491ae5eb2 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -54,8 +54,7 @@ ranges; fmc: spi@1e620000 { - reg = < 0x1e620000 0x94 - 0x20000000 0x10000000 >; + reg = <0x1e620000 0x94>, <0x20000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2400-fmc"; @@ -65,34 +64,42 @@ flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; spi-max-frequency = <50000000>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@3 { reg = < 3 >; compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@4 { reg = < 4 >; compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; status = "disabled"; }; }; spi: spi@1e630000 { - reg = < 0x1e630000 0x18 - 0x30000000 0x10000000 >; + reg = <0x1e630000 0x18>, <0x30000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2400-spi"; @@ -102,6 +109,7 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; @@ -392,6 +400,17 @@ }; }; + peci0: peci-controller@1e78b000 { + compatible = "aspeed,ast2400-peci"; + reg = <0x1e78b000 0x60>; + interrupts = <15>; + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; + resets = <&syscon ASPEED_RESET_PECI>; + cmd-timeout-ms = <1000>; + clock-frequency = <1000000>; + status = "disabled"; + }; + uart2: serial@1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x20>; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 7495f93c5069..04f98d1dbb97 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -55,8 +55,7 @@ ranges; fmc: spi@1e620000 { - reg = < 0x1e620000 0xc4 - 0x20000000 0x10000000 >; + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-fmc"; @@ -67,25 +66,27 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; spi1: spi@1e630000 { - reg = < 0x1e630000 0xc4 - 0x30000000 0x08000000 >; + reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-spi"; @@ -95,19 +96,20 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; spi2: spi@1e631000 { - reg = < 0x1e631000 0xc4 - 0x38000000 0x08000000 >; + reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-spi"; @@ -117,12 +119,14 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; @@ -258,6 +262,14 @@ quality = <100>; }; + hace: crypto@1e6e3000 { + compatible = "aspeed,ast2500-hace"; + reg = <0x1e6e3000 0x100>; + interrupts = <4>; + clocks = <&syscon ASPEED_CLK_GATE_YCLK>; + resets = <&syscon ASPEED_RESET_HACE>; + }; + gfx: display@1e6e6000 { compatible = "aspeed,ast2500-gfx", "syscon"; reg = <0x1e6e6000 0x1000>; @@ -516,6 +528,17 @@ }; }; + peci0: peci-controller@1e78b000 { + compatible = "aspeed,ast2500-peci"; + reg = <0x1e78b000 0x60>; + interrupts = <15>; + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; + resets = <&syscon ASPEED_RESET_PECI>; + cmd-timeout-ms = <1000>; + clock-frequency = <1000000>; + status = "disabled"; + }; + uart2: serial@1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x20>; diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 6dde51c2aed3..7cd4f075e325 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -117,9 +117,9 @@ groups = "FWSPID"; }; - pinctrl_fwqspid_default: fwqspid_default { - function = "FWQSPID"; - groups = "FWQSPID"; + pinctrl_fwqspi_default: fwqspi_default { + function = "FWQSPI"; + groups = "FWQSPI"; }; pinctrl_fwspiwp_default: fwspiwp_default { @@ -653,12 +653,12 @@ }; pinctrl_qspi1_default: qspi1_default { - function = "QSPI1"; + function = "SPI1"; groups = "QSPI1"; }; pinctrl_qspi2_default: qspi2_default { - function = "QSPI2"; + function = "SPI2"; groups = "QSPI2"; }; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index c32e87fad4dc..ebbcfe445d9c 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -95,8 +95,7 @@ }; fmc: spi@1e620000 { - reg = < 0x1e620000 0xc4 - 0x20000000 0x10000000 >; + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2600-fmc"; @@ -107,25 +106,27 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; spi1: spi@1e630000 { - reg = < 0x1e630000 0xc4 - 0x30000000 0x10000000 >; + reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2600-spi"; @@ -135,19 +136,20 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; spi2: spi@1e631000 { - reg = < 0x1e631000 0xc4 - 0x50000000 0x10000000 >; + reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2600-spi"; @@ -157,18 +159,21 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; @@ -181,6 +186,7 @@ status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mdio1_default>; + resets = <&syscon ASPEED_RESET_MII>; }; mdio1: mdio@1e650008 { @@ -191,6 +197,7 @@ status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mdio2_default>; + resets = <&syscon ASPEED_RESET_MII>; }; mdio2: mdio@1e650010 { @@ -201,6 +208,7 @@ status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mdio3_default>; + resets = <&syscon ASPEED_RESET_MII>; }; mdio3: mdio@1e650018 { @@ -211,6 +219,7 @@ status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mdio4_default>; + resets = <&syscon ASPEED_RESET_MII>; }; mac0: ftgmac@1e660000 { @@ -298,12 +307,30 @@ status = "disabled"; }; + udc: usb@1e6a2000 { + compatible = "aspeed,ast2600-udc"; + reg = <0x1e6a2000 0x300>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2bd_default>; + status = "disabled"; + }; + apb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + hace: crypto@1e6d0000 { + compatible = "aspeed,ast2600-hace"; + reg = <0x1e6d0000 0x200>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_YCLK>; + resets = <&syscon ASPEED_RESET_HACE>; + }; + syscon: syscon@1e6e2000 { compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1000>; @@ -351,6 +378,17 @@ quality = <100>; }; + gfx: display@1e6e6000 { + compatible = "aspeed,ast2600-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_GRAPHICS>; + syscon = <&syscon>; + status = "disabled"; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + }; + xdma: xdma@1e6e7000 { compatible = "aspeed,ast2600-xdma"; reg = <0x1e6e7000 0x100>; @@ -389,6 +427,16 @@ reg = <0x1e6f2000 0x1000>; }; + video: video@1e700000 { + compatible = "aspeed,ast2600-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + gpio0: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; @@ -512,6 +560,17 @@ status = "disabled"; }; + peci0: peci-controller@1e78b000 { + compatible = "aspeed,ast2600-peci"; + reg = <0x1e78b000 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>; + resets = <&syscon ASPEED_RESET_PECI>; + cmd-timeout-ms = <1000>; + clock-frequency = <1000000>; + status = "disabled"; + }; + lpc: lpc@1e789000 { compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; reg = <0x1e789000 0x1000>; @@ -705,6 +764,62 @@ status = "disabled"; }; + uart6: serial@1e790000 { + compatible = "ns16550a"; + reg = <0x1e790000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART6CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6_default>; + + status = "disabled"; + }; + + uart7: serial@1e790100 { + compatible = "ns16550a"; + reg = <0x1e790100 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART7CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7_default>; + + status = "disabled"; + }; + + uart8: serial@1e790200 { + compatible = "ns16550a"; + reg = <0x1e790200 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART8CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8_default>; + + status = "disabled"; + }; + + uart9: serial@1e790300 { + compatible = "ns16550a"; + reg = <0x1e790300 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART9CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart9_default>; + + status = "disabled"; + }; + i2c: bus@1e78a000 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi index c1c8650dafce..3542ad8a243e 100644 --- a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi +++ b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi @@ -44,7 +44,7 @@ status = "okay"; /* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */ - spi-flash@0 { + flash@0 { compatible = "mxicy,mx25u4035", "jedec,spi-nor"; spi-max-frequency = <33000000>; reg = <0>; diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts index 7edf057047f8..9dfd5de808d1 100644 --- a/arch/arm/boot/dts/at91-foxg20.dts +++ b/arch/arm/boot/dts/at91-foxg20.dts @@ -155,10 +155,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - btn { + button { label = "Button"; gpios = <&pioC 4 GPIO_ACTIVE_LOW>; linux,code = <0x103>; diff --git a/arch/arm/boot/dts/at91-gatwick.dts b/arch/arm/boot/dts/at91-gatwick.dts index 5a81cab5fc3a..2c718cf84d7b 100644 --- a/arch/arm/boot/dts/at91-gatwick.dts +++ b/arch/arm/boot/dts/at91-gatwick.dts @@ -13,7 +13,7 @@ model = "Laird Workgroup Bridge 50N - Project Gatwick"; compatible = "laird,gatwick", "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; autorepeat; diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts index 3b8812fcd854..307663b4eec2 100644 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ b/arch/arm/boot/dts/at91-kizbox.dts @@ -28,19 +28,17 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - reset { + button-reset { label = "PB_RST"; gpios = <&pioB 30 GPIO_ACTIVE_HIGH>; linux,code = <0x100>; wakeup-source; }; - user { + button-user { label = "PB_USER"; gpios = <&pioB 31 GPIO_ACTIVE_HIGH>; linux,code = <0x101>; diff --git a/arch/arm/boot/dts/at91-kizbox2-common.dtsi b/arch/arm/boot/dts/at91-kizbox2-common.dtsi index c08834ddf07b..e5e21dff882f 100644 --- a/arch/arm/boot/dts/at91-kizbox2-common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox2-common.dtsi @@ -31,26 +31,24 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - prog { + button-prog { label = "PB_PROG"; gpios = <&pioE 27 GPIO_ACTIVE_LOW>; linux,code = <0x102>; wakeup-source; }; - reset { + button-reset { label = "PB_RST"; gpios = <&pioE 29 GPIO_ACTIVE_LOW>; linux,code = <0x100>; wakeup-source; }; - user { + button-user { label = "PB_USER"; gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; linux,code = <0x101>; diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/at91-kizbox3-hs.dts index 2799b2a1f4d2..7075df6549e9 100644 --- a/arch/arm/boot/dts/at91-kizbox3-hs.dts +++ b/arch/arm/boot/dts/at91-kizbox3-hs.dts @@ -55,7 +55,7 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default" , "default", "default", "default", "default" ; @@ -68,35 +68,35 @@ &pinctrl_pio_zbe_rst>; pinctrl-4 = <&pinctrl_pio_input>; - SW1 { + switch-1 { label = "SW1"; gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; linux,code = <0x101>; wakeup-source; }; - SW2 { + switch-2 { label = "SW2"; gpios = <&pioA PIN_PA18 GPIO_ACTIVE_LOW>; linux,code = <0x102>; wakeup-source; }; - SW3 { + switch-3 { label = "SW3"; gpios = <&pioA PIN_PA22 GPIO_ACTIVE_LOW>; linux,code = <0x103>; wakeup-source; }; - SW7 { + switch-7 { label = "SW7"; gpios = <&pioA PIN_PA26 GPIO_ACTIVE_LOW>; linux,code = <0x107>; wakeup-source; }; - SW8 { + switch-8 { label = "SW8"; gpios = <&pioA PIN_PA24 GPIO_ACTIVE_LOW>; linux,code = <0x108>; @@ -186,7 +186,7 @@ &pioA { pinctrl_key_gpio_default: key_gpio_default { - pinmux= <PIN_PA22__GPIO>, + pinmux = <PIN_PA22__GPIO>, <PIN_PA24__GPIO>, <PIN_PA26__GPIO>, <PIN_PA29__GPIO>, diff --git a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi index 9c622892c692..42640fe6b6d0 100644 --- a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi +++ b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi @@ -36,17 +36,15 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - prog { + key-prog { label = "PB_PROG"; gpios = <&pioC 17 GPIO_ACTIVE_LOW>; linux,code = <0x102>; wakeup-source; }; - reset { + key-reset { label = "PB_RST"; gpios = <&pioC 16 GPIO_ACTIVE_LOW>; linux,code = <0x100>; diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts index 4f123477e631..f71377c9b757 100644 --- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts +++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts @@ -18,7 +18,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "Wakeup"; linux,code = <10>; wakeup-source; diff --git a/arch/arm/boot/dts/at91-q5xr5.dts b/arch/arm/boot/dts/at91-q5xr5.dts index 47a00062f01f..9cf60b6f695c 100644 --- a/arch/arm/boot/dts/at91-q5xr5.dts +++ b/arch/arm/boot/dts/at91-q5xr5.dts @@ -125,7 +125,7 @@ cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index 969d990767fc..9d26f9996348 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -198,10 +198,8 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - user_pb { + button-user { label = "user_pb"; gpios = <&pioB 10 GPIO_ACTIVE_LOW>; linux,code = <28>; diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts index 1e2a28c2f365..2fb51b9aca2a 100644 --- a/arch/arm/boot/dts/at91-sam9_l9260.dts +++ b/arch/arm/boot/dts/at91-sam9_l9260.dts @@ -101,7 +101,7 @@ nand0: nand@40000000 { nand-bus-width = <8>; nand-ecc-mode = "soft"; - nand-on-flash-bbt = <1>; + nand-on-flash-bbt; status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index b1068cca4228..4ba52ba11dc6 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -34,58 +34,15 @@ }; }; - regulators: regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_1v8: fixed-regulator-vdd_1v8@0 { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - status = "okay"; - }; - - vdd_1v5: fixed-regulator-vdd_1v5@1 { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - status = "okay"; - }; - - vdd1_3v3: fixed-regulator-vdd1_3v3@2 { - compatible = "regulator-fixed"; - regulator-name = "VDD1_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - status = "okay"; - }; - - vdd2_3v3: regulator-fixed-vdd2_3v3@3 { - compatible = "regulator-fixed"; - regulator-name = "VDD2_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - status = "okay"; - }; - }; - - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - status = "okay"; - sw1 { + button-1 { label = "SW1"; gpios = <&pioD 18 GPIO_ACTIVE_LOW>; - linux,code=<KEY_PROG1>; + linux,code = <KEY_PROG1>; wakeup-source; }; }; @@ -112,6 +69,42 @@ linux,default-trigger = "heartbeat"; }; }; + + vdd_1v8: fixed-regulator-vdd_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + status = "okay"; + }; + + vdd_1v15: fixed-regulator-vdd_1v15 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + status = "okay"; + }; + + vdd1_3v3: fixed-regulator-vdd1_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD1_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + status = "okay"; + }; + + vdd2_3v3: regulator-fixed-vdd2_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + status = "okay"; + }; }; &adc { @@ -233,10 +226,9 @@ status = "okay"; eeprom@53 { - compatible = "atmel,24c32"; + compatible = "atmel,24c02"; reg = <0x53>; pagesize = <16>; - size = <128>; status = "okay"; }; }; @@ -266,8 +258,9 @@ status = "okay"; uart1: serial@200 { - compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index a4623cc67cc1..8aa9e8dea337 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -15,7 +15,7 @@ compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; aliases { - i2c0 = &i2c0; + i2c0 = &i2c0; }; clocks { @@ -83,6 +83,8 @@ macb0: ethernet@f8008000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_default>; + #address-cells = <1>; + #size-cells = <0>; phy-mode = "rmii"; ethernet-phy@7 { diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 08f0d4b995ff..0dc6ca377b0c 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -21,8 +21,8 @@ serial0 = &uart1; /* DBGU */ serial1 = &uart4; /* mikro BUS 1 */ serial2 = &uart2; /* mikro BUS 2 */ - i2c1 = &i2c1; - i2c2 = &i2c3; + i2c1 = &i2c1; + i2c2 = &i2c3; }; chosen { @@ -478,13 +478,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - pb4 { + button { label = "USER"; gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi index 21c86171e462..83bcf9fe0152 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -76,8 +76,8 @@ regulators { vdd_3v3: VDD_IO { regulator-name = "VDD_IO"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -95,8 +95,8 @@ vddio_ddr: VDD_DDR { regulator-name = "VDD_DDR"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -118,8 +118,8 @@ vdd_core: VDD_CORE { regulator-name = "VDD_CORE"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -160,8 +160,8 @@ LDO1 { regulator-name = "LDO1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; regulator-state-standby { @@ -175,9 +175,8 @@ LDO2 { regulator-name = "LDO2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; regulator-state-standby { regulator-on-in-suspend; @@ -194,6 +193,8 @@ &macb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_default>; + #address-cells = <1>; + #size-cells = <0>; phy-mode = "rmii"; ethernet-phy@0 { @@ -214,7 +215,7 @@ pinctrl-0 = <&pinctrl_qspi1_default>; status = "disabled"; - qspi1_flash: spi_flash@0 { + qspi1_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts index c145c4e5ef58..b665ddc6b0de 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts @@ -19,21 +19,20 @@ serial1 = &uart6; /* BT */ serial2 = &uart5; /* mikro BUS 2 */ serial3 = &uart3; /* mikro BUS 1 */ - i2c1 = &i2c1; + i2c1 = &i2c1; }; chosen { stdout-path = "serial0:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - status = "okay"; - sw4 { + button-1 { label = "USER BUTTON"; gpios = <&pioA PIN_PB2 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; @@ -191,7 +190,7 @@ &qspi1 { status = "okay"; - qspi1_flash: spi_flash@0 { + qspi1_flash: flash@0 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index 806eb1d911d7..dd1dec9d4e07 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -24,8 +24,8 @@ serial1 = &uart1; /* mikro BUS 3 */ serial3 = &uart3; /* mikro BUS 2 */ serial5 = &uart7; /* flx2 */ - i2c0 = &i2c0; - i2c1 = &i2c1; + i2c0 = &i2c0; + i2c1 = &i2c1; }; chosen { @@ -42,14 +42,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - status = "okay"; - sw4 { + button-1 { label = "USER_PB1"; gpios = <&pioA PIN_PD0 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; @@ -197,8 +196,8 @@ regulators { vdd_io_reg: VDD_IO { regulator-name = "VDD_IO"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -216,8 +215,8 @@ VDD_DDR { regulator-name = "VDD_DDR"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -235,8 +234,8 @@ VDD_CORE { regulator-name = "VDD_CORE"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -258,7 +257,6 @@ regulator-max-microvolt = <1850000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; - regulator-always-on; regulator-state-standby { regulator-on-in-suspend; @@ -273,8 +271,8 @@ LDO1 { regulator-name = "LDO1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; regulator-always-on; regulator-state-standby { @@ -288,8 +286,8 @@ LDO2 { regulator-name = "LDO2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; regulator-state-standby { @@ -329,21 +327,21 @@ status = "okay"; eeprom@50 { - compatible = "atmel,24c32"; + compatible = "atmel,24c02"; reg = <0x50>; pagesize = <16>; status = "okay"; }; eeprom@52 { - compatible = "atmel,24c32"; + compatible = "atmel,24c02"; reg = <0x52>; pagesize = <16>; status = "disabled"; }; eeprom@53 { - compatible = "atmel,24c32"; + compatible = "atmel,24c02"; reg = <0x53>; pagesize = <16>; status = "disabled"; diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index 8ed58af01391..76a711b167b0 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -20,9 +20,9 @@ aliases { serial0 = &uart0; /* DBGU */ - i2c0 = &i2c0; /* mikroBUS 1 */ - i2c1 = &i2c1; /* XPRO EXT1 */ - i2c2 = &i2c2; + i2c0 = &i2c0; /* mikroBUS 1 */ + i2c1 = &i2c1; /* XPRO EXT1 */ + i2c2 = &i2c2; }; chosen { @@ -139,6 +139,8 @@ macb0: ethernet@f8008000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; + #address-cells = <1>; + #size-cells = <0>; phy-mode = "rmii"; status = "okay"; @@ -394,13 +396,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - bp1 { + button-1 { label = "PB_USER"; gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 9bf2ec0ba3e2..85949c24b687 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -137,7 +137,7 @@ pinctrl-0 = <&pinctrl_spi0_default>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; reg = <0>; spi-max-frequency = <50000000>; @@ -147,6 +147,8 @@ macb0: ethernet@f8008000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; + #address-cells = <1>; + #size-cells = <0>; phy-mode = "rmii"; status = "okay"; @@ -205,10 +207,10 @@ regulator-state-mem { regulator-on-in-suspend; - regulator-suspend-min-microvolt=<1400000>; - regulator-suspend-max-microvolt=<1400000>; + regulator-suspend-min-microvolt = <1400000>; + regulator-suspend-max-microvolt = <1400000>; regulator-changeable-in-suspend; - regulator-mode=<ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-mode = <ACT8945A_REGULATOR_MODE_LOWPOWER>; }; }; @@ -703,13 +705,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - bp1 { + button { label = "PB_USER"; gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-sama5d3_eds.dts b/arch/arm/boot/dts/at91-sama5d3_eds.dts new file mode 100644 index 000000000000..c287b03d768b --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d3_eds.dts @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet + * Development System board. + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Jerry Ray <jerry.ray@microchip.com> + */ +/dts-v1/; +#include "sama5d36.dtsi" + +/ { + model = "SAMA5D3 Ethernet Development System"; + compatible = "microchip,sama5d3-eds", "atmel,sama5d36", + "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + button-3 { + label = "PB_USER"; + gpios = <&pioE 29 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + wakeup-source; + }; + }; + + memory@20000000 { + reg = <0x20000000 0x10000000>; + }; + + vcc_3v3_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_2v5_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "VCC_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + vin-supply = <&vcc_3v3_reg>; + }; + + vcc_1v8_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vcc_3v3_reg>; + }; + + vcc_1v2_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_mmc0_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "mmc0-card-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + }; +}; + +&can0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; +}; + +&i2c0 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&pinctrl_i2c2_pu>; + status = "okay"; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&mmc0 { + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + vmmc-supply = <&vcc_mmc0_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + board { + pinctrl_i2c0_pu: i2c0-pu { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_i2c2_pu: i2c2-pu { + atmel,pins = + <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_key_gpio: key-gpio-0 { + atmel,pins = + <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + + pinctrl_mmc0_cd: mmc0-cd { + atmel,pins = + <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + + /* Reserved for reset signal to the RGMII connector. */ + pinctrl_rgmii_rstn: rgmii-rstn { + atmel,pins = + <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + + /* Reserved for an interrupt line from the RMII and RGMII connectors. */ + pinctrl_spi_irqn: spi-irqn { + atmel,pins = + <AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + + pinctrl_spi0_cs: spi0-cs-default { + atmel,pins = + <AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + + pinctrl_spi1_cs: spi1-cs-default { + atmel,pins = <AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOC 28 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + + pinctrl_usba_vbus: usba-vbus { + atmel,pins = + <AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + + pinctrl_usb_default: usb-default { + atmel,pins = + <AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOE 4 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + + /* Reserved for VBUS fault interrupt. */ + pinctrl_vbusfault_irqn: vbusfault-irqn { + atmel,pins = + <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + + pinctrl_vcc_mmc0_reg_gpio: vcc-mmc0-reg-gpio-default { + atmel,pins = <AT91_PIOE 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&spi0 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi0_cs>; + cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi1_cs>; + cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioC 28 0>; + status = "okay"; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&usb0 { /* USB Device port with VBUS detection. */ + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { /* 3-port Host. First port is unused. */ + atmel,vbus-gpio = <0 + &pioE 3 GPIO_ACTIVE_HIGH + &pioE 4 GPIO_ACTIVE_HIGH + >; + num-ports = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts index 443e8b022897..14af1fd6d247 100644 --- a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts +++ b/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts @@ -120,26 +120,31 @@ port@0 { reg = <0>; label = "lan1"; + phy-mode = "internal"; }; port@1 { reg = <1>; label = "lan2"; + phy-mode = "internal"; }; port@2 { reg = <2>; label = "lan3"; + phy-mode = "internal"; }; port@3 { reg = <3>; label = "lan4"; + phy-mode = "internal"; }; port@4 { reg = <4>; label = "lan5"; + phy-mode = "internal"; }; port@5 { diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index d72c042f2850..1f42a6a981bf 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -57,8 +57,8 @@ }; spi0: spi@f0004000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_cs>; + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi0_cs>; cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; status = "okay"; }; @@ -171,8 +171,8 @@ }; spi1: spi@f8008000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_cs>; + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi1_cs>; cs-gpios = <&pioC 25 0>; status = "okay"; }; @@ -372,13 +372,13 @@ regulator-always-on; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio>; - bp3 { + button { label = "PB_USER"; gpios = <&pioE 29 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi index 710cb72bda5a..fd1086f52b40 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi @@ -49,7 +49,7 @@ cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index d241c24f0d83..f122f302f8e0 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -81,8 +81,8 @@ }; spi1: spi@fc018000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_cs>; + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi1_cs>; cs-gpios = <&pioB 21 0>; status = "okay"; }; @@ -140,7 +140,7 @@ atmel,pins = <AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; }; - pinctrl_spi0_cs: spi0_cs_default { + pinctrl_spi1_cs: spi1_cs_default { atmel,pins = <AT91_PIOB 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; }; @@ -242,13 +242,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio>; - pb_user1 { + button { label = "pb_user1"; gpios = <&pioE 8 GPIO_ACTIVE_HIGH>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index fe432b6b7e95..fce4e93c6bee 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -65,7 +65,7 @@ spi0: spi@f8010000 { cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; reg = <0>; @@ -269,13 +269,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio>; - pb_user1 { + button { label = "pb_user1"; gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; linux,code = <0x100>; diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index ccf9e224da78..3b25c67795dd 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -14,6 +14,7 @@ #include <dt-bindings/mfd/atmel-flexcom.h> #include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/sound/microchip,pdmc.h> / { model = "Microchip SAMA7G5-EK"; @@ -44,13 +45,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - bp1 { + button { label = "PB_USER"; gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; @@ -131,6 +132,18 @@ status = "okay"; }; +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; +}; + &cpu0 { cpu-supply = <&vddcpu>; }; @@ -231,14 +244,15 @@ regulators { vdd_3v3: VDD_IO { regulator-name = "VDD_IO"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; regulator-state-standby { regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; regulator-mode = <4>; }; @@ -250,8 +264,8 @@ vddioddr: VDD_DDR { regulator-name = "VDD_DDR"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1450000>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -271,14 +285,15 @@ vddcore: VDD_CORE { regulator-name = "VDD_CORE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; regulator-state-standby { regulator-on-in-suspend; + regulator-suspend-voltage = <1150000>; regulator-mode = <4>; }; @@ -290,8 +305,8 @@ vddcpu: VDD_OTHER { regulator-name = "VDD_OTHER"; - regulator-min-microvolt = <1125000>; - regulator-max-microvolt = <1850000>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1250000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-ramp-delay = <3125>; @@ -299,6 +314,7 @@ regulator-state-standby { regulator-on-in-suspend; + regulator-suspend-voltage = <1050000>; regulator-mode = <4>; }; @@ -310,11 +326,12 @@ vldo1: LDO1 { regulator-name = "LDO1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-always-on; regulator-state-standby { + regulator-suspend-voltage = <1800000>; regulator-on-in-suspend; }; @@ -329,6 +346,7 @@ regulator-max-microvolt = <3700000>; regulator-state-standby { + regulator-suspend-voltage = <1800000>; regulator-on-in-suspend; }; @@ -439,7 +457,7 @@ &pinctrl_gmac1_mdio_default &pinctrl_gmac1_phy_irq>; phy-mode = "rmii"; - status = "okay"; + status = "okay"; /* Conflict with pdmc0. */ ethernet-phy@0 { reg = <0x0>; @@ -453,7 +471,31 @@ pinctrl-0 = <&pinctrl_i2s0_default>; }; +&pdmc0 { + #sound-dai-cells = <0>; + microchip,mic-pos = <MCHP_PDMC_DS0 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 1 */ + <MCHP_PDMC_DS1 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 2 */ + <MCHP_PDMC_DS0 MCHP_PDMC_CLK_POSITIVE>, /* MIC 3 */ + <MCHP_PDMC_DS1 MCHP_PDMC_CLK_POSITIVE>; /* MIC 4 */ + status = "disabled"; /* Conflict with gmac1. */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdmc0_default>; +}; + &pioA { + + pinctrl_can0_default: can0_default { + pinmux = <PIN_PD12__CANTX0>, + <PIN_PD13__CANRX0 >; + bias-disable; + }; + + pinctrl_can1_default: can1_default { + pinmux = <PIN_PD14__CANTX1>, + <PIN_PD15__CANRX1 >; + bias-disable; + }; + pinctrl_flx0_default: flx0_default { pinmux = <PIN_PE3__FLEXCOM0_IO0>, <PIN_PE4__FLEXCOM0_IO1>, @@ -465,7 +507,7 @@ pinctrl_flx3_default: flx3_default { pinmux = <PIN_PD16__FLEXCOM3_IO0>, <PIN_PD17__FLEXCOM3_IO1>; - bias-disable; + bias-pull-up; }; pinctrl_flx4_default: flx4_default { @@ -609,6 +651,13 @@ bias-disable; }; + pinctrl_pdmc0_default: pdmc0_default { + pinmux = <PIN_PD23__PDMC0_DS0>, + <PIN_PD24__PDMC0_DS1>, + <PIN_PD22__PDMC0_CLK>; + bias_disable; + }; + pinctrl_qspi: qspi { pinmux = <PIN_PB12__QSPI0_IO0>, <PIN_PB11__QSPI0_IO1>, @@ -625,7 +674,7 @@ <PIN_PB21__QSPI0_INT>; bias-disable; slew-rate = <0>; - atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>; + atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>; }; pinctrl_sdmmc0_default: sdmmc0_default { diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts index a51a3372afa1..ebeaa6ab500e 100644 --- a/arch/arm/boot/dts/at91-vinco.dts +++ b/arch/arm/boot/dts/at91-vinco.dts @@ -59,7 +59,7 @@ spi0: spi@f8010000 { cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "n25q32b", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/at91-wb45n.dts b/arch/arm/boot/dts/at91-wb45n.dts index 54d130c92185..ef73f727f7bd 100644 --- a/arch/arm/boot/dts/at91-wb45n.dts +++ b/arch/arm/boot/dts/at91-wb45n.dts @@ -12,13 +12,10 @@ model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - irqbtn@18 { - reg = <18>; + button { label = "IRQBTN"; linux,code = <99>; gpios = <&pioB 18 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts index 89f0f717f7ed..ec2becf6133b 100644 --- a/arch/arm/boot/dts/at91-wb50n.dts +++ b/arch/arm/boot/dts/at91-wb50n.dts @@ -13,21 +13,17 @@ model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - btn0@10 { - reg = <10>; + button-0 { label = "BTNESC"; linux,code = <1>; /* ESC button */ gpios = <&pioA 10 GPIO_ACTIVE_LOW>; wakeup-source; }; - irqbtn@31 { - reg = <31>; + button-1 { label = "IRQBTN"; linux,code = <99>; /* SysReq button */ gpios = <&pioE 31 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index d1181ead18e5..7a113325abb9 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -596,6 +597,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; @@ -607,6 +609,7 @@ usart0: serial@fffc0000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffc0000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -620,6 +623,7 @@ usart1: serial@fffc4000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffc4000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -633,6 +637,7 @@ usart2: serial@fffc8000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffc8000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -646,6 +651,7 @@ usart3: serial@fffcc000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffcc000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index e1ef4e44e663..4624a6f076f8 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -73,7 +73,7 @@ spi0: spi@fffe0000 { status = "okay"; cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <15000000>; reg = <0>; @@ -94,7 +94,7 @@ status = "okay"; }; - nor_flash@10000000 { + flash@10000000 { compatible = "cfi-flash"; reg = <0x10000000 0x800000>; linux,mtd-name = "physmap-flash.0"; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 7368347c9357..789fe356dbf6 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -123,7 +124,7 @@ clock-names = "slow_xtal", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; @@ -532,6 +533,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; @@ -543,6 +545,7 @@ usart0: serial@fffb0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb0000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -556,6 +559,7 @@ usart1: serial@fffb4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb4000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -569,6 +573,7 @@ usart2: serial@fffb8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb8000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -582,6 +587,7 @@ usart3: serial@fffd0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd0000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -595,6 +601,7 @@ uart0: serial@fffd4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd4000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -608,6 +615,7 @@ uart1: serial@fffd8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd8000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index ce96345d28a3..bb72f050a4fe 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -92,7 +92,7 @@ spi0: spi@fffc8000 { cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - mtd_dataflash@1 { + flash@1 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <50000000>; reg = <1>; @@ -144,17 +144,17 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - btn3 { + button-3 { label = "Button 3"; gpios = <&pioA 30 GPIO_ACTIVE_LOW>; linux,code = <0x103>; wakeup-source; }; - btn4 { + button-4 { label = "Button 4"; gpios = <&pioA 31 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 7adc36ca8a46..ee0bd1aceb3f 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -179,6 +180,7 @@ usart0: serial@fffb0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb0000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -192,6 +194,7 @@ usart1: serial@fffb4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb4000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -205,6 +208,7 @@ usart2: serial@fffb8000{ compatible = "atmel,at91sam9260-usart"; reg = <0xfffb8000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -301,6 +305,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; @@ -603,7 +608,7 @@ clock-names = "slow_xtal", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index beed819609e8..88869ca874d1 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts @@ -145,7 +145,7 @@ cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>; status = "okay"; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; reg = <0>; spi-max-frequency = <15000000>; @@ -178,6 +178,10 @@ status = "okay"; }; + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + }; + watchdog@fffffd40 { status = "okay"; }; @@ -207,31 +211,31 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - button_0 { + button-0 { label = "button_0"; gpios = <&pioA 27 GPIO_ACTIVE_LOW>; linux,code = <256>; wakeup-source; }; - button_1 { + button-1 { label = "button_1"; gpios = <&pioA 26 GPIO_ACTIVE_LOW>; linux,code = <257>; wakeup-source; }; - button_2 { + button-2 { label = "button_2"; gpios = <&pioA 25 GPIO_ACTIVE_LOW>; linux,code = <258>; wakeup-source; }; - button_3 { + button-3 { label = "button_3"; gpios = <&pioA 24 GPIO_ACTIVE_LOW>; linux,code = <259>; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index fe45d96239c9..3ce9ea987312 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -151,7 +152,7 @@ clock-names = "t0_clk", "slow_clk"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&slow_xtal>; @@ -540,6 +541,7 @@ dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; @@ -551,6 +553,7 @@ usart0: serial@fff8c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff8c000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -564,6 +567,7 @@ usart1: serial@fff90000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff90000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -577,6 +581,7 @@ usart2: serial@fff94000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff94000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 71f60576761a..ce8baff6a9f4 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -95,13 +95,17 @@ spi0: spi@fffa4000 { status = "okay"; cs-gpios = <&pioA 5 0>, <0>, <0>, <0>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <50000000>; reg = <0>; }; }; + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + }; + watchdog@fffffd40 { status = "okay"; }; @@ -228,17 +232,17 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - left_click { + button-left-click { label = "left_click"; gpios = <&pioC 5 GPIO_ACTIVE_LOW>; linux,code = <272>; wakeup-source; }; - right_click { + button-right-click { label = "right_click"; gpios = <&pioC 4 GPIO_ACTIVE_LOW>; linux,code = <273>; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index 87bb39060e8b..60d61291f344 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -110,7 +110,7 @@ spi0: spi@fffc8000 { cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - mtd_dataflash@1 { + flash@1 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <50000000>; reg = <1>; @@ -214,25 +214,37 @@ 24c512@50 { compatible = "atmel,24c512"; reg = <0x50>; + vcc-supply = <®_3v3>; }; wm8731: wm8731@1b { compatible = "wm8731"; reg = <0x1b>; + + /* PCK0 at 12MHz */ + clocks = <&pmc PMC_TYPE_SYSTEM 8>; + clock-names = "mclk"; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>; + assigned-clock-rates = <12000000>; + + HPVDD-supply = <&vcc_dac>; + AVDD-supply = <&vcc_dac>; + DCVDD-supply = <®_3v3>; + DBVDD-supply = <®_3v3>; }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - btn3 { + button-3 { label = "Button 3"; gpios = <&pioA 30 GPIO_ACTIVE_LOW>; linux,code = <0x103>; wakeup-source; }; - btn4 { + button-4 { label = "Button 4"; gpios = <&pioA 31 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; @@ -254,4 +266,35 @@ atmel,ssc-controller = <&ssc0>; atmel,audio-codec = <&wm8731>; }; + + reg_5v: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_3v3: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + vin-supply = <®_5v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_1v: fixedregulator2 { + compatible = "regulator-fixed"; + regulator-name = "1V"; + vin-supply = <®_5v>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vcc_dac: fixedregulator3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_DAC"; + vin-supply = <®_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; diff --git a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts index 7da70aeeb528..92f2c05c873f 100644 --- a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts +++ b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts @@ -23,7 +23,7 @@ gpio-keys { compatible = "gpio-keys"; - user_btn1 { + button { label = "USER_BTN1"; gpios = <&pioA 24 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 2ab730fd6472..95f5d76234db 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -137,7 +138,7 @@ clock-names = "slow_clk", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffd00 0x10>; clocks = <&clk32k>; @@ -675,6 +676,7 @@ dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; reg = <0xffffee00 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; @@ -687,6 +689,7 @@ usart0: serial@fff8c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff8c000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -700,6 +703,7 @@ usart1: serial@fff90000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff90000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -713,6 +717,7 @@ usart2: serial@fff94000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff94000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -726,6 +731,7 @@ usart3: serial@fff98000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff98000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index b6256a20fbc7..7f45e81ca165 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -167,7 +167,7 @@ spi0: spi@fffa4000{ status = "okay"; cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <13000000>; reg = <0>; @@ -343,48 +343,48 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - left_click { + button-left-click { label = "left_click"; gpios = <&pioB 6 GPIO_ACTIVE_LOW>; linux,code = <272>; wakeup-source; }; - right_click { + button-right-click { label = "right_click"; gpios = <&pioB 7 GPIO_ACTIVE_LOW>; linux,code = <273>; wakeup-source; }; - left { + button-left { label = "Joystick Left"; gpios = <&pioB 14 GPIO_ACTIVE_LOW>; linux,code = <105>; }; - right { + button-right { label = "Joystick Right"; gpios = <&pioB 15 GPIO_ACTIVE_LOW>; linux,code = <106>; }; - up { + button-up { label = "Joystick Up"; gpios = <&pioB 16 GPIO_ACTIVE_LOW>; linux,code = <103>; }; - down { + button-down { label = "Joystick Down"; gpios = <&pioB 17 GPIO_ACTIVE_LOW>; linux,code = <108>; }; - enter { + button-enter { label = "Joystick Press"; gpios = <&pioB 18 GPIO_ACTIVE_LOW>; linux,code = <28>; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 0785389f5507..83114d26f10d 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -126,7 +127,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; - rstc@fffffe00 { + reset-controller@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; @@ -593,6 +594,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; @@ -618,6 +620,7 @@ usart0: serial@f801c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x4000>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; @@ -629,6 +632,7 @@ usart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x4000>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; @@ -640,6 +644,7 @@ usart2: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x4000>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; @@ -651,6 +656,7 @@ usart3: serial@f8028000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8028000 0x4000>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 2bc4e6e0a923..4c644d4c6be7 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -119,7 +119,7 @@ spi0: spi@f0000000 { status = "okay"; cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; reg = <0>; @@ -226,10 +226,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - enter { + button-enter { label = "Enter"; gpios = <&pioB 3 GPIO_ACTIVE_LOW>; linux,code = <28>; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 730d1182c73e..364a2ff0a763 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -175,6 +176,7 @@ usart0: serial@fffb0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb0000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -188,6 +190,7 @@ usart1: serial@fffb4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb4000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -201,6 +204,7 @@ usart2: serial@fffb8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb8000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -214,6 +218,7 @@ usart3: serial@fffbc000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffbc000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -322,6 +327,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; @@ -766,7 +772,7 @@ clock-names = "slow_clk", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index 62981b39c815..a57351270551 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -180,7 +180,7 @@ spi0: spi@fffcc000 { status = "okay"; cs-gpios = <&pioA 28 0>, <0>, <0>, <0>; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; spi-max-frequency = <15000000>; reg = <0>; @@ -212,6 +212,10 @@ status = "okay"; }; + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + }; + rtc@fffffe00 { status = "okay"; }; @@ -244,17 +248,17 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - right_click { + button-right-click { label = "right_click"; gpios = <&pioB 0 GPIO_ACTIVE_LOW>; linux,code = <273>; wakeup-source; }; - left_click { + button-left-click { label = "left_click"; gpios = <&pioB 1 GPIO_ACTIVE_LOW>; linux,code = <272>; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 395e883644cd..0c26c925761b 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -134,7 +135,7 @@ clock-names = "slow_clk", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; @@ -674,6 +675,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; @@ -688,6 +690,7 @@ usart0: serial@f801c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; @@ -702,6 +705,7 @@ usart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; @@ -716,6 +720,7 @@ usart2: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; @@ -775,6 +780,7 @@ uart0: serial@f8040000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8040000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; @@ -786,6 +792,7 @@ uart1: serial@f8044000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8044000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi index 098d3fef5c37..a47c765e1b20 100644 --- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/mfd/at91-usart.h> / { aliases { @@ -44,6 +45,7 @@ usart3: serial@f8028000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8028000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index 6d1264de6060..5f4eaa618ab4 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi @@ -125,7 +125,7 @@ cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; status = "disabled"; /* conflicts with mmc1 */ - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/axm5516-cpus.dtsi index 3bcf4e0a3c85..f13ef80b6637 100644 --- a/arch/arm/boot/dts/axm5516-cpus.dtsi +++ b/arch/arm/boot/dts/axm5516-cpus.dtsi @@ -73,7 +73,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x00>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -81,7 +81,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x01>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -89,7 +89,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x02>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -97,7 +97,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x03>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -105,7 +105,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x100>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -113,7 +113,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x101>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -121,7 +121,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x102>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -129,7 +129,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x103>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -137,7 +137,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x200>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -145,7 +145,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x201>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -153,7 +153,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x202>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -161,7 +161,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x203>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -169,7 +169,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x300>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -177,7 +177,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x301>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -185,7 +185,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x302>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -193,7 +193,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x303>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; }; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index ad65be871938..f9f79ed82518 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -397,8 +397,8 @@ #size-cells = <0>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; pinctrl-0 = <&spi_0>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; status = "disabled"; }; @@ -409,8 +409,8 @@ #size-cells = <0>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; pinctrl-0 = <&spi_1>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; status = "disabled"; }; @@ -421,8 +421,8 @@ #size-cells = <0>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; pinctrl-0 = <&spi_2>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "sspclk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 6197e7d80e3b..53696078bbf0 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -1,15 +1,5 @@ -/* - * Copyright (C) 2012-2013 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2012-2013 Broadcom Corporation #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/bcm21664-garnet.dts index be468f4adc37..1854cd907a1b 100644 --- a/arch/arm/boot/dts/bcm21664-garnet.dts +++ b/arch/arm/boot/dts/bcm21664-garnet.dts @@ -1,15 +1,5 @@ -/* - * Copyright (C) 2014 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2014 Broadcom Corporation /dts-v1/; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index cc58f2b926b9..2684c37cb3a0 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -1,15 +1,5 @@ -/* - * Copyright (C) 2014 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2014 Broadcom Corporation #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/bcm2711-rpi-400.dts index f4d2fc20397c..c53d9eb0b802 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-400.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts @@ -28,12 +28,12 @@ &expgpio { gpio-line-names = "BT_ON", "WL_ON", - "", + "PWR_LED_OFF", "GLOBAL_RESET", "VDD_SD_IO_SEL", - "CAM_GPIO", + "GLOBAL_SHUTDOWN", "SD_PWR_ON", - "SD_OC_N"; + "SHUTDOWN_REQUEST"; }; &genet_mdio { diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/bcm2711-rpi.dtsi index ca266c5d9f9b..98817a6675b9 100644 --- a/arch/arm/boot/dts/bcm2711-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi @@ -69,6 +69,10 @@ }; }; +&v3d { + clocks = <&firmware_clocks 5>; +}; + &vchiq { interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index dff18fc9a906..941c4d16791b 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -107,12 +107,13 @@ }; pm: watchdog@7e100000 { - compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; + compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt"; #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x7e100000 0x114>, <0x7e00a000 0x24>, <0x7ec11000 0x20>; + reg-names = "pm", "asb", "rpivid_asb"; clocks = <&clocks BCM2835_CLOCK_V3D>, <&clocks BCM2835_CLOCK_PERI_IMAGE>, <&clocks BCM2835_CLOCK_H264>, @@ -290,6 +291,7 @@ hvs: hvs@7e400000 { compatible = "brcm,bcm2711-hvs"; + reg = <0x7e400000 0x8000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; }; @@ -458,12 +460,26 @@ #size-cells = <0>; enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/100095/0003 + * /Level-1-Memory-System/About-the-L1-memory-system?lang=en + * Source for d/i-cache-size + * https://www.raspberrypi.com/documentation/computers + * /processors.html#bcm2711 + */ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000d8>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -472,6 +488,13 @@ reg = <1>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000e0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -480,6 +503,13 @@ reg = <2>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000e8>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -488,6 +518,28 @@ reg = <3>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000f0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; + }; + + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/100095/0003 + * /Level-2-Memory-System/About-the-L2-memory-system?lang=en + * Source for d/i-cache-size + * https://www.raspberrypi.com/documentation/computers + * /processors.html#bcm2711 + */ + l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set + cache-level = <2>; }; }; @@ -550,6 +602,17 @@ #size-cells = <0x0>; }; }; + + v3d: gpu@7ec00000 { + compatible = "brcm,2711-v3d"; + reg = <0x0 0x7ec00000 0x4000>, + <0x0 0x7ec04000 0x4000>; + reg-names = "hub", "core0"; + + power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; + resets = <&pm BCM2835_RESET_V3D>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index ead6e9804dbf..fce3d5260b00 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -1,15 +1,5 @@ -/* - * Copyright (C) 2013 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2013 Broadcom Corporation /dts-v1/; @@ -31,22 +21,22 @@ }; i2c@3e016000 { - status="okay"; + status = "okay"; clock-frequency = <400000>; }; i2c@3e017000 { - status="okay"; + status = "okay"; clock-frequency = <400000>; }; i2c@3e018000 { - status="okay"; + status = "okay"; clock-frequency = <400000>; }; i2c@3500d000 { - status="okay"; + status = "okay"; clock-frequency = <100000>; pmu: pmu@8 { diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/bcm2835-common.dtsi index c25e797b9060..a037d2bc5b11 100644 --- a/arch/arm/boot/dts/bcm2835-common.dtsi +++ b/arch/arm/boot/dts/bcm2835-common.dtsi @@ -62,6 +62,7 @@ #reset-cells = <1>; reg = <0x7e100000 0x114>, <0x7e00a000 0x24>; + reg-names = "pm", "asb"; clocks = <&clocks BCM2835_CLOCK_V3D>, <&clocks BCM2835_CLOCK_PERI_IMAGE>, <&clocks BCM2835_CLOCK_H264>, diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 40b9405f1a8e..9b9a18bbb20a 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -32,7 +32,6 @@ * This is based on the unreleased schematic for the Model A+. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -67,21 +66,21 @@ "GPIO27", "SDA0", "SCL0", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ + "", /* GPIO30 */ + "", /* GPIO31 */ "CAM_GPIO1", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ + "", /* GPIO33 */ + "", /* GPIO34 */ "PWR_LOW_N", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ + "", /* GPIO36 */ + "", /* GPIO37 */ "USB_LIMIT", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO39 */ "PWM0_OUT", /* GPIO40 */ "CAM_GPIO0", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ "PWM1_OUT", /* GPIO45 */ "HDMI_HPD_N", "STATUS_LED", diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 11edb581dbaf..f664e4fced93 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -26,7 +26,6 @@ * RPI00021 sheet 02 * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -42,41 +41,41 @@ "SPI_MISO", "SPI_MOSI", "SPI_SCLK", - "NC", /* GPIO12 */ - "NC", /* GPIO13 */ + "", /* GPIO12 */ + "", /* GPIO13 */ /* Serial port */ "TXD0", "RXD0", "STATUS_LED_N", "GPIO17", "GPIO18", - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ + "", /* GPIO19 */ + "", /* GPIO20 */ "GPIO21", "GPIO22", "GPIO23", "GPIO24", "GPIO25", - "NC", /* GPIO26 */ + "", /* GPIO26 */ "CAM_GPIO0", /* Binary number representing build/revision */ "CONFIG0", "CONFIG1", "CONFIG2", "CONFIG3", - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ "PWM0_OUT", - "NC", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ + "", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ "PWM1_OUT", "HDMI_HPD_P", "SD_CARD_DET", diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index 1b435c64bd9c..248feb2ed23d 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -34,7 +34,6 @@ * RPI-BPLUS sheet 1 * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -69,21 +68,21 @@ "GPIO27", "SDA0", "SCL0", - "NC", /* GPIO30 */ + "", /* GPIO30 */ "LAN_RUN", /* GPIO31 */ "CAM_GPIO1", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ + "", /* GPIO33 */ + "", /* GPIO34 */ "PWR_LOW_N", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ + "", /* GPIO36 */ + "", /* GPIO37 */ "USB_LIMIT", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO39 */ "PWM0_OUT", /* GPIO40 */ "CAM_GPIO0", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "ETHCLK", /* GPIO44 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "ETH_CLK", /* GPIO44 */ "PWM1_OUT", /* GPIO45 */ "HDMI_HPD_N", "STATUS_LED", diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index a23c25c00eea..f5b66d3f4ff3 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -27,7 +27,6 @@ * RPI00022 sheet 02 * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -43,40 +42,40 @@ "SPI_MISO", "SPI_MOSI", "SPI_SCLK", - "NC", /* GPIO12 */ - "NC", /* GPIO13 */ + "", /* GPIO12 */ + "", /* GPIO13 */ /* Serial port */ "TXD0", "RXD0", "STATUS_LED_N", "GPIO17", "GPIO18", - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ + "", /* GPIO19 */ + "", /* GPIO20 */ "CAM_GPIO", "GPIO22", "GPIO23", "GPIO24", "GPIO25", - "NC", /* GPIO26 */ + "", /* GPIO26 */ "GPIO27", "GPIO28", "GPIO29", "GPIO30", "GPIO31", - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ "PWM0_OUT", - "NC", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ + "", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ "PWM1_OUT", "HDMI_HPD_P", "SD_CARD_DET", diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 1b63d6b19750..f589bede2b11 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -27,7 +27,6 @@ * RPI00021 sheet 02 * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -43,41 +42,40 @@ "SPI_MISO", "SPI_MOSI", "SPI_SCLK", - "NC", /* GPIO12 */ - "NC", /* GPIO13 */ + "", /* GPIO12 */ + "", /* GPIO13 */ /* Serial port */ "TXD0", "RXD0", "STATUS_LED_N", "GPIO17", "GPIO18", - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ - "GPIO21", + "", /* GPIO19 */ + "", /* GPIO20 */ + "CAM_GPIO0", "GPIO22", "GPIO23", "GPIO24", "GPIO25", - "NC", /* GPIO26 */ - "CAM_GPIO0", - /* Binary number representing build/revision */ - "CONFIG0", - "CONFIG1", - "CONFIG2", - "CONFIG3", - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ + "", /* GPIO26 */ + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "", /* GPIO32 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ "PWM0_OUT", - "NC", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ + "", /* GPIO41 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ "PWM1_OUT", "HDMI_HPD_P", "SD_CARD_DET", diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts index a75c882e6575..87958a96c3e0 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts @@ -13,7 +13,6 @@ * This is based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index 243236bc1e00..596bb1ef994e 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -39,7 +39,6 @@ * This is based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -74,19 +73,21 @@ "GPIO27", "SDA0", "SCL0", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", "CAM_GPIO1", /* GPIO40 */ "WL_ON", /* GPIO41 */ - "NC", /* GPIO42 */ + "", /* GPIO42 */ "WIFI_CLK", /* GPIO43 */ "CAM_GPIO0", /* GPIO44 */ "BT_ON", /* GPIO45 */ diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index 6f9b3a908f28..a65c2bca69ea 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -29,7 +29,6 @@ * This is based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -64,22 +63,22 @@ "GPIO27", "SDA0", "SCL0", - "NC", /* GPIO30 */ - "NC", /* GPIO31 */ + "", /* GPIO30 */ + "", /* GPIO31 */ "CAM_GPIO1", /* GPIO32 */ - "NC", /* GPIO33 */ - "NC", /* GPIO34 */ - "NC", /* GPIO35 */ - "NC", /* GPIO36 */ - "NC", /* GPIO37 */ - "NC", /* GPIO38 */ - "NC", /* GPIO39 */ - "NC", /* GPIO40 */ + "", /* GPIO33 */ + "", /* GPIO34 */ + "", /* GPIO35 */ + "", /* GPIO36 */ + "", /* GPIO37 */ + "", /* GPIO38 */ + "", /* GPIO39 */ + "", /* GPIO40 */ "CAM_GPIO0", /* GPIO41 */ - "NC", /* GPIO42 */ - "NC", /* GPIO43 */ - "NC", /* GPIO44 */ - "NC", /* GPIO45 */ + "", /* GPIO42 */ + "", /* GPIO43 */ + "", /* GPIO44 */ + "", /* GPIO45 */ "HDMI_HPD_N", "STATUS_LED_N", /* Used by SD Card */ diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index 0549686134ea..1c90e5a44283 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -14,6 +14,23 @@ device_type = "cpu"; compatible = "arm,arm1176jzf-s"; reg = <0x0>; + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/ddi0301 + * /h/level-one-memory-system/cache-organization?lang=en + * + * Source for d/i-cache-size + * https://forums.raspberrypi.com/viewtopic.php?t=98428 + * + * NOTE: The BCM2835 has a L2 cache but it is dedicated to the GPU + * It can be shared with the CPU through fw settings, + * but this is not recommended. + */ + d-cache-size = <0x4000>; + d-cache-line-size = <16>; + d-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set + i-cache-size = <0x4000>; + i-cache-line-size = <16>; + i-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set }; }; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index d8af8eeac7b6..3635502b1e0a 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -34,7 +34,6 @@ * the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -83,7 +82,7 @@ "CAM_GPIO0", "SMPS_SCL", "SMPS_SDA", - "ETHCLK", + "ETH_CLK", "PWM1_OUT", "HDMI_HPD_N", "STATUS_LED", diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi index b390006aef79..534dacfc4dd5 100644 --- a/arch/arm/boot/dts/bcm2836.dtsi +++ b/arch/arm/boot/dts/bcm2836.dtsi @@ -41,11 +41,26 @@ #size-cells = <0>; enable-method = "brcm,bcm2836-smp"; + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System + * /About-the-L1-memory-system?lang=en + * + * Source for d/i-cache-size + * https://forums.raspberrypi.com/viewtopic.php?t=98428 + */ + v7_cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; clock-frequency = <800000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set + next-level-cache = <&l2>; }; v7_cpu1: cpu@1 { @@ -53,6 +68,13 @@ compatible = "arm,cortex-a7"; reg = <0xf01>; clock-frequency = <800000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set + next-level-cache = <&l2>; }; v7_cpu2: cpu@2 { @@ -60,6 +82,13 @@ compatible = "arm,cortex-a7"; reg = <0xf02>; clock-frequency = <800000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set + next-level-cache = <&l2>; }; v7_cpu3: cpu@3 { @@ -67,6 +96,27 @@ compatible = "arm,cortex-a7"; reg = <0xf03>; clock-frequency = <800000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set + next-level-cache = <&l2>; + }; + + /* Source for cache-line-size + cache-sets + * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System + * /About-the-L2-Memory-system?lang=en + * Source for cache-size + * https://forums.raspberrypi.com/viewtopic.php?t=98428 + */ + l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; }; }; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts index d73daf5bff1d..f7222a28903e 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -55,7 +55,6 @@ * This is mostly based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index e12938baaf12..ec721d323ac5 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -45,7 +45,7 @@ #gpio-cells = <2>; gpio-line-names = "BT_ON", "WL_ON", - "STATUS_LED_R", + "PWR_LED_R", "LAN_RUN", "", "CAM_GPIO0", @@ -61,7 +61,6 @@ * the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -110,7 +109,7 @@ "SD1_DATA3", "PWM0_OUT", "PWM1_OUT", - "ETHCLK", + "ETH_CLK", "WIFI_CLK", "SDA0", "SCL0", diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 42b5383b55d8..fb6a417d73e7 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -54,7 +54,6 @@ * the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -103,7 +102,7 @@ "SD1_DATA3", "PWM0_OUT", "PWM1_OUT", - "ETHCLK", + "ETH_CLK", "WIFI_CLK", "SDA0", "SCL0", diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts index 588d9411ceb6..cf84e69fced8 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts @@ -13,7 +13,6 @@ * This is based on the official GPU firmware DT blob. * * Legend: - * "NC" = not connected (no rail from the SoC) * "FOO" = GPIO line named "FOO" on the schematic * "FOO_N" = GPIO line named "FOO" on schematic, active low */ @@ -63,8 +62,8 @@ "GPIO43", "GPIO44", "GPIO45", - "GPIO46", - "GPIO47", + "SMPS_SCL", + "SMPS_SDA", /* Used by eMMC */ "SD_CLK_R", "SD_CMD_R", diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi index 828a20561b96..f57b4ca145dd 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi @@ -41,12 +41,12 @@ #gpio-cells = <2>; gpio-line-names = "HDMI_HPD_N", "EMMC_EN_N", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; + "", + "", + "", + "", + "", + ""; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts b/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts new file mode 100644 index 000000000000..4a768562985e --- /dev/null +++ b/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Stefan Wahren <stefan.wahren@i2se.com> + */ + +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-usb-otg.dtsi" +#include "bcm283x-rpi-wifi-bt.dtsi" + +/ { + compatible = "raspberrypi,model-zero-2-w", "brcm,bcm2837"; + model = "Raspberry Pi Zero 2 W"; + + memory@0 { + device_type = "memory"; + reg = <0 0x20000000>; + }; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + leds { + led-act { + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&bt { + shutdown-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_N", + "NC", /* GPIO30 */ + "NC", /* GPIO31 */ + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "CAM_GPIO0", /* GPIO40 */ + "WL_ON", /* GPIO41 */ + "BT_ON", /* GPIO42 */ + "WIFI_CLK", /* GPIO43 */ + "SDA0", /* GPIO44 */ + "SCL0", /* GPIO45 */ + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&sdhci { + pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +&wifi_pwrseq { + reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi index 0199ec98cd61..5dbdebc46259 100644 --- a/arch/arm/boot/dts/bcm2837.dtsi +++ b/arch/arm/boot/dts/bcm2837.dtsi @@ -40,12 +40,26 @@ #size-cells = <0>; enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system + * /about-the-l1-memory-system?lang=en + * + * Source for d/i-cache-size + * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks + */ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000d8>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -54,6 +68,13 @@ reg = <1>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000e0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -62,6 +83,13 @@ reg = <2>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000e8>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -70,6 +98,27 @@ reg = <3>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000f0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; + }; + + /* Source for cache-line-size + cache-sets + * https://developer.arm.com/documentation/ddi0500 + * /e/level-2-memory-system/about-the-l2-memory-system?lang=en + * Source for cache-size + * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf + */ + l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set + cache-level = <2>; }; }; }; diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi index 967e081cb9c2..882b13807075 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi @@ -12,7 +12,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi index dc7ae776db5f..4273b90b53cc 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi @@ -11,7 +11,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index c113661a6668..d2d9c6e67f39 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -50,9 +50,9 @@ trips { cpu-crit { - temperature = <90000>; - hysteresis = <0>; - type = "critical"; + temperature = <90000>; + hysteresis = <0>; + type = "critical"; }; }; @@ -352,8 +352,6 @@ clocks = <&clocks BCM2835_CLOCK_VPU>, <&clocks BCM2835_CLOCK_DPI>; clock-names = "core", "pixel"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts index 8ed403767540..09ee3e46c0cc 100644 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts @@ -70,19 +70,19 @@ gpio-keys { compatible = "gpio-keys"; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts index 667b118ba4ee..32619c6045d3 100644 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts @@ -54,25 +54,25 @@ gpio-keys { compatible = "gpio-keys"; - brightness { + button-brightness { label = "Backlight"; linux,code = <KEY_BRIGHTNESS_ZERO>; gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi new file mode 100644 index 000000000000..a658b9b7bcec --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Buffalo WZR-1166DHP and WZR-1166DHP2 + * + * Copyright (C) 2014 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + * Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com> + */ + + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; + gpio-sck = <&chipcommon 7 0>; + gpio-mosi = <&chipcommon 4 0>; + cs-gpios = <&chipcommon 6 0>; + #address-cells = <1>; + #size-cells = <0>; + + hc595: gpio_spi@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + + gpio-controller; + #gpio-cells = <2>; + + }; + }; + + leds { + compatible = "gpio-leds"; + + usb { + /* label = "bcm53xx:blue:usb"; */ + function = LED_FUNCTION_USB; + color = <LED_COLOR_ID_BLUE>; + gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>, <&ohci_port2>, + <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + power0 { + /* label = "bcm53xx:red:power"; */ + function = LED_FUNCTION_FAULT; + color = <LED_COLOR_ID_RED>; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; + }; + + power1 { + /* label = "bcm53xx:white:power"; */ + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_WHITE>; + gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + router0 { + /* label = "bcm53xx:blue:router"; */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + router1 { + /* label = "bcm53xx:amber:router"; */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_AMBER>; + gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + }; + + wan { + /* label = "bcm53xx:blue:wan"; */ + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_BLUE>; + gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + wireless0 { + /* label = "bcm53xx:blue:wireless"; */ + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_BLUE>; + gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; + }; + + wireless1 { + /* label = "bcm53xx:amber:wireless"; */ + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_AMBER>; + gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + button-aoss { + label = "AOSS"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + }; + + /* Commit mode set by switch? */ + button-mode { + label = "Mode"; + linux,code = <KEY_SETUP>; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + /* Switch: AP mode */ + button-sw-ap { + label = "AP"; + linux,code = <BTN_0>; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + + button-eject { + label = "USB eject"; + linux,code = <KEY_EJECTCD>; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; +}; + +&spi_nor { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts new file mode 100644 index 000000000000..8e506269fa1a --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindigs for Buffalo WZR-1166DHP + * + * Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com> + */ + +/dts-v1/; + +#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi" + +/ { + compatible = "buffalo,wzr-1166dhp", "brcm,bcm4708"; + model = "Buffalo WZR-1166DHP"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + +}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts new file mode 100644 index 000000000000..596129027074 --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Bindigs for Buffalo WZR-1166DHP2 + * + * Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com> + */ + +/dts-v1/; + +#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi" + +/ { + compatible = "buffalo,wzr-1166dhp2", "brcm,bcm4708"; + model = "Buffalo WZR-1166DHP2"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + +}; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts index ff31ce45831a..f8f53457dd43 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts @@ -100,33 +100,33 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; - aoss { + button-aoss { label = "AOSS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; }; /* Commit mode set by switch? */ - mode { + button-mode { label = "Mode"; linux,code = <KEY_SETUP>; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; }; /* Switch: AP mode */ - sw_ap { + button-sw-ap { label = "AP"; linux,code = <BTN_0>; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; - eject { + button-eject { label = "USB eject"; linux,code = <KEY_EJECTCD>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts index 5bac1e15775a..0ed25bf71f0d 100644 --- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts +++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts @@ -29,13 +29,13 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts index cd797b4202ad..f1412ba83def 100644 --- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts +++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts @@ -25,13 +25,13 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index 5b4a481be4f4..14ee410183af 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -45,7 +45,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index c81944cd6d0b..600ab087f5e5 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -52,7 +52,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index 43a5d675dd67..fd6d8d2a4456 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -63,19 +63,19 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts index 4c60eda296d9..76fc1099d47d 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts @@ -59,19 +59,19 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts index 9ca6d1b2590d..6bcdfb73cb9e 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts @@ -94,19 +94,19 @@ gpio-keys { compatible = "gpio-keys"; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts index 0e273c598732..ca47cc4f2ba1 100644 --- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts @@ -60,13 +60,13 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index d00495a8b6fc..0edc2543e568 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -91,26 +91,26 @@ gpio-keys { compatible = "gpio-keys"; - aoss { + button-aoss { label = "AOSS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; /* Switch device mode? */ - mode { + button-mode { label = "Mode"; linux,code = <KEY_SETUP>; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; - eject { + button-eject { label = "USB eject"; linux,code = <KEY_EJECTCD>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts index 8b1a05a0f1a1..1f0998f34afd 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts @@ -96,7 +96,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index 68aaf0af3945..c8c02377543b 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -45,7 +45,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index 9316a36434f7..3b35a7af4b1c 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -94,7 +94,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts index 12e34a0439b4..19a7971b5a00 100644 --- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts @@ -77,13 +77,13 @@ gpio-keys { compatible = "gpio-keys"; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts index 7546c8d07bcd..f52a75c4ca09 100644 --- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts @@ -47,16 +47,14 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts index beae9eab9cb8..5ff6c588e16e 100644 --- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts @@ -77,42 +77,40 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - power { + button-power { label = "Power"; linux,code = <KEY_POWER>; gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; }; - aoss { + button-aoss { label = "AOSS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; }; /* Commit mode set by switch? */ - mode { + button-mode { label = "Mode"; linux,code = <KEY_SETUP>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; }; /* Switch: AP mode */ - sw_ap { + button-sw-ap { label = "AP"; linux,code = <BTN_0>; gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; }; - eject { + button-eject { label = "USB eject"; linux,code = <KEY_EJECTCD>; gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts index 7879f7d7d9c3..99253fd7adb3 100644 --- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts +++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts @@ -29,16 +29,14 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts index 56d309dbc6b0..de961fbb6200 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts @@ -72,22 +72,20 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts index 89f992af61d1..087f7f60de18 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -99,28 +99,26 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; }; - brightness { + button-brightness { label = "Backlight"; linux,code = <KEY_BRIGHTNESS_ZERO>; gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts index c2a266a439d0..11d1068160da 100644 --- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts +++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts @@ -77,16 +77,14 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 249476fdad7a..a5fec56d11c0 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright (C) 2021 Arınç ÃœNAL <arinc.unal@arinc9.com> + * Copyright (C) 2021-2022 Arınç ÃœNAL <arinc.unal@arinc9.com> */ /dts-v1/; @@ -25,6 +25,9 @@ nvram@1c080000 { compatible = "brcm,nvram"; reg = <0x1c080000 0x00180000>; + + et1macaddr: et1macaddr { + }; }; leds { @@ -69,30 +72,106 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; - wifi { + button-wifi { label = "Wi-Fi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; }; - led { + button-led { label = "Backlight"; linux,code = <KEY_BRIGHTNESS_ZERO>; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; }; + + switch { + compatible = "realtek,rtl8365mb"; + /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ + mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + realtek,disable-leds; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + phy-handle = <ðphy0>; + }; + + port@1 { + reg = <1>; + label = "lan6"; + phy-handle = <ðphy1>; + }; + + port@2 { + reg = <2>; + label = "lan7"; + phy-handle = <ðphy2>; + }; + + port@3 { + reg = <3>; + label = "lan8"; + phy-handle = <ðphy3>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&sw0_p5>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2100>; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + compatible = "realtek,smi-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + }; + }; }; &srab { @@ -101,9 +180,6 @@ dsa,member = <0 0>; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan4"; @@ -132,6 +208,7 @@ sw0_p5: port@5 { reg = <5>; label = "extsw"; + phy-mode = "rgmii"; fixed-link { speed = <1000>; @@ -155,7 +232,6 @@ reg = <8>; ethernet = <&gmac2>; label = "cpu"; - status = "disabled"; fixed-link { speed = <1000>; @@ -165,6 +241,15 @@ }; }; +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + nvmem-cells = <&et1macaddr>; + nvmem-cell-names = "mac-address"; +}; + &usb2 { vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index 60bfd52ee677..2c38b642a8b8 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -86,20 +86,20 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; /* Switch: router / extender */ - extender { + button-extender { label = "Extender"; linux,code = <BTN_0>; gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 9bef6b9bfa8d..86c7cc0fa70e 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -30,19 +30,19 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts index b51a0ee7e584..9ad15bcae1ca 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts index 6fa101f0a90d..ee24d3768536 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts @@ -43,7 +43,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts index b959a9504eea..6549d07b9887 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts index b0d8a688141d..654fcce9fded 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts @@ -34,10 +34,8 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index cbe8c8e4a301..bf053a2fcc7c 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -89,7 +89,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index 24ae3c8a3e09..78a90dd57a4e 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -25,6 +25,9 @@ nvram@1eff0000 { compatible = "brcm,nvram"; reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; }; leds { @@ -64,7 +67,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; @@ -72,6 +75,11 @@ }; }; +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + &usb3 { vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts index 42097a4c2659..f850dce37b20 100644 --- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts +++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts @@ -65,25 +65,25 @@ gpio-keys { compatible = "gpio-keys"; - brightness { + button-brightness { label = "Backlight"; linux,code = <KEY_BRIGHTNESS_ZERO>; gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts index a2566ad4619c..3bf6e24978ac 100644 --- a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts +++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts @@ -22,7 +22,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts index 57ca1cfaecd8..e20b6d2eb274 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts @@ -39,7 +39,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts index 2e1a7e382cb7..9d863570fcf3 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts index 07eb3a8287d6..55b92645b0f1 100644 --- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts @@ -59,19 +59,19 @@ gpio-keys { compatible = "gpio-keys"; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi new file mode 100644 index 000000000000..2df04528af82 --- /dev/null +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm47622", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>, <&CA7_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts new file mode 100644 index 000000000000..14f58033efeb --- /dev/null +++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Meraki MR26 / Codename: Venom + * + * Copyright (C) 2022 Christian Lamparter <chunkeey@gmail.com> + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + compatible = "meraki,mr26", "brcm,bcm53015", "brcm,bcm4708"; + model = "Meraki MR26"; + + memory@0 { + reg = <0x00000000 0x08000000>; + device_type = "memory"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_FAULT; + color = <LED_COLOR_ID_AMBER>; + gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; + panic-indicator; + }; + led-1 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + key-restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + clock-frequency = <50000000>; + /delete-property/ clocks; +}; + +&uart1 { + status = "disabled"; +}; + +&gmac0 { + status = "okay"; +}; + +&gmac1 { + status = "disabled"; +}; +&gmac2 { + status = "disabled"; +}; +&gmac3 { + status = "disabled"; +}; + +&nandcs { + nand-ecc-algo = "hw"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <0x1>; + #size-cells = <0x1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x200000>; + read-only; + }; + + partition@200000 { + label = "u-boot-env"; + reg = <0x200000 0x200000>; + /* empty */ + }; + + partition@400000 { + label = "u-boot-backup"; + reg = <0x400000 0x200000>; + /* empty */ + }; + + partition@600000 { + label = "u-boot-env-backup"; + reg = <0x600000 0x200000>; + /* empty */ + }; + + partition@800000 { + label = "ubi"; + reg = <0x800000 0x7780000>; + }; + }; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + reg = <0>; + label = "poe"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + + fixed-link { + speed = <1000>; + duplex-full; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_i2c>; + + clock-frequency = <100000>; + + ina219@40 { + compatible = "ti,ina219"; /* PoE power */ + reg = <0x40>; + shunt-resistor = <60000>; /* = 60 mOhms */ + }; + + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + pagesize = <32>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + /* it's empty */ + }; +}; + +&thermal { + status = "disabled"; + /* does not work, reads 418 degree Celsius */ +}; diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index 66c64a6ec414..e678bc03d816 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -13,7 +13,7 @@ #include <dt-bindings/leds/common.h> / { - compatible = "meraki,mr32", "brcm,brcm53016", "brcm,bcm4708"; + compatible = "meraki,mr32", "brcm,bcm53016", "brcm,bcm4708"; model = "Meraki MR32"; chosen { @@ -47,10 +47,8 @@ keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 603c700c706f..5fc1b847f4aa 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -455,7 +455,7 @@ reg = <0x180 0x4>; }; - pinctrl: pin-controller@1c0 { + pinctrl: pinctrl@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; reg-names = "cru_gpio_control"; @@ -568,9 +568,9 @@ trips { cpu-crit { - temperature = <125000>; - hysteresis = <0>; - type = "critical"; + temperature = <125000>; + hysteresis = <0>; + type = "critical"; }; }; diff --git a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts index 2e7fda9b998c..975f854f652f 100644 --- a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts +++ b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts @@ -34,7 +34,7 @@ status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { compatible = "m25p80"; reg = <0>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index cca49a2e2d62..b774a8d63813 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -9,8 +9,8 @@ / { #address-cells = <1>; #size-cells = <1>; - compatible = "brcm,bcm63138"; - model = "Broadcom BCM63138 DSL SoC"; + compatible = "brcm,bcm63138", "brcm,bcmbca"; + model = "Broadcom BCM963138 Reference Board"; interrupt-parent = <&gic>; aliases { diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi new file mode 100644 index 000000000000..df5307b6b3af --- /dev/null +++ b/arch/arm/boot/dts/bcm63148.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm63148", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + B15_0: cpu@0 { + device_type = "cpu"; + compatible = "brcm,brahma-b15"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B15_1: cpu@1 { + device_type = "cpu"; + compatible = "brcm,brahma-b15"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B15_0>, <&B15_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@80030000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x80030000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8000>; + + uart0: serial@600 { + compatible = "brcm,bcm6345-uart"; + reg = <0x600 0x20>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi new file mode 100644 index 000000000000..cbd094dde6d0 --- /dev/null +++ b/arch/arm/boot/dts/bcm63178.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm63178", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi new file mode 100644 index 000000000000..ce1b59faf800 --- /dev/null +++ b/arch/arm/boot/dts/bcm6756.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm6756", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>, <&CA7_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi new file mode 100644 index 000000000000..8aa47a2583b2 --- /dev/null +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm6846", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x1b>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi new file mode 100644 index 000000000000..620f51aee1a2 --- /dev/null +++ b/arch/arm/boot/dts/bcm6855.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm6855", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi new file mode 100644 index 000000000000..1e8b5fa96c25 --- /dev/null +++ b/arch/arm/boot/dts/bcm6878.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm6878", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts index a76c74b44bba..363009e747b3 100644 --- a/arch/arm/boot/dts/bcm911360_entphn.dts +++ b/arch/arm/boot/dts/bcm911360_entphn.dts @@ -47,10 +47,10 @@ stdout-path = "serial0:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - hook { + button-hook { label = "HOOK"; linux,code = <KEY_O>; gpios = <&gpio_asiu 48 0>; diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts index b0b8c774a37f..16e70a264faf 100644 --- a/arch/arm/boot/dts/bcm947189acdbmr.dts +++ b/arch/arm/boot/dts/bcm947189acdbmr.dts @@ -44,13 +44,13 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm947622.dts b/arch/arm/boot/dts/bcm947622.dts new file mode 100644 index 000000000000..6f083724ab8e --- /dev/null +++ b/arch/arm/boot/dts/bcm947622.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm47622.dtsi" + +/ { + model = "Broadcom BCM947622 Reference Board"; + compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts index 52feca0fb906..4fe3b3653376 100644 --- a/arch/arm/boot/dts/bcm953012er.dts +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -37,7 +37,7 @@ / { model = "NorthStar Enterprise Router (BCM953012ER)"; - compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708"; + compatible = "brcm,bcm953012er", "brcm,bcm53012", "brcm,bcm4708"; memory@0 { device_type = "memory"; @@ -47,13 +47,13 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/bcm953012hr.dts index 9140be7ec053..b070b69466bd 100644 --- a/arch/arm/boot/dts/bcm953012hr.dts +++ b/arch/arm/boot/dts/bcm953012hr.dts @@ -37,7 +37,7 @@ / { model = "NorthStar HR (BCM953012HR)"; - compatible = "brcm,bcm953012hr", "brcm,brcm53012", "brcm,bcm4708"; + compatible = "brcm,bcm953012hr", "brcm,bcm53012", "brcm,bcm4708"; aliases { ethernet0 = &gmac0; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts index de40bd59a5fa..f1e6bcaa1edd 100644 --- a/arch/arm/boot/dts/bcm953012k.dts +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -36,7 +36,7 @@ / { model = "NorthStar SVK (BCM953012K)"; - compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; + compatible = "brcm,bcm953012k", "brcm,bcm53012", "brcm,bcm4708"; aliases { serial0 = &uart0; diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts index 60376b62cd5f..15f023656df0 100644 --- a/arch/arm/boot/dts/bcm958522er.dts +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -136,7 +136,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts index 8eeb319f5b54..9b9c225a1fb3 100644 --- a/arch/arm/boot/dts/bcm958525er.dts +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -136,7 +136,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index dc86d5a91292..ca9311452739 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -152,7 +152,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts index c457e53d886e..9db3c851451a 100644 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -140,7 +140,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index c06871915a1c..32786e7c4e12 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -144,7 +144,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi index ba01054a76cf..c54451dde6dd 100644 --- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi +++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi @@ -13,7 +13,7 @@ autorepeat; poll-interval = <20>; - reset { + button-reset { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; @@ -57,10 +57,9 @@ led-4 { /* amber:power */ - function = LED_FUNCTION_POWER; + function = LED_FUNCTION_FAULT; color = <LED_COLOR_ID_AMBER>; gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; - default-state = "on"; }; led-5 { diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi index 7c487c74fd10..1830844c8404 100644 --- a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi +++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi @@ -14,7 +14,7 @@ autorepeat; poll-interval = <20>; - reset { + button-reset { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; @@ -106,10 +106,9 @@ led-a { /* amber:power */ - function = LED_FUNCTION_POWER; + function = LED_FUNCTION_FAULT; color = <LED_COLOR_ID_AMBER>; gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; - default-state = "on"; }; led-b { diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi index 6519b7c61af1..b0854d881ac6 100644 --- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi +++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi @@ -22,7 +22,7 @@ }; led-2 { - function = LED_FUNCTION_INDICATOR; + function = LED_FUNCTION_POWER; color = <LED_COLOR_ID_GREEN>; pwms = <&pwm 2 50000>; max-brightness = <255>; @@ -39,6 +39,8 @@ &amac2 { status = "okay"; + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; }; &ehci0 { @@ -53,6 +55,12 @@ reg = <0x50>; pagesize = <32>; read-only; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; }; }; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index b22fc6624ae4..74263d98de73 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -151,7 +151,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 0183f8965a74..69ebc7a913a7 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -155,7 +155,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/bcm963138.dts b/arch/arm/boot/dts/bcm963138.dts new file mode 100644 index 000000000000..d28c4f130ca2 --- /dev/null +++ b/arch/arm/boot/dts/bcm963138.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63138.dtsi" + +/ { + model = "Broadcom BCM963138 Reference Board"; + compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &serial0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&serial0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts index df5c8ab90627..15bec75be74c 100644 --- a/arch/arm/boot/dts/bcm963138dvt.dts +++ b/arch/arm/boot/dts/bcm963138dvt.dts @@ -8,7 +8,7 @@ #include "bcm63138.dtsi" / { - compatible = "brcm,BCM963138DVT", "brcm,bcm63138"; + compatible = "brcm,BCM963138DVT", "brcm,bcm63138", "brcm,bcmbca"; model = "Broadcom BCM963138DVT"; chosen { diff --git a/arch/arm/boot/dts/bcm963148.dts b/arch/arm/boot/dts/bcm963148.dts new file mode 100644 index 000000000000..98f6a6d09f50 --- /dev/null +++ b/arch/arm/boot/dts/bcm963148.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63148.dtsi" + +/ { + model = "Broadcom BCM963148 Reference Board"; + compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm963178.dts b/arch/arm/boot/dts/bcm963178.dts new file mode 100644 index 000000000000..fa096e9cde23 --- /dev/null +++ b/arch/arm/boot/dts/bcm963178.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63178.dtsi" + +/ { + model = "Broadcom BCM963178 Reference Board"; + compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96756.dts b/arch/arm/boot/dts/bcm96756.dts new file mode 100644 index 000000000000..9a4a87ba9c8a --- /dev/null +++ b/arch/arm/boot/dts/bcm96756.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6756.dtsi" + +/ { + model = "Broadcom BCM96756 Reference Board"; + compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96846.dts b/arch/arm/boot/dts/bcm96846.dts new file mode 100644 index 000000000000..c70ebccabc19 --- /dev/null +++ b/arch/arm/boot/dts/bcm96846.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6846.dtsi" + +/ { + model = "Broadcom BCM96846 Reference Board"; + compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96855.dts b/arch/arm/boot/dts/bcm96855.dts new file mode 100644 index 000000000000..4438152561ac --- /dev/null +++ b/arch/arm/boot/dts/bcm96855.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6855.dtsi" + +/ { + model = "Broadcom BCM96855 Reference Board"; + compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96878.dts b/arch/arm/boot/dts/bcm96878.dts new file mode 100644 index 000000000000..8fbc175cb452 --- /dev/null +++ b/arch/arm/boot/dts/bcm96878.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6878.dtsi" + +/ { + model = "Broadcom BCM96878 Reference Board"; + compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts index 007e34715956..e96bc3f2d5cf 100644 --- a/arch/arm/boot/dts/bcm988312hr.dts +++ b/arch/arm/boot/dts/bcm988312hr.dts @@ -140,7 +140,7 @@ &qspi { status = "okay"; bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 87c517d65f62..1fdd9a249165 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -52,15 +52,15 @@ enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <16>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; }; display-timings { @@ -278,7 +278,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins &spi1_cs0_pin>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index c3942b4e82ad..e46e4d22db39 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -419,7 +419,7 @@ edma0: edma@0 { compatible = "ti,edma3-tpcc"; /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ - reg = <0x0 0x8000>; + reg = <0x0 0x8000>; reg-names = "edma3_cc"; interrupts = <11 12>; interrupt-names = "edma3_ccint", "edma3_ccerrint"; @@ -430,14 +430,14 @@ }; edma0_tptc0: tptc@8000 { compatible = "ti,edma3-tptc"; - reg = <0x8000 0x400>; + reg = <0x8000 0x400>; interrupts = <13>; interrupt-names = "edm3_tcerrint"; power-domains = <&psc0 1>; }; edma0_tptc1: tptc@8400 { compatible = "ti,edma3-tptc"; - reg = <0x8400 0x400>; + reg = <0x8400 0x400>; interrupts = <32>; interrupt-names = "edm3_tcerrint"; power-domains = <&psc0 2>; @@ -445,7 +445,7 @@ edma1: edma@230000 { compatible = "ti,edma3-tpcc"; /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ - reg = <0x230000 0x8000>; + reg = <0x230000 0x8000>; reg-names = "edma3_cc"; interrupts = <93 94>; interrupt-names = "edma3_ccint", "edma3_ccerrint"; @@ -456,7 +456,7 @@ }; edma1_tptc0: tptc@238000 { compatible = "ti,edma3-tptc"; - reg = <0x238000 0x400>; + reg = <0x238000 0x400>; interrupts = <95>; interrupt-names = "edm3_tcerrint"; power-domains = <&psc1 21>; @@ -672,14 +672,16 @@ cppi41dma: dma-controller@201000 { compatible = "ti,da830-cppi41"; - reg = <0x201000 0x1000 + reg = <0x201000 0x1000 0x202000 0x1000 0x204000 0x4000>; reg-names = "controller", "scheduler", "queuemgr"; interrupts = <58>; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <4>; + dma-channels = <4>; power-domains = <&psc1 1>; status = "okay"; }; diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts index 8ef48c00f98d..fe3f9a970b18 100644 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ b/arch/arm/boot/dts/dm8148-evm.dts @@ -51,7 +51,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f2g16aadwp"; + linux,mtd-name = "micron,mt29f2g16aadwp"; #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 7702e048e110..8104969c67c1 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -1,8 +1,4 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <dt-bindings/bus/ti-sysc.h> #include <dt-bindings/clock/dm814.h> @@ -167,8 +163,11 @@ interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <30>; + dma-channels = <30>; #dma-requests = <256>; + dma-requests = <256>; }; }; diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts index 5126e2d72ed7..244a957f9ba3 100644 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ b/arch/arm/boot/dts/dm8168-evm.dts @@ -119,7 +119,7 @@ nand@0,0 { compatible = "ti,omap2-nand"; - linux,mtd-name= "micron,mt29f2g16aadwp"; + linux,mtd-name = "micron,mt29f2g16aadwp"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ @@ -177,7 +177,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcspi1_pins>; - m25p80@0 { + flash@0 { compatible = "w25x32"; spi-max-frequency = <48000000>; reg = <0>; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index a9e7274806f4..649b33194455 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -1,8 +1,4 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <dt-bindings/bus/ti-sysc.h> #include <dt-bindings/clock/dm816.h> @@ -655,8 +651,11 @@ interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <30>; + dma-channels = <30>; #dma-requests = <256>; + dma-requests = <256>; }; }; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 3e1584e787ae..2639b9fe0ab4 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -127,7 +127,7 @@ status = "okay"; /* spi0.0: 4M Flash Winbond W25Q32BV */ - spi-flash@0 { + flash@0 { compatible = "st,w25q32"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts index 273f12ca2512..a0e8996c2ffd 100644 --- a/arch/arm/boot/dts/dove-d2plug.dts +++ b/arch/arm/boot/dts/dove-d2plug.dts @@ -62,7 +62,7 @@ status = "okay"; /* spi0.0: 4M Flash Macronix MX25L3205D */ - spi-flash@0 { + flash@0 { compatible = "st,m25l3205d"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/dove-d3plug.dts index 826026c28f90..1e81d1b97055 100644 --- a/arch/arm/boot/dts/dove-d3plug.dts +++ b/arch/arm/boot/dts/dove-d3plug.dts @@ -79,7 +79,7 @@ status = "okay"; /* spi0.0: 2M Flash Macronix MX25L1605D */ - spi-flash@0 { + flash@0 { compatible = "st,m25l1605d"; spi-max-frequency = <86000000>; reg = <0>; diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts index 1754a62e014e..c1912dc6bfc3 100644 --- a/arch/arm/boot/dts/dove-dove-db.dts +++ b/arch/arm/boot/dts/dove-dove-db.dts @@ -27,7 +27,7 @@ status = "okay"; /* spi0.0: 4M Flash ST-M25P32-VMF6P */ - spi-flash@0 { + flash@0 { compatible = "st,m25p32"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 89e0bdaf3a85..00a36fba2fd2 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -122,8 +122,18 @@ bus-range = <0x00 0xff>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 16>; + interrupt-names = "intx", "error"; + interrupts = <16>, <15>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie1: pcie@2 { @@ -141,8 +151,18 @@ bus-range = <0x00 0xff>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 18>; + interrupt-names = "intx", "error"; + interrupts = <18>, <17>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts index c16e183822be..577114c4c20a 100644 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts @@ -51,7 +51,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f2g16aadwp"; + linux,mtd-name = "micron,mt29f2g16aadwp"; #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/dra62x.dtsi b/arch/arm/boot/dts/dra62x.dtsi index cc4878aaa8ea..cfefa670515c 100644 --- a/arch/arm/boot/dts/dra62x.dtsi +++ b/arch/arm/boot/dts/dra62x.dtsi @@ -1,8 +1,4 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only #include "dm814x.dtsi" diff --git a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi index e75569383dd8..747ff0db90c7 100644 --- a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi +++ b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for DRA7x SoC DSPEVE thermal * * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi index 0f71a9f37a72..68c43eb12c1a 100644 --- a/arch/arm/boot/dts/dra7-evm-common.dtsi +++ b/arch/arm/boot/dts/dra7-evm-common.dtsi @@ -135,7 +135,7 @@ status = "okay"; spi-max-frequency = <76800000>; - m25p80@0 { + flash@0 { compatible = "s25fl256s1"; spi-max-frequency = <76800000>; reg = <0>; diff --git a/arch/arm/boot/dts/dra7-iva-thermal.dtsi b/arch/arm/boot/dts/dra7-iva-thermal.dtsi index a7077321613f..0a31313065df 100644 --- a/arch/arm/boot/dts/dra7-iva-thermal.dtsi +++ b/arch/arm/boot/dts/dra7-iva-thermal.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for DRA7x SoC IVA thermal * * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 956a26d52a4c..5733e3a4ea8e 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -3482,8 +3482,7 @@ ti,timer-pwm; }; }; - - target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ + timer15_target: target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; reg = <0x2c000 0x4>, <0x2c010 0x4>; @@ -3511,7 +3510,7 @@ }; }; - target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ + timer16_target: target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; reg = <0x2e000 0x4>, <0x2e010 0x4>; @@ -4189,11 +4188,11 @@ reg = <0x1d0010 0x4>; reg-names = "sysc"; ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; + <SYSC_IDLE_NO>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; + power-domains = <&prm_vpe>; clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 6b485cbed8d5..97ce0c4f1df7 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -160,7 +160,7 @@ target-module@48210000 { compatible = "ti,sysc-omap4-simple", "ti,sysc"; power-domains = <&prm_mpu>; - clocks = <&mpu_clkctrl DRA7_MPU_CLKCTRL 0>; + clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; @@ -875,10 +875,10 @@ <0x58000014 4>; reg-names = "rev", "syss"; ti,syss-mask = <1>; - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>, - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>, - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>; clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; #address-cells = <1>; #size-cells = <1>; @@ -912,7 +912,7 @@ SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>; ti,syss-mask = <1>; - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; @@ -939,8 +939,8 @@ <SYSC_IDLE_SMART>, <SYSC_IDLE_SMART_WKUP>; ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; clock-names = "fck", "dss_clk"; #address-cells = <1>; #size-cells = <1>; @@ -979,7 +979,7 @@ compatible = "vivante,gc"; reg = <0x0 0x700>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dss_clkctrl DRA7_BB2D_CLKCTRL 0>; + clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>; clock-names = "core"; }; }; @@ -1333,26 +1333,26 @@ ti,no-reset-on-init; ti,no-idle; timer@0 { - assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; + assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; assigned-clock-parents = <&sys_32k_ck>; }; }; /* Local timers, see ARM architected timer wrap erratum i940 */ -&timer3_target { +&timer15_target { ti,no-reset-on-init; ti,no-idle; timer@0 { - assigned-clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>; + assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; assigned-clock-parents = <&timer_sys_clk_div>; }; }; -&timer4_target { +&timer16_target { ti,no-reset-on-init; ti,no-idle; timer@0 { - assigned-clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>; + assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; assigned-clock-parents = <&timer_sys_clk_div>; }; }; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index f12825268188..8948e10dbeb8 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -474,7 +474,7 @@ status = "okay"; spi-max-frequency = <76800000>; - m25p80@0 { + flash@0 { compatible = "s25fl256s1"; spi-max-frequency = <76800000>; reg = <0>; diff --git a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi index a9dce919d443..34eea3c048bd 100644 --- a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi +++ b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs. * * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /* diff --git a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi index e86da7a970b6..b9d040135c5f 100644 --- a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi +++ b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs. * * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /* diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index e2b7fcb061cf..57868ac60d29 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -511,7 +511,7 @@ &qspi { spi-max-frequency = <96000000>; - m25p80@0 { + flash@0 { spi-max-frequency = <96000000>; }; }; diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index bc4ae91cba16..931db7932c11 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -90,8 +90,8 @@ clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; reg = <0x03fc>; - ti,bit-shift=<20>; - ti,latch-bit=<26>; + ti,bit-shift = <20>; + ti,latch-bit = <26>; assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; assigned-clock-rates = <80000000>; }; @@ -102,7 +102,7 @@ clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; reg = <0x3fc>; ti,bit-shift = <29>; - ti,latch-bit=<26>; + ti,latch-bit = <26>; assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; }; diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 2365554eef3c..04a7a6d1d529 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -5,210 +5,244 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &cm_core_aon_clocks { - atl_clkin0_ck: atl_clkin0_ck { + atl_clkin0_ck: clock-atl-clkin0 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin0_ck"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; - atl_clkin1_ck: atl_clkin1_ck { + atl_clkin1_ck: clock-atl-clkin1 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin1_ck"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; - atl_clkin2_ck: atl_clkin2_ck { + atl_clkin2_ck: clock-atl-clkin2 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin2_ck"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; - atl_clkin3_ck: atl_clkin3_ck { + atl_clkin3_ck: clock-atl-clkin3 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; + clock-output-names = "atl_clkin3_ck"; clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; - hdmi_clkin_ck: hdmi_clkin_ck { + hdmi_clkin_ck: clock-hdmi-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "hdmi_clkin_ck"; clock-frequency = <0>; }; - mlb_clkin_ck: mlb_clkin_ck { + mlb_clkin_ck: clock-mlb-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "mlb_clkin_ck"; clock-frequency = <0>; }; - mlbp_clkin_ck: mlbp_clkin_ck { + mlbp_clkin_ck: clock-mlbp-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "mlbp_clkin_ck"; clock-frequency = <0>; }; - pciesref_acs_clk_ck: pciesref_acs_clk_ck { + pciesref_acs_clk_ck: clock-pciesref-acs { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "pciesref_acs_clk_ck"; clock-frequency = <100000000>; }; - ref_clkin0_ck: ref_clkin0_ck { + ref_clkin0_ck: clock-ref-clkin0 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "ref_clkin0_ck"; clock-frequency = <0>; }; - ref_clkin1_ck: ref_clkin1_ck { + ref_clkin1_ck: clock-ref-clkin1 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "ref_clkin1_ck"; clock-frequency = <0>; }; - ref_clkin2_ck: ref_clkin2_ck { + ref_clkin2_ck: clock-ref-clkin2 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "ref_clkin2_ck"; clock-frequency = <0>; }; - ref_clkin3_ck: ref_clkin3_ck { + ref_clkin3_ck: clock-ref-clkin3 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "ref_clkin3_ck"; clock-frequency = <0>; }; - rmii_clk_ck: rmii_clk_ck { + rmii_clk_ck: clock-rmii { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "rmii_clk_ck"; clock-frequency = <0>; }; - sdvenc_clkin_ck: sdvenc_clkin_ck { + sdvenc_clkin_ck: clock-sdvenc-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sdvenc_clkin_ck"; clock-frequency = <0>; }; - secure_32k_clk_src_ck: secure_32k_clk_src_ck { + secure_32k_clk_src_ck: clock-secure-32k-clk-src { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "secure_32k_clk_src_ck"; clock-frequency = <32768>; }; - sys_clk32_crystal_ck: sys_clk32_crystal_ck { + sys_clk32_crystal_ck: clock-sys-clk32-crystal { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sys_clk32_crystal_ck"; clock-frequency = <32768>; }; - sys_clk32_pseudo_ck: sys_clk32_pseudo_ck { + sys_clk32_pseudo_ck: clock-sys-clk32-pseudo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "sys_clk32_pseudo_ck"; clocks = <&sys_clkin1>; clock-mult = <1>; clock-div = <610>; }; - virt_12000000_ck: virt_12000000_ck { + virt_12000000_ck: clock-virt-12000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_12000000_ck"; clock-frequency = <12000000>; }; - virt_13000000_ck: virt_13000000_ck { + virt_13000000_ck: clock-virt-13000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_13000000_ck"; clock-frequency = <13000000>; }; - virt_16800000_ck: virt_16800000_ck { + virt_16800000_ck: clock-virt-16800000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_16800000_ck"; clock-frequency = <16800000>; }; - virt_19200000_ck: virt_19200000_ck { + virt_19200000_ck: clock-virt-19200000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; - virt_20000000_ck: virt_20000000_ck { + virt_20000000_ck: clock-virt-20000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_20000000_ck"; clock-frequency = <20000000>; }; - virt_26000000_ck: virt_26000000_ck { + virt_26000000_ck: clock-virt-26000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; - virt_27000000_ck: virt_27000000_ck { + virt_27000000_ck: clock-virt-27000000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_27000000_ck"; clock-frequency = <27000000>; }; - virt_38400000_ck: virt_38400000_ck { + virt_38400000_ck: clock-virt-38400000 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_38400000_ck"; clock-frequency = <38400000>; }; - sys_clkin2: sys_clkin2 { + sys_clkin2: clock-sys-clkin2 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sys_clkin2"; clock-frequency = <22579200>; }; - usb_otg_clkin_ck: usb_otg_clkin_ck { + usb_otg_clkin_ck: clock-usb-otg-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "usb_otg_clkin_ck"; clock-frequency = <0>; }; - video1_clkin_ck: video1_clkin_ck { + video1_clkin_ck: clock-video1-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "video1_clkin_ck"; clock-frequency = <0>; }; - video1_m2_clkin_ck: video1_m2_clkin_ck { + video1_m2_clkin_ck: clock-video1-m2-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "video1_m2_clkin_ck"; clock-frequency = <0>; }; - video2_clkin_ck: video2_clkin_ck { + video2_clkin_ck: clock-video2-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "video2_clkin_ck"; clock-frequency = <0>; }; - video2_m2_clkin_ck: video2_m2_clkin_ck { + video2_m2_clkin_ck: clock-video2-m2-clkin { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "video2_m2_clkin_ck"; clock-frequency = <0>; }; - dpll_abe_ck: dpll_abe_ck@1e0 { + dpll_abe_ck: clock@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; + clock-output-names = "dpll_abe_ck"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; - dpll_abe_x2_ck: dpll_abe_x2_ck { + dpll_abe_x2_ck: clock-dpll-abe-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_abe_x2_ck"; clocks = <&dpll_abe_ck>; }; - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { + dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -217,18 +251,20 @@ ti,invert-autoidle-bit; }; - abe_clk: abe_clk@108 { + abe_clk: clock-abe@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_clk"; clocks = <&dpll_abe_m2x2_ck>; ti,max-div = <4>; reg = <0x0108>; ti,index-power-of-two; }; - dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { + dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2_ck"; clocks = <&dpll_abe_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -237,9 +273,10 @@ ti,invert-autoidle-bit; }; - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { + dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m3x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -248,30 +285,34 @@ ti,invert-autoidle-bit; }; - dpll_core_byp_mux: dpll_core_byp_mux@12c { + dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_core_byp_mux"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x012c>; }; - dpll_core_ck: dpll_core_ck@120 { + dpll_core_ck: clock@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; - dpll_core_x2_ck: dpll_core_x2_ck { + dpll_core_x2_ck: clock-dpll-core-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; - dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { + dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h12x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -280,24 +321,27 @@ ti,invert-autoidle-bit; }; - mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { + mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_mpu_ck: dpll_mpu_ck@160 { + dpll_mpu_ck: clock@160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { + dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -306,42 +350,47 @@ ti,invert-autoidle-bit; }; - mpu_dclk_div: mpu_dclk_div { + mpu_dclk_div: clock-mpu-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_dclk_div"; clocks = <&dpll_mpu_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div { + dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dsp_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 { + dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_dsp_byp_mux"; clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x0240>; }; - dpll_dsp_ck: dpll_dsp_ck@234 { + dpll_dsp_ck: clock@234 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_dsp_ck"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; assigned-clocks = <&dpll_dsp_ck>; assigned-clock-rates = <600000000>; }; - dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { + dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_dsp_m2_ck"; clocks = <&dpll_dsp_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -352,34 +401,38 @@ assigned-clock-rates = <600000000>; }; - iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { + iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "iva_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { + dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_iva_byp_mux"; clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x01ac>; }; - dpll_iva_ck: dpll_iva_ck@1a0 { + dpll_iva_ck: clock@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_iva_ck"; clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; assigned-clocks = <&dpll_iva_ck>; assigned-clock-rates = <1165000000>; }; - dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { + dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_m2_ck"; clocks = <&dpll_iva_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -390,34 +443,38 @@ assigned-clock-rates = <388333334>; }; - iva_dclk: iva_dclk { + iva_dclk: clock-iva-dclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "iva_dclk"; clocks = <&dpll_iva_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 { + dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_gpu_byp_mux"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x02e4>; }; - dpll_gpu_ck: dpll_gpu_ck@2d8 { + dpll_gpu_ck: clock@2d8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_gpu_ck"; clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; assigned-clocks = <&dpll_gpu_ck>; assigned-clock-rates = <1277000000>; }; - dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { + dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gpu_m2_ck"; clocks = <&dpll_gpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -428,9 +485,10 @@ assigned-clock-rates = <425666667>; }; - dpll_core_m2_ck: dpll_core_m2_ck@130 { + dpll_core_m2_ck: clock-dpll-core-m2-8@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m2_ck"; clocks = <&dpll_core_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -439,32 +497,36 @@ ti,invert-autoidle-bit; }; - core_dpll_out_dclk_div: core_dpll_out_dclk_div { + core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "core_dpll_out_dclk_div"; clocks = <&dpll_core_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c { + dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_ddr_byp_mux"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x021c>; }; - dpll_ddr_ck: dpll_ddr_ck@210 { + dpll_ddr_ck: clock@210 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_ddr_ck"; clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 { + dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_m2_ck"; clocks = <&dpll_ddr_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -473,24 +535,27 @@ ti,invert-autoidle-bit; }; - dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 { + dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_gmac_byp_mux"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x02b4>; }; - dpll_gmac_ck: dpll_gmac_ck@2a8 { + dpll_gmac_ck: clock@2a8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_gmac_ck"; clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; }; - dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 { + dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_m2_ck"; clocks = <&dpll_gmac_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -499,72 +564,81 @@ ti,invert-autoidle-bit; }; - video2_dclk_div: video2_dclk_div { + video2_dclk_div: clock-video2-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video2_dclk_div"; clocks = <&video2_m2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - video1_dclk_div: video1_dclk_div { + video1_dclk_div: clock-video1-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video1_dclk_div"; clocks = <&video1_m2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - hdmi_dclk_div: hdmi_dclk_div { + hdmi_dclk_div: clock-hdmi-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "hdmi_dclk_div"; clocks = <&hdmi_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - per_dpll_hs_clk_div: per_dpll_hs_clk_div { + per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "per_dpll_hs_clk_div"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <2>; }; - usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { + usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "usb_dpll_hs_clk_div"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <3>; }; - eve_dpll_hs_clk_div: eve_dpll_hs_clk_div { + eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "eve_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_eve_byp_mux: dpll_eve_byp_mux@290 { + dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_eve_byp_mux"; clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x0290>; }; - dpll_eve_ck: dpll_eve_ck@284 { + dpll_eve_ck: clock@284 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_eve_ck"; clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; }; - dpll_eve_m2_ck: dpll_eve_m2_ck@294 { + dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_eve_m2_ck"; clocks = <&dpll_eve_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -573,17 +647,19 @@ ti,invert-autoidle-bit; }; - eve_dclk_div: eve_dclk_div { + eve_dclk_div: clock-eve-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "eve_dclk_div"; clocks = <&dpll_eve_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { + dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h13x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -592,9 +668,10 @@ ti,invert-autoidle-bit; }; - dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { + dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h14x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -603,9 +680,10 @@ ti,invert-autoidle-bit; }; - dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { + dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h22x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -614,9 +692,10 @@ ti,invert-autoidle-bit; }; - dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { + dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h23x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -625,9 +704,10 @@ ti,invert-autoidle-bit; }; - dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { + dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h24x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -636,15 +716,17 @@ ti,invert-autoidle-bit; }; - dpll_ddr_x2_ck: dpll_ddr_x2_ck { + dpll_ddr_x2_ck: clock-dpll-ddr-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_ddr_x2_ck"; clocks = <&dpll_ddr_ck>; }; - dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 { + dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_ddr_h11x2_ck"; clocks = <&dpll_ddr_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -653,15 +735,17 @@ ti,invert-autoidle-bit; }; - dpll_dsp_x2_ck: dpll_dsp_x2_ck { + dpll_dsp_x2_ck: clock-dpll-dsp-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_dsp_x2_ck"; clocks = <&dpll_dsp_ck>; }; - dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 { + dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_dsp_m3x2_ck"; clocks = <&dpll_dsp_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -672,15 +756,17 @@ assigned-clock-rates = <400000000>; }; - dpll_gmac_x2_ck: dpll_gmac_x2_ck { + dpll_gmac_x2_ck: clock-dpll-gmac-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_gmac_x2_ck"; clocks = <&dpll_gmac_ck>; }; - dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 { + dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_h11x2_ck"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -689,9 +775,10 @@ ti,invert-autoidle-bit; }; - dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 { + dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_h12x2_ck"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -700,9 +787,10 @@ ti,invert-autoidle-bit; }; - dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 { + dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_h13x2_ck"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -711,9 +799,10 @@ ti,invert-autoidle-bit; }; - dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc { + dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_gmac_m3x2_ck"; clocks = <&dpll_gmac_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -722,33 +811,37 @@ ti,invert-autoidle-bit; }; - gmii_m_clk_div: gmii_m_clk_div { + gmii_m_clk_div: clock-gmii-m-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "gmii_m_clk_div"; clocks = <&dpll_gmac_h11x2_ck>; clock-mult = <1>; clock-div = <2>; }; - hdmi_clk2_div: hdmi_clk2_div { + hdmi_clk2_div: clock-hdmi-clk2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "hdmi_clk2_div"; clocks = <&hdmi_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - hdmi_div_clk: hdmi_div_clk { + hdmi_div_clk: clock-hdmi-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "hdmi_div_clk"; clocks = <&hdmi_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - l3_iclk_div: l3_iclk_div@100 { + l3_iclk_div: clock-l3-iclk-div-4@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3_iclk_div"; ti,max-div = <2>; ti,bit-shift = <4>; reg = <0x0100>; @@ -756,374 +849,420 @@ ti,index-power-of-two; }; - l4_root_clk_div: l4_root_clk_div { + l4_root_clk_div: clock-l4-root-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l4_root_clk_div"; clocks = <&l3_iclk_div>; clock-mult = <1>; clock-div = <2>; }; - video1_clk2_div: video1_clk2_div { + video1_clk2_div: clock-video1-clk2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video1_clk2_div"; clocks = <&video1_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - video1_div_clk: video1_div_clk { + video1_div_clk: clock-video1-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video1_div_clk"; clocks = <&video1_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - video2_clk2_div: video2_clk2_div { + video2_clk2_div: clock-video2-clk2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video2_clk2_div"; clocks = <&video2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - video2_div_clk: video2_div_clk { + video2_div_clk: clock-video2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "video2_div_clk"; clocks = <&video2_clkin_ck>; clock-mult = <1>; clock-div = <1>; }; - dummy_ck: dummy_ck { + dummy_ck: clock-dummy { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "dummy_ck"; clock-frequency = <0>; }; }; &prm_clocks { - sys_clkin1: sys_clkin1@110 { + sys_clkin1: clock-sys-clkin1@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin1"; clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; reg = <0x0110>; ti,index-starts-at-one; }; - abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 { + abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_sys_clk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0118>; }; - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 { + abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_bypass_clk_mux"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x0114>; }; - abe_dpll_clk_mux: abe_dpll_clk_mux@10c { + abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_clk_mux"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x010c>; }; - abe_24m_fclk: abe_24m_fclk@11c { + abe_24m_fclk: clock-abe-24m@11c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_24m_fclk"; clocks = <&dpll_abe_m2x2_ck>; reg = <0x011c>; ti,dividers = <8>, <16>; }; - aess_fclk: aess_fclk@178 { + aess_fclk: clock-aess@178 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "aess_fclk"; clocks = <&abe_clk>; reg = <0x0178>; ti,max-div = <2>; }; - abe_giclk_div: abe_giclk_div@174 { + abe_giclk_div: clock-abe-giclk-div@174 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_giclk_div"; clocks = <&aess_fclk>; reg = <0x0174>; ti,max-div = <2>; }; - abe_lp_clk_div: abe_lp_clk_div@1d8 { + abe_lp_clk_div: clock-abe-lp-clk-div@1d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_lp_clk_div"; clocks = <&dpll_abe_m2x2_ck>; reg = <0x01d8>; ti,dividers = <16>, <32>; }; - abe_sys_clk_div: abe_sys_clk_div@120 { + abe_sys_clk_div: clock-abe-sys-clk-div@120 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_sys_clk_div"; clocks = <&sys_clkin1>; reg = <0x0120>; ti,max-div = <2>; }; - adc_gfclk_mux: adc_gfclk_mux@1dc { + adc_gfclk_mux: clock-adc-gfclk-mux@1dc { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "adc_gfclk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; reg = <0x01dc>; }; - sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 { + sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "sys_clk1_dclk_div"; clocks = <&sys_clkin1>; ti,max-div = <64>; reg = <0x01c8>; ti,index-power-of-two; }; - sys_clk2_dclk_div: sys_clk2_dclk_div@1cc { + sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "sys_clk2_dclk_div"; clocks = <&sys_clkin2>; ti,max-div = <64>; reg = <0x01cc>; ti,index-power-of-two; }; - per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc { + per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "per_abe_x1_dclk_div"; clocks = <&dpll_abe_m2_ck>; ti,max-div = <64>; reg = <0x01bc>; ti,index-power-of-two; }; - dsp_gclk_div: dsp_gclk_div@18c { + dsp_gclk_div: clock-dsp-gclk-div@18c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dsp_gclk_div"; clocks = <&dpll_dsp_m2_ck>; ti,max-div = <64>; reg = <0x018c>; ti,index-power-of-two; }; - gpu_dclk: gpu_dclk@1a0 { + gpu_dclk: clock-gpu-dclk@1a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "gpu_dclk"; clocks = <&dpll_gpu_m2_ck>; ti,max-div = <64>; reg = <0x01a0>; ti,index-power-of-two; }; - emif_phy_dclk_div: emif_phy_dclk_div@190 { + emif_phy_dclk_div: clock-emif-phy-dclk-div@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "emif_phy_dclk_div"; clocks = <&dpll_ddr_m2_ck>; ti,max-div = <64>; reg = <0x0190>; ti,index-power-of-two; }; - gmac_250m_dclk_div: gmac_250m_dclk_div@19c { + gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "gmac_250m_dclk_div"; clocks = <&dpll_gmac_m2_ck>; ti,max-div = <64>; reg = <0x019c>; ti,index-power-of-two; }; - gmac_main_clk: gmac_main_clk { + gmac_main_clk: clock-gmac-main { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "gmac_main_clk"; clocks = <&gmac_250m_dclk_div>; clock-mult = <1>; clock-div = <2>; }; - l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { + l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3init_480m_dclk_div"; clocks = <&dpll_usb_m2_ck>; ti,max-div = <64>; reg = <0x01ac>; ti,index-power-of-two; }; - usb_otg_dclk_div: usb_otg_dclk_div@184 { + usb_otg_dclk_div: clock-usb-otg-dclk-div@184 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "usb_otg_dclk_div"; clocks = <&usb_otg_clkin_ck>; ti,max-div = <64>; reg = <0x0184>; ti,index-power-of-two; }; - sata_dclk_div: sata_dclk_div@1c0 { + sata_dclk_div: clock-sata-dclk-div@1c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "sata_dclk_div"; clocks = <&sys_clkin1>; ti,max-div = <64>; reg = <0x01c0>; ti,index-power-of-two; }; - pcie2_dclk_div: pcie2_dclk_div@1b8 { + pcie2_dclk_div: clock-pcie2-dclk-div@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "pcie2_dclk_div"; clocks = <&dpll_pcie_ref_m2_ck>; ti,max-div = <64>; reg = <0x01b8>; ti,index-power-of-two; }; - pcie_dclk_div: pcie_dclk_div@1b4 { + pcie_dclk_div: clock-pcie-dclk-div@1b4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "pcie_dclk_div"; clocks = <&apll_pcie_m2_ck>; ti,max-div = <64>; reg = <0x01b4>; ti,index-power-of-two; }; - emu_dclk_div: emu_dclk_div@194 { + emu_dclk_div: clock-emu-dclk-div@194 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "emu_dclk_div"; clocks = <&sys_clkin1>; ti,max-div = <64>; reg = <0x0194>; ti,index-power-of-two; }; - secure_32k_dclk_div: secure_32k_dclk_div@1c4 { + secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "secure_32k_dclk_div"; clocks = <&secure_32k_clk_src_ck>; ti,max-div = <64>; reg = <0x01c4>; ti,index-power-of-two; }; - clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 { + clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkoutmux0_clk_mux"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x0158>; }; - clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c { + clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkoutmux1_clk_mux"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x015c>; }; - clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 { + clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "clkoutmux2_clk_mux"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x0160>; }; - custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { + custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "custefuse_sys_gfclk_div"; clocks = <&sys_clkin1>; clock-mult = <1>; clock-div = <2>; }; - eve_clk: eve_clk@180 { + eve_clk: clock-eve@180 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "eve_clk"; clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; reg = <0x0180>; }; - hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 { + hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "hdmi_dpll_clk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0164>; }; - mlb_clk: mlb_clk@134 { + mlb_clk: clock-mlb@134 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "mlb_clk"; clocks = <&mlb_clkin_ck>; ti,max-div = <64>; reg = <0x0134>; ti,index-power-of-two; }; - mlbp_clk: mlbp_clk@130 { + mlbp_clk: clock-mlbp@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "mlbp_clk"; clocks = <&mlbp_clkin_ck>; ti,max-div = <64>; reg = <0x0130>; ti,index-power-of-two; }; - per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 { + per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "per_abe_x1_gfclk2_div"; clocks = <&dpll_abe_m2_ck>; ti,max-div = <64>; reg = <0x0138>; ti,index-power-of-two; }; - timer_sys_clk_div: timer_sys_clk_div@144 { + timer_sys_clk_div: clock-timer-sys-clk-div@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "timer_sys_clk_div"; clocks = <&sys_clkin1>; reg = <0x0144>; ti,max-div = <2>; }; - video1_dpll_clk_mux: video1_dpll_clk_mux@168 { + video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "video1_dpll_clk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0168>; }; - video2_dpll_clk_mux: video2_dpll_clk_mux@16c { + video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "video2_dpll_clk_mux"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x016c>; }; - wkupaon_iclk_mux: wkupaon_iclk_mux@108 { + wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "wkupaon_iclk_mux"; clocks = <&sys_clkin1>, <&abe_lp_clk_div>; reg = <0x0108>; }; }; &cm_core_clocks { - dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { + dpll_pcie_ref_ck: clock@200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_pcie_ref_ck"; clocks = <&sys_clkin1>, <&sys_clkin1>; reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; }; - dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 { + dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_pcie_ref_m2ldo_ck"; clocks = <&dpll_pcie_ref_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -1132,23 +1271,26 @@ ti,invert-autoidle-bit; }; - apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { + apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 { compatible = "ti,mux-clock"; + clock-output-names = "apll_pcie_in_clk_mux"; clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; #clock-cells = <0>; reg = <0x021c 0x4>; ti,bit-shift = <7>; }; - apll_pcie_ck: apll_pcie_ck@21c { + apll_pcie_ck: clock@21c { #clock-cells = <0>; compatible = "ti,dra7-apll-clock"; + clock-output-names = "apll_pcie_ck"; clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; reg = <0x021c>, <0x0220>; }; - optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { + optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c { compatible = "ti,divider-clock"; + clock-output-names = "optfclk_pciephy_div"; clocks = <&apll_pcie_ck>; #clock-cells = <0>; reg = <0x021c>; @@ -1157,48 +1299,54 @@ ti,max-div = <2>; }; - apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { + apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "apll_pcie_clkvcoldo"; clocks = <&apll_pcie_ck>; clock-mult = <1>; clock-div = <1>; }; - apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div { + apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "apll_pcie_clkvcoldo_div"; clocks = <&apll_pcie_ck>; clock-mult = <1>; clock-div = <1>; }; - apll_pcie_m2_ck: apll_pcie_m2_ck { + apll_pcie_m2_ck: clock-apll-pcie-m2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "apll_pcie_m2_ck"; clocks = <&apll_pcie_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_per_byp_mux: dpll_per_byp_mux@14c { + dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_per_byp_mux"; clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x014c>; }; - dpll_per_ck: dpll_per_ck@140 { + dpll_per_ck: clock@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; - dpll_per_m2_ck: dpll_per_m2_ck@150 { + dpll_per_m2_ck: clock-dpll-per-m2-8@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -1207,32 +1355,36 @@ ti,invert-autoidle-bit; }; - func_96m_aon_dclk_div: func_96m_aon_dclk_div { + func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_96m_aon_dclk_div"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <1>; }; - dpll_usb_byp_mux: dpll_usb_byp_mux@18c { + dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_usb_byp_mux"; clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x018c>; }; - dpll_usb_ck: dpll_usb_ck@180 { + dpll_usb_ck: clock@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; + clock-output-names = "dpll_usb_ck"; clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { + dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_usb_m2_ck"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -1241,9 +1393,10 @@ ti,invert-autoidle-bit; }; - dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 { + dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_pcie_ref_m2_ck"; clocks = <&dpll_pcie_ref_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -1252,15 +1405,17 @@ ti,invert-autoidle-bit; }; - dpll_per_x2_ck: dpll_per_x2_ck { + dpll_per_x2_ck: clock-dpll-per-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_per_x2_ck"; clocks = <&dpll_per_ck>; }; - dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { + dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h11x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -1269,9 +1424,10 @@ ti,invert-autoidle-bit; }; - dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { + dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h12x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -1280,9 +1436,10 @@ ti,invert-autoidle-bit; }; - dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 { + dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h13x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -1291,9 +1448,10 @@ ti,invert-autoidle-bit; }; - dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { + dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h14x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; ti,autoidle-shift = <8>; @@ -1302,9 +1460,10 @@ ti,invert-autoidle-bit; }; - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { + dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -1313,105 +1472,118 @@ ti,invert-autoidle-bit; }; - dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { + dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_usb_clkdcoldo"; clocks = <&dpll_usb_ck>; clock-mult = <1>; clock-div = <1>; }; - func_128m_clk: func_128m_clk { + func_128m_clk: clock-func-128m { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_128m_clk"; clocks = <&dpll_per_h11x2_ck>; clock-mult = <1>; clock-div = <2>; }; - func_12m_fclk: func_12m_fclk { + func_12m_fclk: clock-func-12m-fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <16>; }; - func_24m_clk: func_24m_clk { + func_24m_clk: clock-func-24m { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_24m_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; }; - func_48m_fclk: func_48m_fclk { + func_48m_fclk: clock-func-48m-fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_48m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <4>; }; - func_96m_fclk: func_96m_fclk { + func_96m_fclk: clock-func-96m-fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_96m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <2>; }; - l3init_60m_fclk: l3init_60m_fclk@104 { + l3init_60m_fclk: clock-l3init-60m@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3init_60m_fclk"; clocks = <&dpll_usb_m2_ck>; reg = <0x0104>; ti,dividers = <1>, <8>; }; - clkout2_clk: clkout2_clk@6b0 { + clkout2_clk: clock-clkout2-8@6b0 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "clkout2_clk"; clocks = <&clkoutmux2_clk_mux>; ti,bit-shift = <8>; reg = <0x06b0>; }; - l3init_960m_gfclk: l3init_960m_gfclk@6c0 { + l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "l3init_960m_gfclk"; clocks = <&dpll_usb_clkdcoldo>; ti,bit-shift = <8>; reg = <0x06c0>; }; - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { + usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy1_always_on_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0640>; }; - usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 { + usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy2_always_on_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0688>; }; - usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 { + usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy3_always_on_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0698>; }; - gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { + gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpu_core_gclk_mux"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <24>; reg = <0x1220>; @@ -1419,9 +1591,10 @@ assigned-clock-parents = <&dpll_gpu_m2_ck>; }; - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { + gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpu_hyd_gclk_mux"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <26>; reg = <0x1220>; @@ -1429,34 +1602,38 @@ assigned-clock-parents = <&dpll_gpu_m2_ck>; }; - l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { + l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3instr_ts_gclk_div"; clocks = <&wkupaon_iclk_mux>; ti,bit-shift = <24>; reg = <0x0e50>; ti,dividers = <8>, <16>, <32>; }; - vip1_gclk_mux: vip1_gclk_mux@1020 { + vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "vip1_gclk_mux"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; ti,bit-shift = <24>; reg = <0x1020>; }; - vip2_gclk_mux: vip2_gclk_mux@1028 { + vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "vip2_gclk_mux"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; ti,bit-shift = <24>; reg = <0x1028>; }; - vip3_gclk_mux: vip3_gclk_mux@1030 { + vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "vip3_gclk_mux"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; ti,bit-shift = <24>; reg = <0x1030>; @@ -1464,48 +1641,54 @@ }; &cm_core_clockdomains { - coreaon_clkdm: coreaon_clkdm { + coreaon_clkdm: clock-coreaon-clkdm { compatible = "ti,clockdomain"; + clock-output-names = "coreaon_clkdm"; clocks = <&dpll_usb_ck>; }; }; &scm_conf_clocks { - dss_deshdcp_clk: dss_deshdcp_clk@558 { + dss_deshdcp_clk: clock-dss-deshdcp-0@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "dss_deshdcp_clk"; clocks = <&l3_iclk_div>; ti,bit-shift = <0>; reg = <0x558>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk@558 { + ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm0_tbclk"; clocks = <&l4_root_clk_div>; ti,bit-shift = <20>; reg = <0x0558>; }; - ehrpwm1_tbclk: ehrpwm1_tbclk@558 { + ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm1_tbclk"; clocks = <&l4_root_clk_div>; ti,bit-shift = <21>; reg = <0x0558>; }; - ehrpwm2_tbclk: ehrpwm2_tbclk@558 { + ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "ehrpwm2_tbclk"; clocks = <&l4_root_clk_div>; ti,bit-shift = <22>; reg = <0x0558>; }; - sys_32k_ck: sys_32k_ck { + sys_32k_ck: clock-sys-32k { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_32k_ck"; clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; ti,bit-shift = <8>; reg = <0x6c4>; @@ -1513,97 +1696,110 @@ }; &cm_core_aon { - mpu_cm: mpu-cm@300 { + mpu_cm: clock@300 { compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x300 0x100>; - mpu_clkctrl: mpu-clkctrl@20 { + mpu_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - dsp1_cm: dsp1-cm@400 { + dsp1_cm: clock@400 { compatible = "ti,omap4-cm"; + clock-output-names = "dsp1_cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x400 0x100>; - dsp1_clkctrl: dsp1-clkctrl@20 { + dsp1_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "dsp1_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - ipu_cm: ipu-cm@500 { + ipu_cm: clock@500 { compatible = "ti,omap4-cm"; + clock-output-names = "ipu_cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x500 0x100>; - ipu1_clkctrl: ipu1-clkctrl@20 { + ipu1_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "ipu1_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; assigned-clock-parents = <&dpll_core_h22x2_ck>; }; - ipu_clkctrl: ipu-clkctrl@50 { + ipu_clkctrl: clock@50 { compatible = "ti,clkctrl"; + clock-output-names = "ipu_clkctrl"; reg = <0x50 0x34>; #clock-cells = <2>; }; }; - dsp2_cm: dsp2-cm@600 { + dsp2_cm: clock@600 { compatible = "ti,omap4-cm"; + clock-output-names = "dsp2_cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; - dsp2_clkctrl: dsp2-clkctrl@20 { + dsp2_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "dsp2_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - rtc_cm: rtc-cm@700 { + rtc_cm: clock@700 { compatible = "ti,omap4-cm"; + clock-output-names = "rtc_cm"; reg = <0x700 0x60>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x700 0x60>; - rtc_clkctrl: rtc-clkctrl@20 { + rtc_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "rtc_clkctrl"; reg = <0x20 0x28>; #clock-cells = <2>; }; }; - vpe_cm: vpe-cm@760 { + vpe_cm: clock@760 { compatible = "ti,omap4-cm"; + clock-output-names = "vpe_cm"; reg = <0x760 0xc>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x760 0xc>; - vpe_clkctrl: vpe-clkctrl@0 { + vpe_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "vpe_clkctrl"; reg = <0x0 0xc>; #clock-cells = <2>; }; @@ -1612,212 +1808,242 @@ }; &cm_core { - coreaon_cm: coreaon-cm@600 { + coreaon_cm: clock@600 { compatible = "ti,omap4-cm"; + clock-output-names = "coreaon_cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; - coreaon_clkctrl: coreaon-clkctrl@20 { + coreaon_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "coreaon_clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; }; - l3main1_cm: l3main1-cm@700 { + l3main1_cm: clock@700 { compatible = "ti,omap4-cm"; + clock-output-names = "l3main1_cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x700 0x100>; - l3main1_clkctrl: l3main1-clkctrl@20 { + l3main1_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3main1_clkctrl"; reg = <0x20 0x74>; #clock-cells = <2>; }; }; - ipu2_cm: ipu2-cm@900 { + ipu2_cm: clock@900 { compatible = "ti,omap4-cm"; + clock-output-names = "ipu2_cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x900 0x100>; - ipu2_clkctrl: ipu2-clkctrl@20 { + ipu2_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "ipu2_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - dma_cm: dma-cm@a00 { + dma_cm: clock@a00 { compatible = "ti,omap4-cm"; + clock-output-names = "dma_cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xa00 0x100>; - dma_clkctrl: dma-clkctrl@20 { + dma_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "dma_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - emif_cm: emif-cm@b00 { + emif_cm: clock@b00 { compatible = "ti,omap4-cm"; + clock-output-names = "emif_cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xb00 0x100>; - emif_clkctrl: emif-clkctrl@20 { + emif_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "emif_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - atl_cm: atl-cm@c00 { + atl_cm: clock@c00 { compatible = "ti,omap4-cm"; + clock-output-names = "atl_cm"; reg = <0xc00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xc00 0x100>; - atl_clkctrl: atl-clkctrl@0 { + atl_clkctrl: clock@0 { compatible = "ti,clkctrl"; + clock-output-names = "atl_clkctrl"; reg = <0x0 0x4>; #clock-cells = <2>; }; }; - l4cfg_cm: l4cfg-cm@d00 { + l4cfg_cm: clock@d00 { compatible = "ti,omap4-cm"; + clock-output-names = "l4cfg_cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xd00 0x100>; - l4cfg_clkctrl: l4cfg-clkctrl@20 { + l4cfg_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4cfg_clkctrl"; reg = <0x20 0x84>; #clock-cells = <2>; }; }; - l3instr_cm: l3instr-cm@e00 { + l3instr_cm: clock@e00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3instr_cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xe00 0x100>; - l3instr_clkctrl: l3instr-clkctrl@20 { + l3instr_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3instr_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; - iva_cm: iva-cm@f00 { + iva_cm: clock@f00 { compatible = "ti,omap4-cm"; + clock-output-names = "iva_cm"; reg = <0xf00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xf00 0x100>; - iva_clkctrl: iva-clkctrl@20 { + iva_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "iva_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; - cam_cm: cam-cm@1000 { + cam_cm: clock@1000 { compatible = "ti,omap4-cm"; + clock-output-names = "cam_cm"; reg = <0x1000 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1000 0x100>; - cam_clkctrl: cam-clkctrl@20 { + cam_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "cam_clkctrl"; reg = <0x20 0x2c>; #clock-cells = <2>; }; }; - dss_cm: dss-cm@1100 { + dss_cm: clock@1100 { compatible = "ti,omap4-cm"; + clock-output-names = "dss_cm"; reg = <0x1100 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1100 0x100>; - dss_clkctrl: dss-clkctrl@20 { + dss_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "dss_clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; }; - gpu_cm: gpu-cm@1200 { + gpu_cm: clock@1200 { compatible = "ti,omap4-cm"; + clock-output-names = "gpu_cm"; reg = <0x1200 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1200 0x100>; - gpu_clkctrl: gpu-clkctrl@20 { + gpu_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "gpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - l3init_cm: l3init-cm@1300 { + l3init_cm: clock@1300 { compatible = "ti,omap4-cm"; + clock-output-names = "l3init_cm"; reg = <0x1300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1300 0x100>; - l3init_clkctrl: l3init-clkctrl@20 { + l3init_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3init_clkctrl"; reg = <0x20 0x6c>, <0xe0 0x14>; #clock-cells = <2>; }; - pcie_clkctrl: pcie-clkctrl@b0 { + pcie_clkctrl: clock@b0 { compatible = "ti,clkctrl"; + clock-output-names = "pcie_clkctrl"; reg = <0xb0 0xc>; #clock-cells = <2>; }; - gmac_clkctrl: gmac-clkctrl@d0 { + gmac_clkctrl: clock@d0 { compatible = "ti,clkctrl"; + clock-output-names = "gmac_clkctrl"; reg = <0xd0 0x4>; #clock-cells = <2>; }; }; - l4per_cm: l4per-cm@1700 { + l4per_cm: clock@1700 { compatible = "ti,omap4-cm"; + clock-output-names = "l4per_cm"; reg = <0x1700 0x300>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1700 0x300>; - l4per_clkctrl: l4per-clkctrl@28 { + l4per_clkctrl: clock@28 { compatible = "ti,clkctrl"; + clock-output-names = "l4per_clkctrl"; reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>; #clock-cells = <2>; @@ -1825,20 +2051,23 @@ assigned-clock-parents = <&abe_24m_fclk>; }; - l4sec_clkctrl: l4sec-clkctrl@1a0 { + l4sec_clkctrl: clock@1a0 { compatible = "ti,clkctrl"; + clock-output-names = "l4sec_clkctrl"; reg = <0x1a0 0x2c>; #clock-cells = <2>; }; - l4per2_clkctrl: l4per2-clkctrl@c { + l4per2_clkctrl: clock@c { compatible = "ti,clkctrl"; + clock-output-names = "l4per2_clkctrl"; reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>; #clock-cells = <2>; }; - l4per3_clkctrl: l4per3-clkctrl@14 { + l4per3_clkctrl: clock@14 { compatible = "ti,clkctrl"; + clock-output-names = "l4per3_clkctrl"; reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>; #clock-cells = <2>; }; @@ -1847,15 +2076,17 @@ }; &prm { - wkupaon_cm: wkupaon-cm@1800 { + wkupaon_cm: clock@1800 { compatible = "ti,omap4-cm"; + clock-output-names = "wkupaon_cm"; reg = <0x1800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1800 0x100>; - wkupaon_clkctrl: wkupaon-clkctrl@20 { + wkupaon_clkctrl: clock@20 { compatible = "ti,clkctrl"; + clock-output-names = "wkupaon_clkctrl"; reg = <0x20 0x6c>; #clock-cells = <2>; }; diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/e60k02.dtsi index 1a49f15f2df2..935e2359f8df 100644 --- a/arch/arm/boot/dts/e60k02.dtsi +++ b/arch/arm/boot/dts/e60k02.dtsi @@ -22,14 +22,14 @@ gpio_keys: gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - cover { + key-cover { label = "Cover"; gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; linux,code = <SW_LID>; diff --git a/arch/arm/boot/dts/e70k02.dtsi b/arch/arm/boot/dts/e70k02.dtsi index 156de653f2cd..27ef9a62b23c 100644 --- a/arch/arm/boot/dts/e70k02.dtsi +++ b/arch/arm/boot/dts/e70k02.dtsi @@ -26,14 +26,14 @@ gpio_keys: gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - cover { + key-cover { label = "Cover"; gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; linux,code = <SW_LID>; @@ -41,13 +41,13 @@ wakeup-source; }; - pageup { + key-pageup { label = "PageUp"; gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; linux,code = <KEY_PAGEUP>; }; - pagedown { + key-pagedown { label = "PageDown"; gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_PAGEDOWN>; diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi index 57a028a69373..ce5221c6b358 100644 --- a/arch/arm/boot/dts/ecx-common.dtsi +++ b/arch/arm/boot/dts/ecx-common.dtsi @@ -9,11 +9,11 @@ }; psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000002>; - cpu_off = <0x84000004>; - cpu_on = <0x84000006>; + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000002>; + cpu_off = <0x84000004>; + cpu_on = <0x84000006>; }; soc { diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts new file mode 100644 index 000000000000..f23a25cce119 --- /dev/null +++ b/arch/arm/boot/dts/en7523-evb.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7523.dtsi" + +/ { + model = "Airoha EN7523 Evaluation Board"; + compatible = "airoha,en7523-evb", "airoha,en7523"; + + aliases { + serial0 = &uart1; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + stdout-path = "serial0:115200n8"; + linux,usable-memory-range = <0x80200000 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi new file mode 100644 index 000000000000..7f839331a777 --- /dev/null +++ b/arch/arm/boot/dts/en7523.dtsi @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/en7523-clk.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + npu_binary@84000000 { + no-map; + reg = <0x84000000 0xA00000>; + }; + + npu_flag@84B0000 { + no-map; + reg = <0x84B00000 0x100000>; + }; + + npu_pkt@85000000 { + no-map; + reg = <0x85000000 0x1A00000>; + }; + + npu_phyaddr@86B00000 { + no-map; + reg = <0x86B00000 0x100000>; + }; + + npu_rxdesc@86D00000 { + no-map; + reg = <0x86D00000 0x100000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; + + gic: interrupt-controller@9000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x09000000 0x20000>, + <0x09080000 0x80000>, + <0x09400000 0x2000>, + <0x09500000 0x2000>, + <0x09600000 0x20000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + uart1: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x1fbf0000 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + status = "okay"; + }; + + gpio0: gpio@1fbf0200 { + compatible = "airoha,en7523-gpio"; + reg = <0x1fbf0204 0x4>, + <0x1fbf0200 0x4>, + <0x1fbf0220 0x4>, + <0x1fbf0214 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio1: gpio@1fbf0270 { + compatible = "airoha,en7523-gpio"; + reg = <0x1fbf0270 0x4>, + <0x1fbf0260 0x4>, + <0x1fbf0264 0x4>, + <0x1fbf0278 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; + + pcie0: pcie@1fa91000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa91000 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck0"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@1fa92000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa92000 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck1"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos-pinctrl.h b/arch/arm/boot/dts/exynos-pinctrl.h new file mode 100644 index 000000000000..e3a6df95281c --- /dev/null +++ b/arch/arm/boot/dts/exynos-pinctrl.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung Exynos DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ + +#define EXYNOS_PIN_PULL_NONE 0 +#define EXYNOS_PIN_PULL_DOWN 1 +#define EXYNOS_PIN_PULL_UP 3 + +/* Pin function in power down mode */ +#define EXYNOS_PIN_PDN_OUT0 0 +#define EXYNOS_PIN_PDN_OUT1 1 +#define EXYNOS_PIN_PDN_INPUT 2 +#define EXYNOS_PIN_PDN_PREV 3 + +/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ +#define EXYNOS4_PIN_DRV_LV1 0 +#define EXYNOS4_PIN_DRV_LV2 2 +#define EXYNOS4_PIN_DRV_LV3 1 +#define EXYNOS4_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos5260 */ +#define EXYNOS5260_PIN_DRV_LV1 0 +#define EXYNOS5260_PIN_DRV_LV2 1 +#define EXYNOS5260_PIN_DRV_LV4 2 +#define EXYNOS5260_PIN_DRV_LV6 3 + +/* + * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except + * GPIO_HSI block) + */ +#define EXYNOS5420_PIN_DRV_LV1 0 +#define EXYNOS5420_PIN_DRV_LV2 1 +#define EXYNOS5420_PIN_DRV_LV3 2 +#define EXYNOS5420_PIN_DRV_LV4 3 + +#define EXYNOS_PIN_FUNC_INPUT 0 +#define EXYNOS_PIN_FUNC_OUTPUT 1 +#define EXYNOS_PIN_FUNC_2 2 +#define EXYNOS_PIN_FUNC_3 3 +#define EXYNOS_PIN_FUNC_4 4 +#define EXYNOS_PIN_FUNC_5 5 +#define EXYNOS_PIN_FUNC_6 6 +#define EXYNOS_PIN_FUNC_EINT 0xf +#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT + +#endif /* __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 829c05b2c405..0ac3f284fbb8 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -356,15 +356,15 @@ }; &pinctrl_1 { - bten: bten { - samsung,pins ="gpx1-7"; + bten: bten-pins { + samsung,pins = "gpx1-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_DOWN>; }; - wlanen: wlanen { + wlanen: wlanen-pins { samsung,pins = "gpx2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -372,12 +372,12 @@ samsung,pin-val = <1>; }; - s2mps14_irq: s2mps14-irq { + s2mps14_irq: s2mps14-irq-pins { samsung,pins = "gpx3-5"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - bthostwake: bthostwake { + bthostwake: bthostwake-pins { samsung,pins = "gpx3-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; @@ -385,7 +385,7 @@ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; }; - btwake: btwake { + btwake: btwake-pins { samsung,pins = "gpx3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 8b41a9d5e2db..02a9dc479d34 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -69,7 +69,7 @@ reg = <0x25>; wakeup-source; - muic: max77836-muic { + extcon { compatible = "maxim,max77836-muic"; }; diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi index dff3c6e3aa1f..011ba2eff29e 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -9,50 +9,25 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" #define PIN_IN(_pin, _pull, _drv) \ - _pin { \ + pin- ## _pin { \ samsung,pins = #_pin; \ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \ samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \ samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \ } -#define PIN_OUT(_pin, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; \ - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; \ - samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \ - } - -#define PIN_OUT_SET(_pin, _val, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; \ - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; \ - samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \ - samsung,pin-val = <_val>; \ - } - -#define PIN_CFG(_pin, _sel, _pull, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <_sel>; \ - samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \ - samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \ - } - #define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ + pin- ## _pin { \ samsung,pins = #_pin; \ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \ } &pinctrl_0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -60,7 +35,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -68,7 +43,7 @@ #interrupt-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -76,7 +51,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -84,7 +59,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -92,7 +67,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -100,7 +75,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -108,84 +83,84 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c3_bus: i2c3-bus { + i2c3_bus: i2c3-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c4_bus: i2c4-bus { + i2c4_bus: i2c4-bus-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c5_bus: i2c5-bus { + i2c5_bus: i2c5-bus-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; @@ -193,7 +168,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pcm2_bus: pcm2-bus { + pcm2_bus: pcm2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -201,63 +176,63 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c6_bus: i2c6-bus { + i2c6_bus: i2c6-bus-pins { samsung,pins = "gpc1-3", "gpc1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpd0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpd0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c7_bus: i2c7-bus { + i2c7_bus: i2c7-bus-pins { samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpd0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpd0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - mipi0_clk: mipi0-clk { + mipi0_clk: mipi0-clk-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; @@ -266,22 +241,22 @@ }; &pinctrl_1 { - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpe2: gpe2 { + gpe2: gpe2-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpk0: gpk0 { + gpk0: gpk0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -289,7 +264,7 @@ #interrupt-cells = <2>; }; - gpk1: gpk1 { + gpk1: gpk1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -297,7 +272,7 @@ #interrupt-cells = <2>; }; - gpk2: gpk2 { + gpk2: gpk2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -305,7 +280,7 @@ #interrupt-cells = <2>; }; - gpl0: gpl0 { + gpl0: gpl0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -313,7 +288,7 @@ #interrupt-cells = <2>; }; - gpm0: gpm0 { + gpm0: gpm0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -321,7 +296,7 @@ #interrupt-cells = <2>; }; - gpm1: gpm1 { + gpm1: gpm1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -329,7 +304,7 @@ #interrupt-cells = <2>; }; - gpm2: gpm2 { + gpm2: gpm2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -337,7 +312,7 @@ #interrupt-cells = <2>; }; - gpm3: gpm3 { + gpm3: gpm3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -345,7 +320,7 @@ #interrupt-cells = <2>; }; - gpm4: gpm4 { + gpm4: gpm4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -353,7 +328,7 @@ #interrupt-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -370,7 +345,7 @@ #interrupt-cells = <2>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -387,7 +362,7 @@ #interrupt-cells = <2>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -395,7 +370,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -403,126 +378,126 @@ #interrupt-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpk0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpk0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpk0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_rdqs: sd0-rdqs { + sd0_rdqs: sd0-rdqs-pins { samsung,pins = "gpk0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpk0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpk1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpk1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpk1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpk1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpk2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpk2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpk2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpk2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - cam_port_b_io: cam-port-b-io { + cam_port_b_io: cam-port-b-io-pins { samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; @@ -531,35 +506,35 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_port_b_clk_active: cam-port-b-clk-active { + cam_port_b_clk_active: cam-port-b-clk-active-pins { samsung,pins = "gpm2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - cam_port_b_clk_idle: cam-port-b-clk-idle { + cam_port_b_clk_idle: cam-port-b-clk-idle-pins { samsung,pins = "gpm2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - fimc_is_i2c0: fimc-is-i2c0 { + fimc_is_i2c0: fimc-is-i2c0-pins { samsung,pins = "gpm4-0", "gpm4-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - fimc_is_i2c1: fimc-is-i2c1 { + fimc_is_i2c1: fimc-is-i2c1-pins { samsung,pins = "gpm4-2", "gpm4-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - fimc_is_uart: fimc-is-uart { + fimc_is_uart: fimc-is-uart-pins { samsung,pins = "gpm3-5", "gpm3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 5f7f8fedfb92..6d2c7bb19184 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -70,7 +70,7 @@ reg = <0x25>; wakeup-source; - muic: max77836-muic { + extcon { compatible = "maxim,max77836-muic"; }; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index a10b789d8acf..326b9e0ed8d3 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -269,7 +269,8 @@ }; timer@10050000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos3250-mct", + "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, @@ -375,7 +376,7 @@ status = "disabled"; }; - mshc_0: mshc@12510000 { + mshc_0: mmc@12510000 { compatible = "samsung,exynos5420-dw-mshc"; reg = <0x12510000 0x1000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; @@ -387,7 +388,7 @@ status = "disabled"; }; - mshc_1: mshc@12520000 { + mshc_1: mmc@12520000 { compatible = "samsung,exynos5420-dw-mshc"; reg = <0x12520000 0x1000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; @@ -399,7 +400,7 @@ status = "disabled"; }; - mshc_2: mshc@12530000 { + mshc_2: mmc@12530000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12530000 0x1000>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; @@ -421,26 +422,22 @@ status = "disabled"; }; - pdma0: pdma@12680000 { + pdma0: dma-controller@12680000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; - pdma1: pdma@12690000 { + pdma1: dma-controller@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; adc: adc@126c0000 { diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index eab77a66ae8f..5c4ecda27a47 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -316,7 +316,7 @@ status = "disabled"; }; - sdhci_0: sdhci@12510000 { + sdhci_0: mmc@12510000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12510000 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -325,7 +325,7 @@ status = "disabled"; }; - sdhci_1: sdhci@12520000 { + sdhci_1: mmc@12520000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12520000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; @@ -334,7 +334,7 @@ status = "disabled"; }; - sdhci_2: sdhci@12530000 { + sdhci_2: mmc@12530000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12530000 0x100>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; @@ -343,7 +343,7 @@ status = "disabled"; }; - sdhci_3: sdhci@12540000 { + sdhci_3: mmc@12540000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12540000 0x100>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; @@ -373,7 +373,7 @@ status = "disabled"; }; - ehci: ehci@12580000 { + ehci: usb@12580000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12580000 0x100>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; @@ -384,7 +384,7 @@ phy-names = "host", "hsic0", "hsic1"; }; - ohci: ohci@12590000 { + ohci: usb@12590000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12590000 0x100>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; @@ -669,37 +669,31 @@ status = "disabled"; }; - pdma0: pdma@12680000 { + pdma0: dma-controller@12680000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; - pdma1: pdma@12690000 { + pdma1: dma-controller@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; - mdma1: mdma@12850000 { + mdma1: dma-controller@12850000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12850000 0x1000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; }; fimd: fimd@11c00000 { diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 33894054b8b0..bba85011ecc9 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -89,21 +89,21 @@ gpio-keys { compatible = "gpio-keys"; - vol-down { + key-vol-down { gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; label = "volume down"; debounce-interval = <10>; }; - vol-up { + key-vol-up { gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; label = "volume up"; debounce-interval = <10>; }; - power { + key-power { gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "power"; @@ -111,7 +111,7 @@ wakeup-source; }; - ok { + key-ok { gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_OK>; label = "ok"; @@ -672,26 +672,26 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep0>; - sleep0: sleep-states { - gpa0-0 { + sleep0: sleep-state { + gpa0-0-pin { samsung,pins = "gpa0-0"; samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>; samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; }; - gpa0-1 { + gpa0-1-pin { samsung,pins = "gpa0-1"; samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT0>; samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; }; - gpa0-2 { + gpa0-2-pin { samsung,pins = "gpa0-2"; samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>; samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; }; - gpa0-3 { + gpa0-3-pin { samsung,pins = "gpa0-3"; samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>; samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; @@ -700,19 +700,19 @@ }; &pinctrl_1 { - mhl_int: mhl-int { + mhl_int: mhl-int-pins { samsung,pins = "gpf3-5"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - i2c_mhl_bus: i2c-mhl-bus { + i2c_mhl_bus: i2c-mhl-bus-pins { samsung,pins = "gpf0-4", "gpf0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - usb_sel: usb-sel { + usb_sel: usb-sel-pins { samsung,pins = "gpl0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -720,7 +720,7 @@ samsung,pin-val = <0>; }; - bt_en: bt-en { + bt_en: bt-en-pins { samsung,pins = "gpl0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -728,7 +728,7 @@ samsung,pin-val = <0>; }; - bt_res: bt-res { + bt_res: bt-res-pins { samsung,pins = "gpl1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -736,7 +736,7 @@ samsung,pin-val = <0>; }; - otg_gp: otg-gp { + otg_gp: otg-gp-pins { samsung,pins = "gpx3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -744,23 +744,23 @@ samsung,pin-val = <0>; }; - mag_mhl_gpio: mag-mhl { + mag_mhl_gpio: mag-mhl-pins { samsung,pins = "gpd0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - max8997_irq: max8997-irq { + max8997_irq: max8997-irq-pins { samsung,pins = "gpx0-7"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - max17042_fuel_irq: max17042-fuel-irq { + max17042_fuel_irq: max17042-fuel-irq-pins { samsung,pins = "gpx2-3"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - tsp224_irq: tsp224-irq { + tsp224_irq: tsp224-irq-pins { samsung,pins = "gpx0-4"; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; }; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 435fda60e86d..5f37b751f700 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -15,6 +15,7 @@ #include "exynos4210.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include "exynos-mfc-reserved-memory.dtsi" / { @@ -46,35 +47,35 @@ gpio-keys { compatible = "gpio-keys"; - up { + key-up { label = "Up"; gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; linux,code = <KEY_UP>; wakeup-source; }; - down { + key-down { label = "Down"; gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_DOWN>; wakeup-source; }; - back { + key-back { label = "Back"; gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; wakeup-source; }; - home { + key-home { label = "Home"; gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; wakeup-source; }; - menu { + key-menu { label = "Menu"; gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; @@ -86,6 +87,7 @@ compatible = "gpio-leds"; status { gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_HEARTBEAT; linux,default-trigger = "heartbeat"; }; }; @@ -316,7 +318,7 @@ }; &pinctrl_1 { - max8997_irq: max8997-irq { + max8997_irq: max8997-irq-pins { samsung,pins = "gpx0-3", "gpx0-4"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index 520c5934a8d4..76f44ae0de46 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -11,10 +11,10 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -22,7 +22,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -30,7 +30,7 @@ #interrupt-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -38,7 +38,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -46,7 +46,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -54,7 +54,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -62,7 +62,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -70,7 +70,7 @@ #interrupt-cells = <2>; }; - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -78,7 +78,7 @@ #interrupt-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -86,7 +86,7 @@ #interrupt-cells = <2>; }; - gpe2: gpe2 { + gpe2: gpe2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -94,7 +94,7 @@ #interrupt-cells = <2>; }; - gpe3: gpe3 { + gpe3: gpe3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -102,7 +102,7 @@ #interrupt-cells = <2>; }; - gpe4: gpe4 { + gpe4: gpe4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -110,7 +110,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -118,7 +118,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -126,7 +126,7 @@ #interrupt-cells = <2>; }; - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -134,7 +134,7 @@ #interrupt-cells = <2>; }; - gpf3: gpf3 { + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -142,112 +142,112 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart_audio_a: uart-audio-a { + uart_audio_a: uart-audio-a-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c3_bus: i2c3-bus { + i2c3_bus: i2c3-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart_audio_b: uart-audio-b { + uart_audio_b: uart-audio-b-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c4_bus: i2c4-bus { + i2c4_bus: i2c4-bus-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c5_bus: i2c5-bus { + i2c5_bus: i2c5-bus-pins { samsung,pins = "gpb-6", "gpb-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; @@ -255,7 +255,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -263,7 +263,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - ac97_bus: ac97-bus { + ac97_bus: ac97-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; @@ -271,7 +271,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; @@ -279,7 +279,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pcm2_bus: pcm2-bus { + pcm2_bus: pcm2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -287,105 +287,105 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spdif_bus: spdif-bus { + spdif_bus: spdif-bus-pins { samsung,pins = "gpc1-0", "gpc1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c6_bus: i2c6-bus { + i2c6_bus: i2c6-bus-pins { samsung,pins = "gpc1-3", "gpc1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_5>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c7_bus: i2c7-bus { + i2c7_bus: i2c7-bus-pins { samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpd0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpd0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpd0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpd0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_ctrl: lcd-ctrl { + lcd_ctrl: lcd-ctrl-pins { samsung,pins = "gpd0-0", "gpd0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_sync: lcd-sync { + lcd_sync: lcd-sync-pins { samsung,pins = "gpf0-0", "gpf0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_en: lcd-en { + lcd_en: lcd-en-pins { samsung,pins = "gpe3-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_clk: lcd-clk { + lcd_clk: lcd-clk-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_data16: lcd-data-width16 { + lcd_data16: lcd-data-width16-pins { samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", @@ -395,7 +395,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_data18: lcd-data-width18 { + lcd_data18: lcd-data-width18-pins { samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", @@ -406,7 +406,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_data24: lcd-data-width24 { + lcd_data24: lcd-data-width24-pins { samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", @@ -420,7 +420,7 @@ }; &pinctrl_1 { - gpj0: gpj0 { + gpj0: gpj0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -428,7 +428,7 @@ #interrupt-cells = <2>; }; - gpj1: gpj1 { + gpj1: gpj1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -436,7 +436,7 @@ #interrupt-cells = <2>; }; - gpk0: gpk0 { + gpk0: gpk0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -444,7 +444,7 @@ #interrupt-cells = <2>; }; - gpk1: gpk1 { + gpk1: gpk1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -452,7 +452,7 @@ #interrupt-cells = <2>; }; - gpk2: gpk2 { + gpk2: gpk2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -460,7 +460,7 @@ #interrupt-cells = <2>; }; - gpk3: gpk3 { + gpk3: gpk3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -468,7 +468,7 @@ #interrupt-cells = <2>; }; - gpl0: gpl0 { + gpl0: gpl0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -476,7 +476,7 @@ #interrupt-cells = <2>; }; - gpl1: gpl1 { + gpl1: gpl1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -484,7 +484,7 @@ #interrupt-cells = <2>; }; - gpl2: gpl2 { + gpl2: gpl2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -492,42 +492,42 @@ #interrupt-cells = <2>; }; - gpy0: gpy0 { + gpy0: gpy0-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy1: gpy1 { + gpy1: gpy1-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy2: gpy2 { + gpy2: gpy2-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy3: gpy3 { + gpy3: gpy3-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy4: gpy4 { + gpy4: gpy4-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy5: gpy5 { + gpy5: gpy5-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy6: gpy6 { + gpy6: gpy6-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -544,7 +544,7 @@ #interrupt-cells = <2>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -561,7 +561,7 @@ #interrupt-cells = <2>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -569,7 +569,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -577,238 +577,238 @@ #interrupt-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpk0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpk0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpk0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpk0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd4_clk: sd4-clk { + sd4_clk: sd4-clk-pins { samsung,pins = "gpk0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd4_cmd: sd4-cmd { + sd4_cmd: sd4-cmd-pins { samsung,pins = "gpk0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd4_cd: sd4-cd { + sd4_cd: sd4-cd-pins { samsung,pins = "gpk0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd4_bus1: sd4-bus-width1 { + sd4_bus1: sd4-bus-width1-pins { samsung,pins = "gpk0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd4_bus4: sd4-bus-width4 { + sd4_bus4: sd4-bus-width4-pins { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd4_bus8: sd4-bus-width8 { + sd4_bus8: sd4-bus-width8-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpk1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpk1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpk1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpk1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpk2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpk2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpk2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpk2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_bus8: sd2-bus-width8 { + sd2_bus8: sd2-bus-width8-pins { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_clk: sd3-clk { + sd3_clk: sd3-clk-pins { samsung,pins = "gpk3-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_cmd: sd3-cmd { + sd3_cmd: sd3-cmd-pins { samsung,pins = "gpk3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_cd: sd3-cd { + sd3_cd: sd3-cd-pins { samsung,pins = "gpk3-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_bus1: sd3-bus-width1 { + sd3_bus1: sd3-bus-width1-pins { samsung,pins = "gpk3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_bus4: sd3-bus-width4 { + sd3_bus4: sd3-bus-width4-pins { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - eint0: ext-int0 { + eint0: ext-int0-pins { samsung,pins = "gpx0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - eint8: ext-int8 { + eint8: ext-int8-pins { samsung,pins = "gpx1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - eint15: ext-int15 { + eint15: ext-int15-pins { samsung,pins = "gpx1-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - eint16: ext-int16 { + eint16: ext-int16-pins { samsung,pins = "gpx2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - eint31: ext-int31 { + eint31: ext-int31-pins { samsung,pins = "gpx3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_port_a_io: cam-port-a-io { + cam_port_a_io: cam-port-a-io-pins { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; @@ -817,21 +817,21 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_port_a_clk_active: cam-port-a-clk-active { + cam_port_a_clk_active: cam-port-a-clk-active-pins { samsung,pins = "gpj1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - cam_port_a_clk_idle: cam-port-a-clk-idle { + cam_port_a_clk_idle: cam-port-a-clk-idle-pins { samsung,pins = "gpj1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - hdmi_cec: hdmi-cec { + hdmi_cec: hdmi-cec-pins { samsung,pins = "gpx3-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -840,12 +840,12 @@ }; &pinctrl_2 { - gpz: gpz { + gpz: gpz-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; @@ -853,7 +853,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pcm0_bus: pcm0-bus { + pcm0_bus: pcm0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index d5797a67bf48..a5dfd7fd49b3 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -152,14 +152,14 @@ }; &pinctrl_1 { - keypad_rows: keypad-rows { + keypad_rows: keypad-rows-pins { samsung,pins = "gpx2-0", "gpx2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - keypad_cols: keypad-cols { + keypad_cols: keypad-cols-pins { samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 9c4ff7521348..b8e9dd23fc51 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -180,7 +180,7 @@ vdd3-supply = <&vcclcd_reg>; vci-supply = <&vlcd_reg>; reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; - power-on-delay= <50>; + power-on-delay = <50>; reset-delay = <100>; init-delay = <100>; flip-horizontal; @@ -464,19 +464,19 @@ }; &pinctrl_1 { - bt_shutdown: bt-shutdown { + bt_shutdown: bt-shutdown-pins { samsung,pins = "gpl1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - bt_host_wakeup: bt-host-wakeup { + bt_host_wakeup: bt-host-wakeup-pins { samsung,pins = "gpx2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - bt_device_wakeup: bt-device-wakeup { + bt_device_wakeup: bt-device-wakeup-pins { samsung,pins = "gpx3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 9f93e7464aed..62bf335d5bed 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -533,37 +533,37 @@ }; &pinctrl_1 { - bt_shutdown: bt-shutdown { + bt_shutdown: bt-shutdown-pins { samsung,pins = "gpe1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - bt_host_wakeup: bt-host-wakeup { + bt_host_wakeup: bt-host-wakeup-pins { samsung,pins = "gpx2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - bt_device_wakeup: bt-device-wakeup { + bt_device_wakeup: bt-device-wakeup-pins { samsung,pins = "gpx3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - lp3974_irq: lp3974-irq { + lp3974_irq: lp3974-irq-pins { samsung,pins = "gpx0-7", "gpx2-7"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - hdmi_hpd: hdmi-hpd { + hdmi_hpd: hdmi-hpd-pins { samsung,pins = "gpx3-7"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; }; &pinctrl_0 { - i2c_ddc_bus: i2c-ddc-bus { + i2c_ddc_bus: i2c-ddc-bus-pins { samsung,pins = "gpe4-2", "gpe4-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; @@ -659,15 +659,13 @@ }; &soc { - mdma0: mdma@12840000 { + mdma0: dma-controller@12840000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12840000 0x1000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; power-domains = <&pd_lcd0>; }; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 7e7d65ce6585..2c25cc37934e 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -527,8 +527,6 @@ compatible = "samsung,exynos4210-tmu"; clocks = <&clock CLK_TMU_APBIF>; clock-names = "tmu_apbif"; - samsung,tmu_gain = <15>; - samsung,tmu_reference_voltage = <7>; }; #include "exynos4210-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index c14e37dc3a9b..94122e9c6625 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -7,6 +7,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include "exynos4412-midas.dtsi" / { @@ -25,8 +26,9 @@ pinctrl-1 = <&camera_flash_host>; pinctrl-2 = <&camera_flash_isp>; - flash-led { - label = "flash"; + led { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; led-max-microamp = <520833>; flash-max-microamp = <1012500>; flash-max-timeout-us = <1940000>; @@ -107,7 +109,7 @@ vdd3-supply = <&lcd_vdd3_reg>; vci-supply = <&ldo25_reg>; reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; - power-on-delay= <50>; + power-on-delay = <50>; reset-delay = <100>; init-delay = <100>; flip-horizontal; @@ -151,13 +153,13 @@ }; &pinctrl_0 { - camera_flash_host: camera-flash-host { + camera_flash_host: camera-flash-host-pins { samsung,pins = "gpj1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-val = <0>; }; - camera_flash_isp: camera-flash-isp { + camera_flash_isp: camera-flash-isp-pins { samsung,pins = "gpj1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-val = <1>; diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index 47431307cb3c..202ab0fee3b7 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -11,6 +11,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include <dt-bindings/pwm/pwm.h> #include <dt-bindings/sound/samsung-i2s.h> #include "exynos4412-itop-scp-core.dtsi" @@ -28,7 +29,8 @@ compatible = "gpio-leds"; led2 { - label = "red:system"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_RED>; gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "heartbeat"; @@ -36,6 +38,7 @@ led3 { label = "red:user"; + color = <LED_COLOR_ID_RED>; gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; @@ -44,31 +47,31 @@ gpio-keys { compatible = "gpio-keys"; - home { + key-home { label = "GPIO Key Home"; linux,code = <KEY_HOME>; gpios = <&gpx1 1 GPIO_ACTIVE_LOW>; }; - back { + key-back { label = "GPIO Key Back"; linux,code = <KEY_BACK>; gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; }; - sleep { + key-sleep { label = "GPIO Key Sleep"; linux,code = <KEY_POWER>; gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; }; - vol-up { + key-vol-up { label = "GPIO Key Vol+"; linux,code = <KEY_UP>; gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; }; - vol-down { + key-vol-down { label = "GPIO Key Vol-"; linux,code = <KEY_DOWN>; gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; @@ -192,7 +195,7 @@ }; &pinctrl_1 { - ether-reset { + ether-reset-pins { samsung,pins = "gpc0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index b3726d4d7d93..a67cb61e3cbb 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -484,7 +484,7 @@ }; &pinctrl_1 { - hsic_reset: hsic-reset { + hsic_reset: hsic-reset-pins { samsung,pins = "gpm2-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 968c7943653e..8e1c19a8ad06 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -12,11 +12,12 @@ /dts-v1/; #include "exynos4412.dtsi" #include "exynos4412-ppmu-common.dtsi" + #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/clock/maxim,max77686.h> -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" / { compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; @@ -585,7 +586,7 @@ clocks = <&camera 1>; clock-names = "extclk"; samsung,camclk-out = <1>; - gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>; + gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; port { is_s5k6a3_ep: endpoint { @@ -987,19 +988,19 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep0>; - mhl_int: mhl-int { + mhl_int: mhl-int-pins { samsung,pins = "gpf3-5"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - i2c_mhl_bus: i2c-mhl-bus { + i2c_mhl_bus: i2c-mhl-bus-pins { samsung,pins = "gpf0-4", "gpf0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - sleep0: sleep-states { + sleep0: sleep-state { PIN_SLP(gpa0-0, INPUT, NONE); PIN_SLP(gpa0-1, OUT0, NONE); PIN_SLP(gpa0-2, INPUT, NONE); @@ -1102,52 +1103,52 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep1>; - gpio_keys: gpio-keys { + gpio_keys: gpio-keys-pins { samsung,pins = "gpx0-1", "gpx2-2", "gpx2-7", "gpx3-3"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - bt_shutdown: bt-shutdown { + bt_shutdown: bt-shutdown-pins { samsung,pins = "gpl0-6"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - bt_host_wakeup: bt-host-wakeup { + bt_host_wakeup: bt-host-wakeup-pins { samsung,pins = "gpx2-6"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - bt_device_wakeup: bt-device-wakeup { + bt_device_wakeup: bt-device-wakeup-pins { samsung,pins = "gpx3-1"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - max77686_irq: max77686-irq { + max77686_irq: max77686-irq-pins { samsung,pins = "gpx0-7"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - max77693_irq: max77693-irq { + max77693_irq: max77693-irq-pins { samsung,pins = "gpx1-5"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - max77693_fuel_irq: max77693-fuel-irq { + max77693_fuel_irq: max77693-fuel-irq-pins { samsung,pins = "gpx2-3"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - sdhci2_cd: sdhci2-cd-irq { + sdhci2_cd: sdhci2-cd-irq-pins { samsung,pins = "gpx3-4"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - hdmi_hpd: hdmi-hpd { + hdmi_hpd: hdmi-hpd-pins { samsung,pins = "gpx3-7"; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; }; - sleep1: sleep-states { + sleep1: sleep-state { PIN_SLP(gpk0-0, PREV, NONE); PIN_SLP(gpk0-1, PREV, NONE); PIN_SLP(gpk0-2, OUT0, NONE); @@ -1300,7 +1301,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep2>; - sleep2: sleep-states { + sleep2: sleep-state { PIN_SLP(gpz-0, INPUT, DOWN); PIN_SLP(gpz-1, INPUT, DOWN); PIN_SLP(gpz-2, INPUT, DOWN); @@ -1315,7 +1316,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep3>; - sleep3: sleep-states { + sleep3: sleep-state { PIN_SLP(gpv0-0, INPUT, DOWN); PIN_SLP(gpv0-1, INPUT, DOWN); PIN_SLP(gpv0-2, INPUT, DOWN); diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 5b1d4591b35c..e7669b9e9edb 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -172,24 +172,24 @@ }; &pinctrl_1 { - gpio_power_key: power-key { + gpio_power_key: power-key-pins { samsung,pins = "gpx1-3"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - max77686_irq: max77686-irq { + max77686_irq: max77686-irq-pins { samsung,pins = "gpx3-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - hdmi_hpd: hdmi-hpd { + hdmi_hpd: hdmi-hpd-pins { samsung,pins = "gpx3-7"; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; }; - emmc_rstn: emmc-rstn { + emmc_rstn: emmc-rstn-pins { samsung,pins = "gpk1-2"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index efaf7533e84f..a5ad88b897ff 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -9,6 +9,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include "exynos4412-odroid-common.dtsi" #include "exynos4412-prime.dtsi" @@ -37,7 +38,8 @@ leds { compatible = "gpio-leds"; led1 { - label = "led1:heart"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; default-state = "on"; linux,default-trigger = "heartbeat"; @@ -119,8 +121,8 @@ phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; phy-names = "hsic0", "hsic1"; - ethernet: usbether@2 { - compatible = "usb0424,9730"; + ethernet: ethernet@2 { + compatible = "usb424,9730"; reg = <2>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 440135d0ff2a..68d589e081bc 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -9,6 +9,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include "exynos4412-odroid-common.dtsi" / { @@ -27,13 +28,15 @@ leds { compatible = "gpio-leds"; led1 { - label = "led1:heart"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; default-state = "on"; linux,default-trigger = "heartbeat"; }; led2 { label = "led2:mmc0"; + function = LED_FUNCTION_DISK_ACTIVITY; gpios = <&gpc1 2 GPIO_ACTIVE_LOW>; default-state = "on"; linux,default-trigger = "mmc0"; @@ -70,19 +73,19 @@ phy-names = "hsic0"; hub@2 { - compatible = "usb0424,3503"; + compatible = "usb424,3503"; reg = <2>; #address-cells = <1>; #size-cells = <0>; hub@1 { - compatible = "usb0424,9514"; + compatible = "usb424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { - compatible = "usb0424,ec00"; + ethernet: ethernet@1 { + compatible = "usb424,ec00"; reg = <1>; /* Filled in by a bootloader */ local-mac-address = [00 00 00 00 00 00]; @@ -112,7 +115,7 @@ }; &pinctrl_1 { - gpio_home_key: home-key { + gpio_home_key: home-key-pins { samsung,pins = "gpx2-2"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index e6aec5facabf..a3905e27b9cd 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -95,7 +95,7 @@ }; &ehci { - samsung,vbus-gpio = <&gpx3 5 1>; + samsung,vbus-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>; status = "okay"; phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; phy-names = "hsic0", "hsic1"; @@ -506,14 +506,14 @@ }; &pinctrl_1 { - keypad_rows: keypad-rows { + keypad_rows: keypad-rows-pins { samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - keypad_cols: keypad-cols { + keypad_cols: keypad-cols-pins { samsung,pins = "gpx1-0", "gpx1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 22c3086e0076..7a515b87bc7c 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -15,7 +15,8 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/samsung.h> +#include <dt-bindings/power/summit,smb347-charger.h> +#include "exynos-pinctrl.h" / { compatible = "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; @@ -105,6 +106,16 @@ regulator-always-on; }; + panel_vdd: voltage-regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "LCD_ENABLE"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable>; + gpios = <&gpc0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + wlan_pwrseq: sdhci3-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpm3 5 GPIO_ACTIVE_LOW>; @@ -114,6 +125,17 @@ clock-names = "ext_clock"; }; + battery_cell: battery-cell { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + constant-charge-current-max-microamp = <2200000>; + precharge-current-microamp = <250000>; + charge-term-current-microamp = <250000>; + constant-charge-voltage-max-microvolt = <4200000>; + + power-supplies = <&power_supply>; + }; + i2c-gpio-1 { compatible = "i2c-gpio"; sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -182,6 +204,54 @@ }; }; }; + + i2c-gpio-4 { + compatible = "i2c-gpio"; + sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + power_supply: charger@6 { + compatible = "summit,smb347"; + reg = <0x6>; + summit,enable-usb-charging; + summit,enable-charge-control = <SMB3XX_CHG_ENABLE_SW>; + summit,fast-voltage-threshold-microvolt = <2600000>; + summit,chip-temperature-threshold-celsius = <130>; + summit,usb-current-limit-microamp = <1800000>; + + monitored-battery = <&battery_cell>; + }; + }; + + panel { + compatible = "samsung,ltl101al01"; + pinctrl-0 = <&lvds_nshdn>; + pinctrl-names = "default"; + power-supply = <&panel_vdd>; + enable-gpios = <&gpm0 5 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_ep>; + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-0 = <&led_bl_reset>; + pinctrl-names = "default"; + enable-gpios = <&gpm0 1 GPIO_ACTIVE_HIGH>; + pwms = <&pwm 1 78770 0>; + brightness-levels = <0 48 128 255>; + num-interpolated-steps = <8>; + default-brightness-level = <12>; + }; }; &adc { @@ -261,22 +331,19 @@ }; &fimd { - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; + pinctrl-0 = <&lcd_clk &lcd_data24>; pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; - display-timings { - timing0 { - clock-frequency = <66666666>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <18>; - hback-porch = <36>; - hsync-len = <16>; - vback-porch = <16>; - vfront-porch = <4>; - vsync-len = <3>; - hsync-active = <1>; + samsung,invert-vclk; + + port@3 { + reg = <3>; + + fimd_ep: endpoint { + remote-endpoint = <&lcd_ep>; }; }; }; @@ -641,19 +708,25 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep0>; - tsp_reg_gpio_2: tsp-reg-gpio-2 { + tsp_reg_gpio_2: tsp-reg-gpio-2-pins { samsung,pins = "gpb-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - tsp_reg_gpio_3: tsp-reg-gpio-3 { + tsp_reg_gpio_3: tsp-reg-gpio-3-pins { samsung,pins = "gpb-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - sleep0: sleep-states { + lcd_enable: lcd-enable-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + sleep0: sleep-state { PIN_SLP(gpa0-0, INPUT, NONE); PIN_SLP(gpa0-1, OUT0, NONE); PIN_SLP(gpa0-2, INPUT, NONE); @@ -755,19 +828,19 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep1>; - sd3_wifi: sd3-wifi { + sd3_wifi: sd3-wifi-pins { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - bt_shutdown: bt-shutdown { + bt_shutdown: bt-shutdown-pins { samsung,pins = "gpl0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - uart_sel: uart-sel { + uart_sel: uart-sel-pins { samsung,pins = "gpl2-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -775,82 +848,94 @@ /* 0 = CP, 1 = AP (serial output) */ }; - tsp_rst: tsp-rst { + led_bl_reset: led-bl-reset-pins { + samsung,pins = "gpm0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + tsp_rst: tsp-rst-pins { samsung,pins = "gpm0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - tsp_irq: tsp-irq { + lvds_nshdn: lvds-nshdn-pins { + samsung,pins = "gpm0-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + tsp_irq: tsp-irq-pins { samsung,pins = "gpm2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - wifi_reset: wifi-reset { + wifi_reset: wifi-reset-pins { samsung,pins = "gpm3-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - tsp_reg_gpio_1: tsp-reg-gpio-1 { + tsp_reg_gpio_1: tsp-reg-gpio-1-pins { samsung,pins = "gpm4-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - ak8975_irq: ak8975-irq { + ak8975_irq: ak8975-irq-pins { samsung,pins = "gpm4-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; }; - stmpe_adc_irq: stmpe-adc-irq { + stmpe_adc_irq: stmpe-adc-irq-pins { samsung,pins = "gpx0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - max77686_irq: max77686-irq { + max77686_irq: max77686-irq-pins { samsung,pins = "gpx0-7"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - gpio_keys: gpio-keys { + gpio_keys: gpio-keys-pins { samsung,pins = "gpx2-2", "gpx2-7", "gpx3-3"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - fuel_alert_irq: fuel-alert-irq { + fuel_alert_irq: fuel-alert-irq-pins { samsung,pins = "gpx2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - wifi_host_wake: wifi-host-wake { + wifi_host_wake: wifi-host-wake-pins { samsung,pins = "gpx2-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; }; - bt_host_wakeup: bt-host-wakeup { + bt_host_wakeup: bt-host-wakeup-pins { samsung,pins = "gpx2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - bt_device_wakeup: bt-device-wakeup { + bt_device_wakeup: bt-device-wakeup-pins { samsung,pins = "gpx3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - sdhci2_cd: sdhci2-cd { + sdhci2_cd: sdhci2-cd-pins { samsung,pins = "gpx3-4"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; - sleep1: sleep-states { + sleep1: sleep-state { PIN_SLP(gpk0-0, PREV, NONE); PIN_SLP(gpk0-1, PREV, NONE); PIN_SLP(gpk0-2, PREV, NONE); @@ -1004,7 +1089,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep2>; - sleep2: sleep-states { + sleep2: sleep-state { PIN_SLP(gpz-0, INPUT, DOWN); PIN_SLP(gpz-1, INPUT, DOWN); PIN_SLP(gpz-2, INPUT, DOWN); @@ -1019,7 +1104,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep3>; - sleep3: sleep-states { + sleep3: sleep-state { PIN_SLP(gpv0-0, INPUT, DOWN); PIN_SLP(gpv0-1, INPUT, DOWN); PIN_SLP(gpv0-2, INPUT, DOWN); @@ -1066,6 +1151,13 @@ assigned-clock-parents = <&clock CLK_XUSBXTI>; }; +&pwm { + pinctrl-0 = <&pwm1_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <1>; + status = "okay"; +}; + &rtc { clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; clock-names = "rtc", "rtc_src"; diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi index d7d5fdc230d8..58847d4fa846 100644 --- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi @@ -9,7 +9,7 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" #define PIN_SLP(_pin, _mode, _pull) \ _pin { \ @@ -19,7 +19,7 @@ } &pinctrl_0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -27,7 +27,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -35,7 +35,7 @@ #interrupt-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -43,7 +43,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -51,7 +51,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -59,7 +59,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -67,7 +67,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -75,7 +75,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -83,7 +83,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -91,7 +91,7 @@ #interrupt-cells = <2>; }; - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -99,7 +99,7 @@ #interrupt-cells = <2>; }; - gpf3: gpf3 { + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -107,7 +107,7 @@ #interrupt-cells = <2>; }; - gpj0: gpj0 { + gpj0: gpj0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -115,7 +115,7 @@ #interrupt-cells = <2>; }; - gpj1: gpj1 { + gpj1: gpj1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -123,112 +123,112 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart_audio_a: uart-audio-a { + uart_audio_a: uart-audio-a-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c3_bus: i2c3-bus { + i2c3_bus: i2c3-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart_audio_b: uart-audio-b { + uart_audio_b: uart-audio-b-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c4_bus: i2c4-bus { + i2c4_bus: i2c4-bus-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c5_bus: i2c5-bus { + i2c5_bus: i2c5-bus-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; @@ -236,7 +236,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -244,7 +244,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - ac97_bus: ac97-bus { + ac97_bus: ac97-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; @@ -252,7 +252,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; @@ -260,7 +260,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pcm2_bus: pcm2-bus { + pcm2_bus: pcm2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -268,105 +268,105 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spdif_bus: spdif-bus { + spdif_bus: spdif-bus-pins { samsung,pins = "gpc1-0", "gpc1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c6_bus: i2c6-bus { + i2c6_bus: i2c6-bus-pins { samsung,pins = "gpc1-3", "gpc1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_5>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpd0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpd0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_ctrl: lcd-ctrl { + lcd_ctrl: lcd-ctrl-pins { samsung,pins = "gpd0-0", "gpd0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c7_bus: i2c7-bus { + i2c7_bus: i2c7-bus-pins { samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpd0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpd0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - mipi0_clk: mipi0-clk { + mipi0_clk: mipi0-clk-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - mipi1_clk: mipi1-clk { + mipi1_clk: mipi1-clk-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_clk: lcd-clk { + lcd_clk: lcd-clk-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_data16: lcd-data-width16 { + lcd_data16: lcd-data-width16-pins { samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", @@ -376,7 +376,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_data18: lcd-data-width18 { + lcd_data18: lcd-data-width18-pins { samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", @@ -387,7 +387,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_data24: lcd-data-width24 { + lcd_data24: lcd-data-width24-pins { samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", @@ -399,14 +399,14 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lcd_ldi: lcd-ldi { + lcd_ldi: lcd-ldi-pins { samsung,pins = "gpf3-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_port_a_io: cam-port-a-io { + cam_port_a_io: cam-port-a-io-pins { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; @@ -415,14 +415,14 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_port_a_clk_active: cam-port-a-clk-active { + cam_port_a_clk_active: cam-port-a-clk-active-pins { samsung,pins = "gpj1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - cam_port_a_clk_idle: cam-port-a-clk-idle { + cam_port_a_clk_idle: cam-port-a-clk-idle-pins { samsung,pins = "gpj1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; @@ -431,7 +431,7 @@ }; &pinctrl_1 { - gpk0: gpk0 { + gpk0: gpk0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -439,7 +439,7 @@ #interrupt-cells = <2>; }; - gpk1: gpk1 { + gpk1: gpk1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -447,7 +447,7 @@ #interrupt-cells = <2>; }; - gpk2: gpk2 { + gpk2: gpk2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -455,7 +455,7 @@ #interrupt-cells = <2>; }; - gpk3: gpk3 { + gpk3: gpk3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -463,7 +463,7 @@ #interrupt-cells = <2>; }; - gpl0: gpl0 { + gpl0: gpl0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -471,7 +471,7 @@ #interrupt-cells = <2>; }; - gpl1: gpl1 { + gpl1: gpl1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -479,7 +479,7 @@ #interrupt-cells = <2>; }; - gpl2: gpl2 { + gpl2: gpl2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -487,7 +487,7 @@ #interrupt-cells = <2>; }; - gpm0: gpm0 { + gpm0: gpm0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -495,7 +495,7 @@ #interrupt-cells = <2>; }; - gpm1: gpm1 { + gpm1: gpm1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -503,7 +503,7 @@ #interrupt-cells = <2>; }; - gpm2: gpm2 { + gpm2: gpm2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -511,7 +511,7 @@ #interrupt-cells = <2>; }; - gpm3: gpm3 { + gpm3: gpm3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -519,7 +519,7 @@ #interrupt-cells = <2>; }; - gpm4: gpm4 { + gpm4: gpm4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -527,42 +527,42 @@ #interrupt-cells = <2>; }; - gpy0: gpy0 { + gpy0: gpy0-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy1: gpy1 { + gpy1: gpy1-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy2: gpy2 { + gpy2: gpy2-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy3: gpy3 { + gpy3: gpy3-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy4: gpy4 { + gpy4: gpy4-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy5: gpy5 { + gpy5: gpy5-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy6: gpy6 { + gpy6: gpy6-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -579,7 +579,7 @@ #interrupt-cells = <2>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -596,7 +596,7 @@ #interrupt-cells = <2>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -604,7 +604,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -612,203 +612,203 @@ #interrupt-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpk0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpk0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpk0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpk0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd4_clk: sd4-clk { + sd4_clk: sd4-clk-pins { samsung,pins = "gpk0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd4_cmd: sd4-cmd { + sd4_cmd: sd4-cmd-pins { samsung,pins = "gpk0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd4_cd: sd4-cd { + sd4_cd: sd4-cd-pins { samsung,pins = "gpk0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd4_bus1: sd4-bus-width1 { + sd4_bus1: sd4-bus-width1-pins { samsung,pins = "gpk0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd4_bus4: sd4-bus-width4 { + sd4_bus4: sd4-bus-width4-pins { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd4_bus8: sd4-bus-width8 { + sd4_bus8: sd4-bus-width8-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpk1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpk1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpk1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpk1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpk2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpk2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpk2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpk2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_bus8: sd2-bus-width8 { + sd2_bus8: sd2-bus-width8-pins { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_clk: sd3-clk { + sd3_clk: sd3-clk-pins { samsung,pins = "gpk3-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_cmd: sd3-cmd { + sd3_cmd: sd3-cmd-pins { samsung,pins = "gpk3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_cd: sd3-cd { + sd3_cd: sd3-cd-pins { samsung,pins = "gpk3-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_bus1: sd3-bus-width1 { + sd3_bus1: sd3-bus-width1-pins { samsung,pins = "gpk3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_bus4: sd3-bus-width4 { + sd3_bus4: sd3-bus-width4-pins { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - cam_port_b_io: cam-port-b-io { + cam_port_b_io: cam-port-b-io-pins { samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; @@ -817,77 +817,77 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_port_b_clk_active: cam-port-b-clk-active { + cam_port_b_clk_active: cam-port-b-clk-active-pins { samsung,pins = "gpm2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - cam_port_b_clk_idle: cam-port-b-clk-idle { + cam_port_b_clk_idle: cam-port-b-clk-idle-pins { samsung,pins = "gpm2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - eint0: ext-int0 { + eint0: ext-int0-pins { samsung,pins = "gpx0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - eint8: ext-int8 { + eint8: ext-int8-pins { samsung,pins = "gpx1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - eint15: ext-int15 { + eint15: ext-int15-pins { samsung,pins = "gpx1-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - eint16: ext-int16 { + eint16: ext-int16-pins { samsung,pins = "gpx2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - eint31: ext-int31 { + eint31: ext-int31-pins { samsung,pins = "gpx3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - fimc_is_i2c0: fimc-is-i2c0 { + fimc_is_i2c0: fimc-is-i2c0-pins { samsung,pins = "gpm4-0", "gpm4-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - fimc_is_i2c1: fimc-is-i2c1 { + fimc_is_i2c1: fimc-is-i2c1-pins { samsung,pins = "gpm4-2", "gpm4-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - fimc_is_uart: fimc-is-uart { + fimc_is_uart: fimc-is-uart-pins { samsung,pins = "gpm3-5", "gpm3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - hdmi_cec: hdmi-cec { + hdmi_cec: hdmi-cec-pins { samsung,pins = "gpx3-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -896,7 +896,7 @@ }; &pinctrl_2 { - gpz: gpz { + gpz: gpz-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -904,7 +904,7 @@ #interrupt-cells = <2>; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; @@ -912,7 +912,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pcm0_bus: pcm0-bus { + pcm0_bus: pcm0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -922,7 +922,7 @@ }; &pinctrl_3 { - gpv0: gpv0 { + gpv0: gpv0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -930,7 +930,7 @@ #interrupt-cells = <2>; }; - gpv1: gpv1 { + gpv1: gpv1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -938,7 +938,7 @@ #interrupt-cells = <2>; }; - gpv2: gpv2 { + gpv2: gpv2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -946,7 +946,7 @@ #interrupt-cells = <2>; }; - gpv3: gpv3 { + gpv3: gpv3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -954,7 +954,7 @@ #interrupt-cells = <2>; }; - gpv4: gpv4 { + gpv4: gpv4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -962,7 +962,7 @@ #interrupt-cells = <2>; }; - c2c_bus: c2c-bus { + c2c_bus: c2c-bus-pins { samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index cc99b955af0c..a40ff394977c 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -133,14 +133,14 @@ }; &pinctrl_1 { - keypad_rows: keypad-rows { + keypad_rows: keypad-rows-pins { samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - keypad_cols: keypad-cols { + keypad_cols: keypad-cols-pins { samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts index 017b26108bb0..04388c575efe 100644 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "exynos4412.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> / { model = "FriendlyARM TINY4412 board based on Exynos4412"; @@ -30,6 +31,7 @@ led1 { label = "led1"; + function = LED_FUNCTION_HEARTBEAT; gpios = <&gpm4 0 GPIO_ACTIVE_LOW>; default-state = "off"; linux,default-trigger = "heartbeat"; @@ -49,6 +51,7 @@ led4 { label = "led4"; + function = LED_FUNCTION_DISK_ACTIVITY; gpios = <&gpm4 3 GPIO_ACTIVE_LOW>; default-state = "off"; linux,default-trigger = "mmc0"; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index d3802046c8b8..aa0b61b59970 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -813,7 +813,7 @@ interrupt-parent = <&combiner>; interrupts = <2 4>; reg = <0x100C0000 0x100>; - clocks = <&clock 383>; + clocks = <&clock CLK_TMU_APBIF>; clock-names = "tmu_apbif"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 9ce9fb3fc190..c8da0d4b1b33 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -89,7 +89,7 @@ compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x10481000 0x1000>, + reg = <0x10481000 0x1000>, <0x10482000 0x2000>, <0x10484000 0x2000>, <0x10486000 0x2000>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 3583095fbb2a..71c0e87d3a1d 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -30,42 +30,42 @@ gpio-keys { compatible = "gpio-keys"; - menu { + key-menu { label = "SW-TACT2"; gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; wakeup-source; }; - home { + key-home { label = "SW-TACT3"; gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; wakeup-source; }; - up { + key-up { label = "SW-TACT4"; gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_UP>; wakeup-source; }; - down { + key-down { label = "SW-TACT5"; gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_DOWN>; wakeup-source; }; - back { + key-back { label = "SW-TACT6"; gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; wakeup-source; }; - wakeup { + key-wakeup { label = "SW-TACT7"; gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; @@ -590,7 +590,7 @@ }; &pinctrl_0 { - s5m8767_irq: s5m8767-irq { + s5m8767_irq: s5m8767-irq-pins { samsung,pins = "gpx3-2"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; @@ -632,3 +632,8 @@ #size-cells = <0>; }; }; + +&usbdrd { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index d31a68672bfa..48732edadff1 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -9,10 +9,10 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -20,7 +20,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -28,7 +28,7 @@ #interrupt-cells = <2>; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -36,7 +36,7 @@ #interrupt-cells = <2>; }; - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -44,7 +44,7 @@ #interrupt-cells = <2>; }; - gpb1: gpb1 { + gpb1: gpb1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -52,7 +52,7 @@ #interrupt-cells = <2>; }; - gpb2: gpb2 { + gpb2: gpb2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -60,7 +60,7 @@ #interrupt-cells = <2>; }; - gpb3: gpb3 { + gpb3: gpb3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -68,7 +68,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -76,7 +76,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -84,7 +84,7 @@ #interrupt-cells = <2>; }; - gpc2: gpc2 { + gpc2: gpc2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -92,7 +92,7 @@ #interrupt-cells = <2>; }; - gpc3: gpc3 { + gpc3: gpc3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -100,7 +100,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -108,7 +108,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -116,42 +116,42 @@ #interrupt-cells = <2>; }; - gpy0: gpy0 { + gpy0: gpy0-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy1: gpy1 { + gpy1: gpy1-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy2: gpy2 { + gpy2: gpy2-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy3: gpy3 { + gpy3: gpy3-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy4: gpy4 { + gpy4: gpy4-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy5: gpy5 { + gpy5: gpy5-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy6: gpy6 { + gpy6: gpy6-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpc4: gpc4 { + gpc4: gpc4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -159,7 +159,7 @@ #interrupt-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -170,7 +170,7 @@ <26 0>, <26 1>, <27 0>, <27 1>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -181,7 +181,7 @@ <30 0>, <30 1>, <31 0>, <31 1>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -189,7 +189,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -197,104 +197,104 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c2_hs_bus: i2c2-hs-bus { + i2c2_hs_bus: i2c2-hs-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c2_gpio_bus: i2c2-gpio-bus { + i2c2_gpio_bus: i2c2-gpio-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c3_bus: i2c3-bus { + i2c3_bus: i2c3-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c3_hs_bus: i2c3-hs-bus { + i2c3_hs_bus: i2c3-hs-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-4"; + uart3_data: uart3-data-pins { + samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c4_bus: i2c4-bus { + i2c4_bus: i2c4-bus-pins { samsung,pins = "gpa2-0", "gpa2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c5_bus: i2c5-bus { + i2c5_bus: i2c5-bus-pins { samsung,pins = "gpa2-2", "gpa2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; @@ -302,7 +302,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -310,7 +310,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - ac97_bus: ac97-bus { + ac97_bus: ac97-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; @@ -318,7 +318,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; @@ -326,7 +326,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pcm2_bus: pcm2-bus { + pcm2_bus: pcm2-bus-pins { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -334,280 +334,280 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spdif_bus: spdif-bus { + spdif_bus: spdif-bus-pins { samsung,pins = "gpb1-0", "gpb1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_5>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c6_bus: i2c6-bus { + i2c6_bus: i2c6-bus-pins { samsung,pins = "gpb1-3", "gpb1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpb2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpb2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpb2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpb2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c7_bus: i2c7-bus { + i2c7_bus: i2c7-bus-pins { samsung,pins = "gpb2-2", "gpb2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpb3-0", "gpb3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpb3-2", "gpb3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c0_hs_bus: i2c0-hs-bus { + i2c0_hs_bus: i2c0-hs-bus-pins { samsung,pins = "gpb3-0", "gpb3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - i2c1_hs_bus: i2c1-hs-bus { + i2c1_hs_bus: i2c1-hs-bus-pins { samsung,pins = "gpb3-2", "gpb3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpc0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpc0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpc0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpc0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpc2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpc2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpc2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpc2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpc3-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpc3-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpc3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd2_bus8: sd2-bus-width8 { + sd2_bus8: sd2-bus-width8-pins { samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_clk: sd3-clk { + sd3_clk: sd3-clk-pins { samsung,pins = "gpc4-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_cmd: sd3-cmd { + sd3_cmd: sd3-cmd-pins { samsung,pins = "gpc4-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_cd: sd3-cd { + sd3_cd: sd3-cd-pins { samsung,pins = "gpc4-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_bus1: sd3-bus-width1 { + sd3_bus1: sd3-bus-width1-pins { samsung,pins = "gpc4-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - sd3_bus4: sd3-bus-width4 { + sd3_bus4: sd3-bus-width4-pins { samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpd0-0", "gpd0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - dp_hpd: dp_hpd { + dp_hpd: dp-hpd-pins { samsung,pins = "gpx0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - hdmi_cec: hdmi-cec { + hdmi_cec: hdmi-cec-pins { samsung,pins = "gpx3-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - hdmi_hpd: hdmi-hpd { + hdmi_hpd: hdmi-hpd-pins { samsung,pins = "gpx3-7"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; }; &pinctrl_1 { - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -615,7 +615,7 @@ #interrupt-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -623,7 +623,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -631,7 +631,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -639,7 +639,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -647,7 +647,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -655,7 +655,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -663,7 +663,7 @@ #interrupt-cells = <2>; }; - gph0: gph0 { + gph0: gph0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -671,7 +671,7 @@ #interrupt-cells = <2>; }; - gph1: gph1 { + gph1: gph1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -679,7 +679,7 @@ #interrupt-cells = <2>; }; - cam_gpio_a: cam-gpio-a { + cam_gpio_a: cam-gpio-a-pins { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; @@ -688,7 +688,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_gpio_b: cam-gpio-b { + cam_gpio_b: cam-gpio-b-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -696,42 +696,42 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_i2c2_bus: cam-i2c2-bus { + cam_i2c2_bus: cam-i2c2-bus-pins { samsung,pins = "gpe0-6", "gpe1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_spi1_bus: cam-spi1-bus { + cam_spi1_bus: cam-spi1-bus-pins { samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_i2c1_bus: cam-i2c1-bus { + cam_i2c1_bus: cam-i2c1-bus-pins { samsung,pins = "gpf0-2", "gpf0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_i2c0_bus: cam-i2c0-bus { + cam_i2c0_bus: cam-i2c0-bus-pins { samsung,pins = "gpf0-0", "gpf0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_spi0_bus: cam-spi0-bus { + cam_spi0_bus: cam-spi0-bus-pins { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_bayrgb_bus: cam-bayrgb-bus { + cam_bayrgb_bus: cam-bayrgb-bus-pins { samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", @@ -742,7 +742,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - cam_port_a: cam-port-a { + cam_port_a: cam-port-a-pins { samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3", "gph1-0", "gph1-1", "gph1-2", "gph1-3", "gph1-4", "gph1-5", "gph1-6", "gph1-7"; @@ -753,7 +753,7 @@ }; &pinctrl_2 { - gpv0: gpv0 { + gpv0: gpv0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -761,7 +761,7 @@ #interrupt-cells = <2>; }; - gpv1: gpv1 { + gpv1: gpv1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -769,7 +769,7 @@ #interrupt-cells = <2>; }; - gpv2: gpv2 { + gpv2: gpv2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -777,7 +777,7 @@ #interrupt-cells = <2>; }; - gpv3: gpv3 { + gpv3: gpv3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -785,7 +785,7 @@ #interrupt-cells = <2>; }; - gpv4: gpv4 { + gpv4: gpv4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -793,7 +793,7 @@ #interrupt-cells = <2>; }; - c2c_rxd: c2c-rxd { + c2c_rxd: c2c-rxd-pins { samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", @@ -803,7 +803,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - c2c_txd: c2c-txd { + c2c_txd: c2c-txd-pins { samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", @@ -815,7 +815,7 @@ }; &pinctrl_3 { - gpz: gpz { + gpz: gpz-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -823,7 +823,7 @@ #interrupt-cells = <2>; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 39bbe18145cf..71293749ac48 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -118,6 +118,9 @@ status = "okay"; ddc = <&i2c_2>; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; }; &i2c_0 { @@ -126,7 +129,7 @@ samsung,i2c-max-bus-freq = <20000>; eeprom@50 { - compatible = "samsung,s524ad0xd1"; + compatible = "samsung,s524ad0xd1", "atmel,24c128"; reg = <0x50>; }; @@ -286,7 +289,7 @@ samsung,i2c-max-bus-freq = <20000>; eeprom@51 { - compatible = "samsung,s524ad0xd1"; + compatible = "samsung,s524ad0xd1", "atmel,24c128"; reg = <0x51>; }; @@ -410,10 +413,15 @@ }; &pinctrl_0 { - max77686_irq: max77686-irq { + max77686_irq: max77686-irq-pins { samsung,pins = "gpx3-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; }; + +&usbdrd { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index 2335c4687349..3d84b9c6dea3 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -32,7 +32,7 @@ pinctrl-names = "default"; pinctrl-0 = <&power_key_irq &lid_irq>; - power { + power-key { label = "Power"; gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -587,63 +587,63 @@ }; &pinctrl_0 { - wifi_en: wifi-en { + wifi_en: wifi-en-pins { samsung,pins = "gpx0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - wifi_rst: wifi-rst { + wifi_rst: wifi-rst-pins { samsung,pins = "gpx0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - power_key_irq: power-key-irq { + power_key_irq: power-key-irq-pins { samsung,pins = "gpx1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - ec_irq: ec-irq { + ec_irq: ec-irq-pins { samsung,pins = "gpx1-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - tps65090_irq: tps65090-irq { + tps65090_irq: tps65090-irq-pins { samsung,pins = "gpx2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - usb3_vbus_en: usb3-vbus-en { + usb3_vbus_en: usb3-vbus-en-pins { samsung,pins = "gpx2-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - max77686_irq: max77686-irq { + max77686_irq: max77686-irq-pins { samsung,pins = "gpx3-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lid_irq: lid-irq { + lid_irq: lid-irq-pins { samsung,pins = "gpx3-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; @@ -652,14 +652,14 @@ }; &pinctrl_1 { - arb_their_claim: arb-their-claim { + arb_their_claim: arb-their-claim-pins { samsung,pins = "gpe0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - arb_our_claim: arb-our-claim { + arb_our_claim: arb-our-claim-pins { samsung,pins = "gpf0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -698,6 +698,11 @@ cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; }; +&usbdrd { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + &usbdrd_dwc3 { dr_mode = "host"; }; diff --git a/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/exynos5250-snow-rev5.dts index f8ca61df6981..0a47597d6f0d 100644 --- a/arch/arm/boot/dts/exynos5250-snow-rev5.dts +++ b/arch/arm/boot/dts/exynos5250-snow-rev5.dts @@ -47,7 +47,7 @@ }; &pinctrl_0 { - max98090_irq: max98090-irq { + max98090_irq: max98090-irq-pins { samsung,pins = "gpx0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index a630bc654a49..906aa7aae710 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -43,7 +43,7 @@ }; &pinctrl_0 { - max98095_en: max98095-en { + max98095_en: max98095-en-pins { samsung,pins = "gpx1-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index e0feedcf54bb..5eca10ecd550 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -33,7 +33,7 @@ pinctrl-names = "default"; pinctrl-0 = <&power_key_irq>, <&lid_irq>; - power { + power-key { label = "Power"; gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -451,63 +451,63 @@ }; &pinctrl_0 { - s5m8767_dvs: s5m8767-dvs { + s5m8767_dvs: s5m8767-dvs-pins { samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - dp_hpd_gpio: dp-hpd { + dp_hpd_gpio: dp-hpd-pins { samsung,pins = "gpc3-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - trackpad_irq: trackpad-irq { + trackpad_irq: trackpad-irq-pins { samsung,pins = "gpx1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - power_key_irq: power-key-irq { + power_key_irq: power-key-irq-pins { samsung,pins = "gpx1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - ec_irq: ec-irq { + ec_irq: ec-irq-pins { samsung,pins = "gpx1-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - s5m8767_ds: s5m8767-ds { + s5m8767_ds: s5m8767-ds-pins { samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - s5m8767_irq: s5m8767-irq { + s5m8767_irq: s5m8767-irq-pins { samsung,pins = "gpx3-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - lid_irq: lid-irq { + lid_irq: lid-irq-pins { samsung,pins = "gpx3-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; @@ -516,7 +516,7 @@ }; &pinctrl_1 { - hsic_reset: hsic-reset { + hsic_reset: hsic-reset-pins { samsung,pins = "gpe1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -553,4 +553,9 @@ num-cs = <1>; }; +&usbdrd { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + #include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 139778928b93..4708dcd575a7 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -245,7 +245,8 @@ }; timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5250-mct", + "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; @@ -496,8 +497,7 @@ status = "disabled"; reg = <0x12d20000 0x100>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&pdma0 5 - &pdma0 4>; + dmas = <&pdma0 5>, <&pdma0 4>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; @@ -512,8 +512,7 @@ status = "disabled"; reg = <0x12d30000 0x100>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&pdma1 5 - &pdma1 4>; + dmas = <&pdma1 5>, <&pdma1 4>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; @@ -528,8 +527,7 @@ status = "disabled"; reg = <0x12d40000 0x100>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&pdma0 7 - &pdma0 6>; + dmas = <&pdma0 7>, <&pdma0 6>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; @@ -637,7 +635,7 @@ #sound-dai-cells = <1>; }; - usb_dwc3 { + usbdrd: usb3 { compatible = "samsung,exynos5250-dwusb3"; clocks = <&clock CLK_USB3>; clock-names = "usbdrd30"; @@ -695,48 +693,40 @@ samsung,pmureg-phandle = <&pmu_system_controller>; }; - pdma0: pdma@121a0000 { + pdma0: dma-controller@121a0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; - pdma1: pdma@121b0000 { + pdma1: dma-controller@121b0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; - mdma0: mdma@10800000 { + mdma0: dma-controller@10800000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; }; - mdma1: mdma@11c10000 { + mdma1: dma-controller@11c10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; }; gsc_0: gsc@13e00000 { @@ -820,15 +810,14 @@ status = "disabled"; }; - dp_phy: video-phy { + dp_phy: video-phy-0 { compatible = "samsung,exynos5250-dp-video-phy"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <0>; }; - mipi_phy: video-phy@10040710 { + mipi_phy: video-phy-1 { compatible = "samsung,s5pv210-mipi-video-phy"; - reg = <0x10040710 0x100>; #phy-cells = <1>; syscon = <&pmu_system_controller>; }; diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi index 17e2f3e0d71e..43e4a541f479 100644 --- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi @@ -9,10 +9,10 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -20,7 +20,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -28,7 +28,7 @@ #interrupt-cells = <2>; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -36,7 +36,7 @@ #interrupt-cells = <2>; }; - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -44,7 +44,7 @@ #interrupt-cells = <2>; }; - gpb1: gpb1 { + gpb1: gpb1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -52,7 +52,7 @@ #interrupt-cells = <2>; }; - gpb2: gpb2 { + gpb2: gpb2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -60,7 +60,7 @@ #interrupt-cells = <2>; }; - gpb3: gpb3 { + gpb3: gpb3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -68,7 +68,7 @@ #interrupt-cells = <2>; }; - gpb4: gpb4 { + gpb4: gpb4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -76,7 +76,7 @@ #interrupt-cells = <2>; }; - gpb5: gpb5 { + gpb5: gpb5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -84,7 +84,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -92,7 +92,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -100,7 +100,7 @@ #interrupt-cells = <2>; }; - gpd2: gpd2 { + gpd2: gpd2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -108,7 +108,7 @@ #interrupt-cells = <2>; }; - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -116,7 +116,7 @@ #interrupt-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -124,7 +124,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -132,7 +132,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -140,7 +140,7 @@ #interrupt-cells = <2>; }; - gpk0: gpk0 { + gpk0: gpk0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -148,7 +148,7 @@ #interrupt-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -164,7 +164,7 @@ #interrupt-cells = <2>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -180,7 +180,7 @@ #interrupt-cells = <2>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -188,7 +188,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -196,63 +196,63 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - usb3_vbus0_en: usb3-vbus0-en { + usb3_vbus0_en: usb3-vbus0-en-pins { samsung,pins = "gpa2-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; @@ -260,7 +260,7 @@ samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -268,105 +268,105 @@ samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - spdif1_bus: spdif1-bus { + spdif1_bus: spdif1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2c0_hs_bus: i2c0-hs-bus { + i2c0_hs_bus: i2c0-hs-bus-pins { samsung,pins = "gpb3-0", "gpb3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2c1_hs_bus: i2c1-hs-bus { + i2c1_hs_bus: i2c1-hs-bus-pins { samsung,pins = "gpb3-2", "gpb3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2c2_hs_bus: i2c2-hs-bus { + i2c2_hs_bus: i2c2-hs-bus-pins { samsung,pins = "gpb3-4", "gpb3-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2c3_hs_bus: i2c3-hs-bus { + i2c3_hs_bus: i2c3-hs-bus-pins { samsung,pins = "gpb3-6", "gpb3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2c4_bus: i2c4-bus { + i2c4_bus: i2c4-bus-pins { samsung,pins = "gpb4-0", "gpb4-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2c5_bus: i2c5-bus { + i2c5_bus: i2c5-bus-pins { samsung,pins = "gpb4-2", "gpb4-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2c6_bus: i2c6-bus { + i2c6_bus: i2c6-bus-pins { samsung,pins = "gpb4-4", "gpb4-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2c7_bus: i2c7-bus { + i2c7_bus: i2c7-bus-pins { samsung,pins = "gpb4-6", "gpb4-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2c8_bus: i2c8-bus { + i2c8_bus: i2c8-bus-pins { samsung,pins = "gpb5-0", "gpb5-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2c9_bus: i2c9-bus { + i2c9_bus: i2c9-bus-pins { samsung,pins = "gpb5-2", "gpb5-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2c10_bus: i2c10-bus { + i2c10_bus: i2c10-bus-pins { samsung,pins = "gpb5-4", "gpb5-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - i2c11_bus: i2c11-bus { + i2c11_bus: i2c11-bus-pins { samsung,pins = "gpb5-6", "gpb5-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - cam_gpio_a: cam-gpio-a { + cam_gpio_a: cam-gpio-a-pins { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; @@ -375,7 +375,7 @@ samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - cam_gpio_b: cam-gpio-b { + cam_gpio_b: cam-gpio-b-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -383,28 +383,28 @@ samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - cam_i2c1_bus: cam-i2c1-bus { + cam_i2c1_bus: cam-i2c1-bus-pins { samsung,pins = "gpf0-2", "gpf0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - cam_i2c0_bus: cam-i2c0-bus { + cam_i2c0_bus: cam-i2c0-bus-pins { samsung,pins = "gpf0-0", "gpf0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - cam_spi0_bus: cam-spi0-bus { + cam_spi0_bus: cam-spi0-bus-pins { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; }; - cam_spi1_bus: cam-spi1-bus { + cam_spi1_bus: cam-spi1-bus-pins { samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -413,7 +413,7 @@ }; &pinctrl_1 { - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -421,7 +421,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -429,7 +429,7 @@ #interrupt-cells = <2>; }; - gpc2: gpc2 { + gpc2: gpc2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -437,7 +437,7 @@ #interrupt-cells = <2>; }; - gpc3: gpc3 { + gpc3: gpc3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -445,7 +445,7 @@ #interrupt-cells = <2>; }; - gpc4: gpc4 { + gpc4: gpc4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -453,112 +453,112 @@ #interrupt-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpc0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpc0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpc0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd0_rdqs: sd0-rdqs { + sd0_rdqs: sd0-rdqs-pins { samsung,pins = "gpc0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpc1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpc1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpc1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd1_bus8: sd1-bus-width8 { + sd1_bus8: sd1-bus-width8-pins { samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpc2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpc2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpc2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV6>; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; @@ -567,7 +567,7 @@ }; &pinctrl_2 { - gpz0: gpz0 { + gpz0: gpz0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -575,7 +575,7 @@ #interrupt-cells = <2>; }; - gpz1: gpz1 { + gpz1: gpz1-gpio-bank { gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index 0dc2ec16aa0a..3c3b751d4360 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -29,6 +29,27 @@ #clock-cells = <0>; }; + ioclk_pcm: clock-pcm-ext { + compatible = "fixed-clock"; + clock-frequency = <2048000>; + clock-output-names = "ioclk_pcm_extclk"; + #clock-cells = <0>; + }; + + ioclk_i2s: clock-i2s-cd { + compatible = "fixed-clock"; + clock-frequency = <147456000>; + clock-output-names = "ioclk_i2s_cdclk"; + #clock-cells = <0>; + }; + + ioclk_spdif: clock-spdif-ext { + compatible = "fixed-clock"; + clock-frequency = <49152000>; + clock-output-names = "ioclk_spdif_extclk"; + #clock-cells = <0>; + }; + xrtcxti: xrtcxti { compatible = "fixed-clock"; clock-frequency = <32768>; @@ -38,7 +59,7 @@ }; &pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 524d244050e0..ff1ee409eff3 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -113,78 +113,206 @@ compatible = "samsung,exynos5260-clock-top"; reg = <0x10010000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_mif MIF_DOUT_MEM_PLL>, + <&clock_mif MIF_DOUT_BUS_PLL>, + <&clock_mif MIF_DOUT_MEDIA_PLL>; + clock-names = "fin_pll", + "dout_mem_pll", + "dout_bus_pll", + "dout_media_pll"; }; clock_peri: clock-controller@10200000 { compatible = "samsung,exynos5260-clock-peri"; reg = <0x10200000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&ioclk_pcm>, + <&ioclk_i2s>, + <&ioclk_spdif>, + <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_PERI_66>, + <&clock_top TOP_DOUT_SCLK_PERI_UART0>, + <&clock_top TOP_DOUT_SCLK_PERI_UART1>, + <&clock_top TOP_DOUT_SCLK_PERI_UART2>, + <&clock_top TOP_DOUT_SCLK_PERI_SPI0_B>, + <&clock_top TOP_DOUT_SCLK_PERI_SPI1_B>, + <&clock_top TOP_DOUT_SCLK_PERI_SPI2_B>, + <&clock_top TOP_DOUT_ACLK_PERI_AUD>; + clock-names = "fin_pll", + "ioclk_pcm_extclk", + "ioclk_i2s_cdclk", + "ioclk_spdif_extclk", + "phyclk_hdmi_phy_ref_cko", + "dout_aclk_peri_66", + "dout_sclk_peri_uart0", + "dout_sclk_peri_uart1", + "dout_sclk_peri_uart2", + "dout_sclk_peri_spi0_b", + "dout_sclk_peri_spi1_b", + "dout_sclk_peri_spi2_b", + "dout_aclk_peri_aud"; }; clock_egl: clock-controller@10600000 { compatible = "samsung,exynos5260-clock-egl"; reg = <0x10600000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_mif MIF_DOUT_BUS_PLL>; + clock-names = "fin_pll", + "dout_bus_pll"; }; clock_kfc: clock-controller@10700000 { compatible = "samsung,exynos5260-clock-kfc"; reg = <0x10700000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_mif MIF_DOUT_MEDIA_PLL>; + clock-names = "fin_pll", + "dout_media_pll"; }; clock_g2d: clock-controller@10a00000 { compatible = "samsung,exynos5260-clock-g2d"; reg = <0x10A00000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_G2D_333>; + clock-names = "fin_pll", + "dout_aclk_g2d_333"; }; clock_mif: clock-controller@10ce0000 { compatible = "samsung,exynos5260-clock-mif"; reg = <0x10CE0000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; }; clock_mfc: clock-controller@11090000 { compatible = "samsung,exynos5260-clock-mfc"; reg = <0x11090000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_MFC_333>; + clock-names = "fin_pll", + "dout_aclk_mfc_333"; }; clock_g3d: clock-controller@11830000 { compatible = "samsung,exynos5260-clock-g3d"; reg = <0x11830000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; }; clock_fsys: clock-controller@122e0000 { compatible = "samsung,exynos5260-clock-fsys"; reg = <0x122E0000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_FSYS_200>; + clock-names = "fin_pll", + "phyclk_usbhost20_phy_phyclock", + "phyclk_usbhost20_phy_freeclk", + "phyclk_usbhost20_phy_clk48mohci", + "phyclk_usbdrd30_udrd30_pipe_pclk", + "phyclk_usbdrd30_udrd30_phyclock", + "dout_aclk_fsys_200"; }; clock_aud: clock-controller@128c0000 { compatible = "samsung,exynos5260-clock-aud"; reg = <0x128C0000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_FOUT_AUD_PLL>, + <&ioclk_i2s>, + <&ioclk_pcm>; + clock-names = "fin_pll", + "fout_aud_pll", + "ioclk_i2s_cdclk", + "ioclk_pcm_extclk"; }; clock_isp: clock-controller@133c0000 { compatible = "samsung,exynos5260-clock-isp"; reg = <0x133C0000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_ISP1_266>, + <&clock_top TOP_DOUT_ACLK_ISP1_400>, + <&clock_top TOP_MOUT_ACLK_ISP1_266>; + clock-names = "fin_pll", + "dout_aclk_isp1_266", + "dout_aclk_isp1_400", + "mout_aclk_isp1_266"; }; clock_gscl: clock-controller@13f00000 { compatible = "samsung,exynos5260-clock-gscl"; reg = <0x13F00000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_GSCL_400>, + <&clock_top TOP_DOUT_ACLK_GSCL_333>; + clock-names = "fin_pll", + "dout_aclk_gscl_400", + "dout_aclk_gscl_333"; }; clock_disp: clock-controller@14550000 { compatible = "samsung,exynos5260-clock-disp"; reg = <0x14550000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&ioclk_spdif>, + <&clock_top TOP_DOUT_ACLK_PERI_AUD>, + <&clock_top TOP_DOUT_ACLK_DISP_222>, + <&clock_top TOP_DOUT_SCLK_DISP_PIXEL>, + <&clock_top TOP_DOUT_ACLK_DISP_333>; + clock-names = "fin_pll", + "phyclk_dptx_phy_ch3_txd_clk", + "phyclk_dptx_phy_ch2_txd_clk", + "phyclk_dptx_phy_ch1_txd_clk", + "phyclk_dptx_phy_ch0_txd_clk", + "phyclk_hdmi_phy_tmds_clko", + "phyclk_hdmi_phy_ref_clko", + "phyclk_hdmi_phy_pixel_clko", + "phyclk_hdmi_link_o_tmds_clkhi", + "phyclk_mipi_dphy_4l_m_txbyte_clkhs", + "phyclk_dptx_phy_o_ref_clk_24m", + "phyclk_dptx_phy_clk_div2", + "phyclk_mipi_dphy_4l_m_rxclkesc0", + "phyclk_hdmi_phy_ref_cko", + "ioclk_spdif_extclk", + "dout_aclk_peri_aud", + "dout_aclk_disp_222", + "dout_sclk_disp_pixel", + "dout_aclk_disp_333"; }; gic: interrupt-controller@10481000 { @@ -205,7 +333,8 @@ }; mct: timer@100b0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5260-mct", + "samsung,exynos4210-mct"; reg = <0x100B0000 0x1000>; clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; clock-names = "fin_pll", "mct"; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 884fef55836c..d1cbc6b8a570 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -188,8 +188,7 @@ interrupt-parent = <&gpx0>; interrupts = <4 IRQ_TYPE_NONE>; pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>, - <&pmic_dvs_3>; + pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>; wakeup-source; #clock-cells = <1>; @@ -394,10 +393,6 @@ regulator-always-on; }; - ldo16_reg: LDO16 { - regulator-name = "ldo16"; - }; - ldo17_reg: LDO17 { regulator-name = "cam_sensor_core"; regulator-min-microvolt = <1200000>; @@ -427,10 +422,6 @@ regulator-max-microvolt = <2850000>; }; - ldo22_reg: LDO22 { - regulator-name = "ldo22"; - }; - ldo23_reg: LDO23 { regulator-name = "dp_p3v3"; regulator-min-microvolt = <3300000>; @@ -477,10 +468,6 @@ regulator-always-on; }; - ldo31_reg: LDO31 { - regulator-name = "ldo31"; - }; - /* On revisions with ti,ina231 this is sensor VS */ ldo32_reg: LDO32 { regulator-name = "vs_power_meter"; @@ -548,14 +535,14 @@ }; &pinctrl_0 { - emmc_nrst_pin: emmc-nrst { + emmc_nrst_pin: emmc-nrst-pins { samsung,pins = "gpd1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - sd2_wp: sd2-wp { + sd2_wp: sd2-wp-pins { samsung,pins = "gpm5-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; /* Pin is floating so be sure to disable write-protect */ @@ -563,21 +550,14 @@ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpx0-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; - }; - - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpx0-1"; + pmic_dvs_2: pmic-dvs-2-pins { + samsung,pins = "gpx0-0", "gpx0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pmic_dvs_1: pmic-dvs-1 { + pmic_dvs_1: pmic-dvs-1-pins { samsung,pins = "gpx0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -585,7 +565,7 @@ samsung,pin-val = <1>; }; - max77802_irq: max77802-irq { + max77802_irq: max77802-irq-pins { samsung,pins = "gpx0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -675,8 +655,8 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@2 { - compatible = "usb0424,9730"; + ethernet: ethernet@2 { + compatible = "usb424,9730"; reg = <2>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index 9599ba8ba798..f7b923382892 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -6,10 +6,10 @@ * https://www.hardkernel.com */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -17,7 +17,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -25,7 +25,7 @@ #interrupt-cells = <2>; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -33,7 +33,7 @@ #interrupt-cells = <2>; }; - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -41,7 +41,7 @@ #interrupt-cells = <2>; }; - gpb1: gpb1 { + gpb1: gpb1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -49,7 +49,7 @@ #interrupt-cells = <2>; }; - gpb2: gpb2 { + gpb2: gpb2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -57,7 +57,7 @@ #interrupt-cells = <2>; }; - gpb3: gpb3 { + gpb3: gpb3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -65,7 +65,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -73,7 +73,7 @@ #interrupt-cells = <2>; }; - gpc3: gpc3 { + gpc3: gpc3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -81,7 +81,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -89,7 +89,7 @@ #interrupt-cells = <2>; }; - gpc2: gpc2 { + gpc2: gpc2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -97,12 +97,12 @@ #interrupt-cells = <2>; }; - gpm5: gpm5 { + gpm5: gpm5-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -110,7 +110,7 @@ #interrupt-cells = <2>; }; - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -118,7 +118,7 @@ #interrupt-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -126,7 +126,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -134,7 +134,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -142,7 +142,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -150,7 +150,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -158,7 +158,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -166,7 +166,7 @@ #interrupt-cells = <2>; }; - gph0: gph0 { + gph0: gph0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -174,7 +174,7 @@ #interrupt-cells = <2>; }; - gph1: gph1 { + gph1: gph1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -182,52 +182,52 @@ #interrupt-cells = <2>; }; - gpm7: gpm7 { + gpm7: gpm7-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy0: gpy0 { + gpy0: gpy0-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy1: gpy1 { + gpy1: gpy1-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy2: gpy2 { + gpy2: gpy2-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy3: gpy3 { + gpy3: gpy3-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy4: gpy4 { + gpy4: gpy4-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy5: gpy5 { + gpy5: gpy5-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy6: gpy6 { + gpy6: gpy6-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy7: gpy7 { + gpy7: gpy7-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -244,7 +244,7 @@ <27 1>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -261,7 +261,7 @@ <31 1>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -269,7 +269,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -277,210 +277,210 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c3_bus: i2c3-bus { + i2c3_bus: i2c3-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c4_hs_bus: i2c4-hs-bus { + i2c4_hs_bus: i2c4-hs-bus-pins { samsung,pins = "gpa2-0", "gpa2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c5_hs_bus: i2c5-hs-bus { + i2c5_hs_bus: i2c5-hs-bus-pins { samsung,pins = "gpa2-2", "gpa2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c6_hs_bus: i2c6-hs-bus { + i2c6_hs_bus: i2c6-hs-bus-pins { samsung,pins = "gpb1-3", "gpb1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpb2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpb2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpb2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpb2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c7_hs_bus: i2c7-hs-bus { + i2c7_hs_bus: i2c7-hs-bus-pins { samsung,pins = "gpb2-2", "gpb2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpb3-0", "gpb3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpb3-2", "gpb3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpc0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpc0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpc0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpc0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpc2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpc2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpc2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; @@ -489,7 +489,7 @@ }; &pinctrl_1 { - gpj0: gpj0 { + gpj0: gpj0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -497,7 +497,7 @@ #interrupt-cells = <2>; }; - gpj1: gpj1 { + gpj1: gpj1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -505,7 +505,7 @@ #interrupt-cells = <2>; }; - gpj2: gpj2 { + gpj2: gpj2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -513,7 +513,7 @@ #interrupt-cells = <2>; }; - gpj3: gpj3 { + gpj3: gpj3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -521,7 +521,7 @@ #interrupt-cells = <2>; }; - gpj4: gpj4 { + gpj4: gpj4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -529,7 +529,7 @@ #interrupt-cells = <2>; }; - gpk0: gpk0 { + gpk0: gpk0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -537,7 +537,7 @@ #interrupt-cells = <2>; }; - gpk1: gpk1 { + gpk1: gpk1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -545,7 +545,7 @@ #interrupt-cells = <2>; }; - gpk2: gpk2 { + gpk2: gpk2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -553,7 +553,7 @@ #interrupt-cells = <2>; }; - gpk3: gpk3 { + gpk3: gpk3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -561,28 +561,28 @@ #interrupt-cells = <2>; }; - usb3_1_oc: usb3-1-oc { + usb3_1_oc: usb3-1-oc-pins { samsung,pins = "gpk2-4", "gpk2-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - usb3_1_vbusctrl: usb3-1-vbusctrl { + usb3_1_vbusctrl: usb3-1-vbusctrl-pins { samsung,pins = "gpk2-6", "gpk2-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - usb3_0_oc: usb3-0-oc { + usb3_0_oc: usb3-0-oc-pins { samsung,pins = "gpk3-0", "gpk3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - usb3_0_vbusctrl: usb3-0-vbusctrl { + usb3_0_vbusctrl: usb3-0-vbusctrl-pins { samsung,pins = "gpk3-2", "gpk3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; @@ -591,7 +591,7 @@ }; &pinctrl_2 { - gpv0: gpv0 { + gpv0: gpv0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -599,7 +599,7 @@ #interrupt-cells = <2>; }; - gpv1: gpv1 { + gpv1: gpv1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -607,7 +607,7 @@ #interrupt-cells = <2>; }; - gpv2: gpv2 { + gpv2: gpv2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -615,7 +615,7 @@ #interrupt-cells = <2>; }; - gpv3: gpv3 { + gpv3: gpv3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -623,7 +623,7 @@ #interrupt-cells = <2>; }; - gpv4: gpv4 { + gpv4: gpv4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -633,7 +633,7 @@ }; &pinctrl_3 { - gpz: gpz { + gpz: gpz-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -641,7 +641,7 @@ #interrupt-cells = <2>; }; - audi2s0_bus: audi2s0-bus { + audi2s0_bus: audi2s0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4"; samsung,pin-function = <2>; diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 2a3ade77a2de..b8f953c41c73 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -41,6 +41,19 @@ reg = <0x02037000 0x1000>; }; + vdd10_usb3: voltage-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VDD10_USB3"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vdd33_usb3: voltage-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VDD33_USB3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &mmc_0 { @@ -66,14 +79,14 @@ }; &pinctrl_0 { - srom_ctl: srom-ctl { + srom_ctl: srom-ctl-pins { samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5", "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - srom_ebi: srom-ebi { + srom_ebi: srom-ebi-pins { samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3", "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7", "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3", @@ -121,3 +134,13 @@ &serial_2 { status = "okay"; }; + +&usbdrd3_0 { + vdd10-supply = <&vdd10_usb3>; + vdd33-supply = <&vdd33_usb3>; +}; + +&usbdrd3_1 { + vdd10-supply = <&vdd10_usb3>; + vdd33-supply = <&vdd33_usb3>; +}; diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 584ce62361b1..8a6b890fb8f7 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -189,26 +189,22 @@ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; }; - pdma0: pdma@121a0000 { + pdma0: dma-controller@121a0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121a0000 0x1000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; - pdma1: pdma@121b0000 { + pdma1: dma-controller@121b0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121b0000 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; audi2s0: i2s@3830000 { diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index dfc7f14f5772..55b7759682a9 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -42,7 +42,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "SW-TACT1"; gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; @@ -808,7 +808,7 @@ }; &pinctrl_0 { - s2mps11_irq: s2mps11-irq { + s2mps11_irq: s2mps11-irq-pins { samsung,pins = "gpx3-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -825,3 +825,13 @@ &usbdrd_dwc3_1 { dr_mode = "host"; }; + +&usbdrd3_0 { + vdd10-supply = <&ldo11_reg>; + vdd33-supply = <&ldo9_reg>; +}; + +&usbdrd3_1 { + vdd10-supply = <&ldo11_reg>; + vdd33-supply = <&ldo9_reg>; +}; diff --git a/arch/arm/boot/dts/exynos5420-chagall-wifi.dts b/arch/arm/boot/dts/exynos5420-chagall-wifi.dts new file mode 100644 index 000000000000..1319344a2c74 --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-chagall-wifi.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos5420 Chagall WiFi board device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Henrik Grimler + */ + +/dts-v1/; +#include "exynos5420-galaxy-tab-common.dtsi" + +/ { + model = "Samsung Chagall WiFi based on Exynos5420"; + compatible = "samsung,chagall-wifi", "samsung,exynos5420", \ + "samsung,exynos5"; +}; + +&ldo15_reg { + /* Unused */ + regulator-name = "VDD_LDO15"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&ldo17_reg { + regulator-name = "VDD_IRLED_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo28_reg { + /* Unused */ + regulator-name = "VDD_LDO28"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&ldo29_reg { + regulator-name = "VDD_TCON_1V8"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo31_reg { + regulator-name = "VDD_GRIP_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo32_reg { + regulator-name = "VDD_TSP_1V8"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; diff --git a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi new file mode 100644 index 000000000000..d19bc3d266fa --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Base DT for Samsung's family of tablets based on Exynos5420. + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Henrik Grimler + */ + +/dts-v1/; +#include "exynos5420.dtsi" +#include "exynos5420-cpus.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/samsung,s2mps11.h> + +/ { + chassis-type = "tablet"; + + /* + * To successfully boot the mainline kernel with the stock + * bootloader (SBOOT), the tlb needs to be flushed after the + * page table pointer has been updated in __common_mmu_cache_on. + * The same hack is also needed to boot exynos4412-i9300 with + * stock bootloader, and probably other Samsung devices of + * similar age. See + * https://lore.kernel.org/all/1355276466-18295-1-git-send-email-arve@android.com + * for more details. + */ + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0xc0000000>; + }; + + firmware@2073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + + key-power { + debounce-interval = <10>; + gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; + label = "Power"; + linux,code = <KEY_POWER>; + wakeup-source; + }; + + key-home { + debounce-interval = <10>; + gpios = <&gpx0 5 GPIO_ACTIVE_LOW>; + label = "Home"; + linux,code = <KEY_HOME>; + wakeup-source; + }; + + key-volume-up { + debounce-interval = <10>; + gpios = <&gpx0 2 GPIO_ACTIVE_LOW>; + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + }; + + key-volume-down { + debounce-interval = <10>; + gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; +}; + +&cci { + /* CCI is disabled in hardware */ + status = "disabled"; +}; + +&cpu0 { + cpu-supply = <&buck2_reg>; +}; + +&cpu4 { + cpu-supply = <&buck6_reg>; +}; + +&gpu { + status = "okay"; + mali-supply = <&buck4_reg>; +}; + +&hsi2c_7 { + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + + s2mps11_osc: clocks { + compatible = "samsung,s2mps11-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", "s2mps11_cp", + "s2mps11_bt"; + }; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF_1V1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D_1V0"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDD_MEM_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + buck6_reg: BUCK6 { + regulator-name = "VDD_KFC_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck7_reg: BUCK7 { + regulator-name = "VIN_LLDO_1V4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "VIN_MLDO_2V0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "VIN_HLDO_3V5"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "VDD_CAM_ISP_1V0"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3550000>; + }; + + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_APIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDD_APIO_MMC01_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_ADC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + /* Unused */ + regulator-name = "VDD_LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD_MIPI_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_MIPI_PLL_ABB1_18V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + /* Unused */ + regulator-name = "VDD_LDO8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD_UOTG_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDDQ_PRE_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_HSIC_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD_HSIC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDD_APIO_MMC2_2V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD_MOTOR_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD_LDO15"; + /* + * LDO15 varies between devices and is + * specified in the device dts + */ + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD_AP_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "VDD_LDO17"; + /* + * LDO17 varies between devices and is + * specified in the device dts + */ + }; + + ldo18_reg: LDO18 { + /* Unused */ + regulator-name = "VDD_LDO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "VDD_VTF_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo20_reg: LDO20 { + regulator-name = "VDD_CAM1_CAM_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD_CAM_IO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo22_reg: LDO22 { + regulator-name = "VDD_CAM0_S_CORE_1V1"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo23_reg: LDO23 { + regulator-name = "VDD_MIFS_1V1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo24_reg: LDO24 { + regulator-name = "VDD_TSP_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo25_reg: LDO25 { + /* Unused */ + regulator-name = "VDD_LDO25"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "VDD_CAM0_AF_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo27_reg: LDO27 { + regulator-name = "VDD_G3DS_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo28_reg: LDO28 { + regulator-name = "VDD_LDO28"; + /* + * LDO28 varies between devices and is + * specified in the device dts + */ + }; + + ldo29_reg: LDO29 { + regulator-name = "VDD_LDO29"; + /* + * LDO29 varies between devices and is + * specified in the device dts + */ + }; + + ldo30_reg: LDO30 { + regulator-name = "VDD_TOUCH_1V8"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo31_reg: LDO31 { + regulator-name = "VDD_LDO31"; + /* + * LDO31 varies between devices and is + * specified in the device dts + */ + }; + + ldo32_reg: LDO32 { + regulator-name = "VDD_LDO32"; + /* + * LDO32 varies between devices and is + * specified in the device dts + */ + }; + + ldo33_reg: LDO33 { + regulator-name = "VDD_MHL_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo34_reg: LDO34 { + regulator-name = "VDD_MHL_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo35_reg: LDO35 { + regulator-name = "VDD_SIL_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo36_reg: LDO36 { + /* Unused */ + regulator-name = "VDD_LDO36"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo37_reg: LDO37 { + /* Unused */ + regulator-name = "VDD_LDO37"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo38_reg: LDO38 { + regulator-name = "VDD_KEY_LED_3V3"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mixer { + status = "okay"; +}; + +/* Internal storage */ +&mmc_0 { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + card-detect-delay = <200>; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-names = "default"; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-sdr-timing = <0 4>; + vqmmc-supply = <&ldo3_reg>; +}; + +/* External sdcard */ +&mmc_2 { + status = "okay"; + bus-width = <4>; + cap-sd-highspeed; + card-detect-delay = <200>; + cd-gpios = <&gpx2 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sd2_clk &sd2_cmd &mmc2_cd &sd2_bus1 &sd2_bus4>; + pinctrl-names = "default"; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-sdr-timing = <0 4>; + sd-uhs-sdr50; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>; +}; + +&pinctrl_0 { + mmc2_cd: mmc2-cd-pins { + samsung,pins = "gpx2-4"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + s2mps11_irq: s2mps11-irq-pins { + samsung,pins = "gpx3-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo10_reg>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "peripheral"; +}; + +&usbdrd3_0 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; + +&usbdrd3_1 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; diff --git a/arch/arm/boot/dts/exynos5420-klimt-wifi.dts b/arch/arm/boot/dts/exynos5420-klimt-wifi.dts new file mode 100644 index 000000000000..011787b1bbf0 --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-klimt-wifi.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos5420 Klimt WiFi board device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Henrik Grimler + */ + +/dts-v1/; +#include "exynos5420-galaxy-tab-common.dtsi" + +/ { + model = "Samsung Klimt WiFi based on Exynos5420"; + compatible = "samsung,klimt-wifi", "samsung,exynos5420", \ + "samsung,exynos5"; +}; + +&ldo15_reg { + /* Unused */ + regulator-name = "VDD_LDO15"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&ldo17_reg { + regulator-name = "VDD_VCI_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo28_reg { + regulator-name = "VDD3_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo29_reg { + regulator-name = "VDDR_1V6"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1600000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo31_reg { + /* Unused */ + regulator-name = "VDD_LDO31"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&ldo32_reg { + regulator-name = "VDD_TSP_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&mmc_2 { + sd-uhs-sdr104; +}; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index e76fb104db19..9e2123470cad 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -60,7 +60,7 @@ pinctrl-names = "default"; pinctrl-0 = <&power_key_irq &lid_irq>; - power { + power-key { label = "Power"; gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -212,7 +212,7 @@ interrupts = <1 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&max77802_irq>, <&pmic_selb>, - <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; + <&pmic_dvs_1>, <&pmic_dvs_2>; wakeup-source; reg = <0x9>; #clock-cells = <1>; @@ -774,14 +774,14 @@ pinctrl-names = "default"; pinctrl-0 = <&mask_tpm_reset>; - wifi_en: wifi-en { + wifi_en: wifi-en-pins { samsung,pins = "gpx0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - max98090_irq: max98090-irq { + max98090_irq: max98090-irq-pins { samsung,pins = "gpx0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -789,7 +789,7 @@ }; /* We need GPX0_6 to be low at sleep time; just keep it low always */ - mask_tpm_reset: mask-tpm-reset { + mask_tpm_reset: mask-tpm-reset-pins { samsung,pins = "gpx0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -797,70 +797,70 @@ samsung,pin-val = <0>; }; - tpm_irq: tpm-irq { + tpm_irq: tpm-irq-pins { samsung,pins = "gpx1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - trackpad_irq: trackpad-irq { + trackpad_irq: trackpad-irq-pins { samsung,pins = "gpx1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - power_key_irq: power-key-irq { + power_key_irq: power-key-irq-pins { samsung,pins = "gpx1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - ec_irq: ec-irq { + ec_irq: ec-irq-pins { samsung,pins = "gpx1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - tps65090_irq: tps65090-irq { + tps65090_irq: tps65090-irq-pins { samsung,pins = "gpx2-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - dp_hpd_gpio: dp_hpd_gpio { + dp_hpd_gpio: dp-hpd-gpio-pins { samsung,pins = "gpx2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - max77802_irq: max77802-irq { + max77802_irq: max77802-irq-pins { samsung,pins = "gpx3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - lid_irq: lid-irq { + lid_irq: lid-irq-pins { samsung,pins = "gpx3-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pmic_dvs_1: pmic-dvs-1 { + pmic_dvs_1: pmic-dvs-1-pins { samsung,pins = "gpy7-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -868,74 +868,67 @@ }; }; -&pinctrl_1 { - /* Adjust WiFi drive strengths lower for EMI */ - sd1_clk: sd1-clk { - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; - }; +/* pinctrl_1 */ +/* Adjust WiFi drive strengths lower for EMI */ +&sd1_bus1 { + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; +}; - sd1_cmd: sd1-cmd { - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; - }; +&sd1_bus4 { + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; +}; - sd1_bus1: sd1-bus-width1 { - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; - }; +&sd1_bus8 { + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; +}; - sd1_bus4: sd1-bus-width4 { - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; - }; +&sd1_clk { + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; +}; - sd1_bus8: sd1-bus-width8 { - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; - }; +&sd1_cmd { + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; &pinctrl_2 { - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpj4-2"; + pmic_dvs_2: pmic-dvs-2-pins { + samsung,pins = "gpj4-2", "gpj4-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; +}; - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpj4-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; - }; +/* pinctrl_3*/ +/* Drive SPI lines at x2 for better integrity */ +&spi2_bus { + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; &pinctrl_3 { - /* Drive SPI lines at x2 for better integrity */ - spi2-bus { - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; - }; - /* Drive SPI chip select at x2 for better integrity */ - ec_spi_cs: ec-spi-cs { + ec_spi_cs: ec-spi-cs-pins { samsung,pins = "gpb1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; - usb300_vbus_en: usb300-vbus-en { + usb300_vbus_en: usb300-vbus-en-pins { samsung,pins = "gph0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - usb301_vbus_en: usb301-vbus-en { + usb301_vbus_en: usb301-vbus-en-pins { samsung,pins = "gph0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pmic_selb: pmic-selb { + pmic_selb: pmic-selb-pins { samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", "gph0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; @@ -1090,6 +1083,16 @@ vtmu-supply = <&ldo10_reg>; }; +&usbdrd3_0 { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + +&usbdrd3_1 { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index b82af7c89654..14cf9c4ca0ed 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -9,10 +9,10 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_0 { - gpy7: gpy7 { + gpy7: gpy7-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -20,7 +20,7 @@ #interrupt-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -31,7 +31,7 @@ <26 0>, <26 1>, <27 0>, <27 1>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -42,7 +42,7 @@ <30 0>, <30 1>, <31 0>, <31 1>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -50,7 +50,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -58,14 +58,14 @@ #interrupt-cells = <2>; }; - dp_hpd: dp_hpd { + dp_hpd: dp-hpd-pins { samsung,pins = "gpx0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - hdmi_cec: hdmi-cec { + hdmi_cec: hdmi-cec-pins { samsung,pins = "gpx3-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -74,7 +74,7 @@ }; &pinctrl_1 { - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -82,7 +82,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -90,7 +90,7 @@ #interrupt-cells = <2>; }; - gpc2: gpc2 { + gpc2: gpc2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -98,7 +98,7 @@ #interrupt-cells = <2>; }; - gpc3: gpc3 { + gpc3: gpc3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -106,7 +106,7 @@ #interrupt-cells = <2>; }; - gpc4: gpc4 { + gpc4: gpc4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -114,7 +114,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -122,175 +122,175 @@ #interrupt-cells = <2>; }; - gpy0: gpy0 { + gpy0: gpy0-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy1: gpy1 { + gpy1: gpy1-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy2: gpy2 { + gpy2: gpy2-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy3: gpy3 { + gpy3: gpy3-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy4: gpy4 { + gpy4: gpy4-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy5: gpy5 { + gpy5: gpy5-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy6: gpy6 { + gpy6: gpy6-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpc0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpc0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpc0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpc0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd0_rclk: sd0-rclk { + sd0_rclk: sd0-rclk-pins { samsung,pins = "gpc0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpc1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpc1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpc1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd1_int: sd1-int { + sd1_int: sd1-int-pins { samsung,pins = "gpd1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpc1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd1_bus8: sd1-bus-width8 { + sd1_bus8: sd1-bus-width8-pins { samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpc2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpc2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpc2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; }; - sd2_wp: sd2-wp { + sd2_wp: sd2-wp-pins { samsung,pins = "gpc4-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; @@ -299,7 +299,7 @@ }; &pinctrl_2 { - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -307,7 +307,7 @@ #interrupt-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -315,7 +315,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -323,7 +323,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -331,7 +331,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -339,7 +339,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -347,7 +347,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -355,7 +355,7 @@ #interrupt-cells = <2>; }; - gpj4: gpj4 { + gpj4: gpj4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -363,7 +363,7 @@ #interrupt-cells = <2>; }; - cam_gpio_a: cam-gpio-a { + cam_gpio_a: cam-gpio-a-pins { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; @@ -372,7 +372,7 @@ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - cam_gpio_b: cam-gpio-b { + cam_gpio_b: cam-gpio-b-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -380,42 +380,42 @@ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - cam_i2c2_bus: cam-i2c2-bus { + cam_i2c2_bus: cam-i2c2-bus-pins { samsung,pins = "gpf0-4", "gpf0-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - cam_spi1_bus: cam-spi1-bus { + cam_spi1_bus: cam-spi1-bus-pins { samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - cam_i2c1_bus: cam-i2c1-bus { + cam_i2c1_bus: cam-i2c1-bus-pins { samsung,pins = "gpf0-2", "gpf0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - cam_i2c0_bus: cam-i2c0-bus { + cam_i2c0_bus: cam-i2c0-bus-pins { samsung,pins = "gpf0-0", "gpf0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - cam_spi0_bus: cam-spi0-bus { + cam_spi0_bus: cam-spi0-bus-pins { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - cam_bayrgb_bus: cam-bayrgb-bus { + cam_bayrgb_bus: cam-bayrgb-bus-pins { samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", @@ -428,7 +428,7 @@ }; &pinctrl_3 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -436,7 +436,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -444,7 +444,7 @@ #interrupt-cells = <2>; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -452,7 +452,7 @@ #interrupt-cells = <2>; }; - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -460,7 +460,7 @@ #interrupt-cells = <2>; }; - gpb1: gpb1 { + gpb1: gpb1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -468,7 +468,7 @@ #interrupt-cells = <2>; }; - gpb2: gpb2 { + gpb2: gpb2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -476,7 +476,7 @@ #interrupt-cells = <2>; }; - gpb3: gpb3 { + gpb3: gpb3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -484,7 +484,7 @@ #interrupt-cells = <2>; }; - gpb4: gpb4 { + gpb4: gpb4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -492,7 +492,7 @@ #interrupt-cells = <2>; }; - gph0: gph0 { + gph0: gph0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -500,98 +500,98 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c3_bus: i2c3-bus { + i2c3_bus: i2c3-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c4_hs_bus: i2c4-hs-bus { + i2c4_hs_bus: i2c4-hs-bus-pins { samsung,pins = "gpa2-0", "gpa2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c5_hs_bus: i2c5-hs-bus { + i2c5_hs_bus: i2c5-hs-bus-pins { samsung,pins = "gpa2-2", "gpa2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; @@ -599,7 +599,7 @@ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -607,7 +607,7 @@ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; @@ -615,7 +615,7 @@ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pcm2_bus: pcm2-bus { + pcm2_bus: pcm2-bus-pins { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; @@ -623,91 +623,91 @@ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - spdif_bus: spdif-bus { + spdif_bus: spdif-bus-pins { samsung,pins = "gpb1-0", "gpb1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_5>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c6_hs_bus: i2c6-hs-bus { + i2c6_hs_bus: i2c6-hs-bus-pins { samsung,pins = "gpb1-3", "gpb1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_4>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpb2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpb2-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpb2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpb2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c7_hs_bus: i2c7-hs-bus { + i2c7_hs_bus: i2c7-hs-bus-pins { samsung,pins = "gpb2-2", "gpb2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpb3-0", "gpb3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpb3-2", "gpb3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c8_hs_bus: i2c8-hs-bus { + i2c8_hs_bus: i2c8-hs-bus-pins { samsung,pins = "gpb3-4", "gpb3-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c9_hs_bus: i2c9-hs-bus { + i2c9_hs_bus: i2c9-hs-bus-pins { samsung,pins = "gpb3-6", "gpb3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - i2c10_hs_bus: i2c10-hs-bus { + i2c10_hs_bus: i2c10-hs-bus-pins { samsung,pins = "gpb4-0", "gpb4-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; @@ -716,7 +716,7 @@ }; &pinctrl_4 { - gpz: gpz { + gpz: gpz-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -724,7 +724,7 @@ #interrupt-cells = <2>; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index a4f0e3ffedbd..4d7b6d9008a7 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -124,6 +124,9 @@ hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; + vdd-supply = <&ldo6_reg>; + vdd_osc-supply = <&ldo7_reg>; + vdd_pll-supply = <&ldo6_reg>; }; &hsi2c_4 { @@ -377,7 +380,7 @@ }; &pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; @@ -386,14 +389,14 @@ }; &pinctrl_2 { - usb300_vbus_en: usb300-vbus-en { + usb300_vbus_en: usb300-vbus-en-pins { samsung,pins = "gpg0-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - usb301_vbus_en: usb301-vbus-en { + usb301_vbus_en: usb301-vbus-en-pins { samsung,pins = "gpg1-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -407,6 +410,16 @@ clock-names = "rtc", "rtc_src"; }; +&usbdrd3_0 { + vdd10-supply = <&ldo11_reg>; + vdd33-supply = <&ldo9_reg>; +}; + +&usbdrd3_1 { + vdd10-supply = <&ldo11_reg>; + vdd33-supply = <&ldo9_reg>; +}; + &usbdrd_phy0 { vbus-supply = <&usb300_vbus_reg>; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index e23e8ffb093f..9f2523a873d9 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -302,8 +302,8 @@ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; clock-names = "ppmu"; events { - ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { - event-name = "ppmu-event3-dmc0_0"; + ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 { + event-name = "ppmu-event3-dmc0-0"; }; }; }; @@ -314,8 +314,8 @@ clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; clock-names = "ppmu"; events { - ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { - event-name = "ppmu-event3-dmc0_1"; + ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 { + event-name = "ppmu-event3-dmc0-1"; }; }; }; @@ -326,8 +326,8 @@ clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; clock-names = "ppmu"; events { - ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { - event-name = "ppmu-event3-dmc1_0"; + ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 { + event-name = "ppmu-event3-dmc1-0"; }; }; }; @@ -338,8 +338,8 @@ clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; clock-names = "ppmu"; events { - ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { - event-name = "ppmu-event3-dmc1_1"; + ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 { + event-name = "ppmu-event3-dmc1-1"; }; }; }; @@ -430,60 +430,50 @@ power-domains = <&mau_pd>; }; - adma: adma@3880000 { + adma: dma-controller@3880000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x03880000 0x1000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_audss EXYNOS_ADMA>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <6>; - #dma-requests = <16>; power-domains = <&mau_pd>; }; - pdma0: pdma@121a0000 { + pdma0: dma-controller@121a0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; - pdma1: pdma@121b0000 { + pdma1: dma-controller@121b0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; - mdma0: mdma@10800000 { + mdma0: dma-controller@10800000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; }; - mdma1: mdma@11c10000 { + mdma1: dma-controller@11c10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; /* * MDMA1 can support both secure and non-secure * AXI transactions. When this is enabled in diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index e7958dbecfd2..35818c4cd852 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -333,8 +333,6 @@ compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; density = <16384>; io-width = <32>; - #address-cells = <1>; - #size-cells = <0>; tRFC-min-tck = <17>; tRRD-min-tck = <2>; @@ -358,10 +356,9 @@ tCKESR-min-tck = <2>; tMRD-min-tck = <5>; - timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + timings_samsung_K3QF2F20DB_800mhz: timings { compatible = "jedec,lpddr3-timings"; - /* workaround: 'reg' shows max-freq */ - reg = <800000000>; + max-freq = <800000000>; min-freq = <100000000>; tRFC = <65000>; tRRD = <6000>; @@ -999,7 +996,7 @@ }; &pinctrl_0 { - s2mps11_irq: s2mps11-irq { + s2mps11_irq: s2mps11-irq-pins { samsung,pins = "gpx0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts index d91f7fa2cf80..3de7019572a2 100644 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -8,6 +8,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include "exynos5422-odroid-core.dtsi" / { @@ -19,7 +20,8 @@ compatible = "pwm-leds"; led-1 { - label = "blue:heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; max-brightness = <255>; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index e35af40a55cb..a6961ff24030 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -480,14 +480,14 @@ }; &pinctrl_0 { - power_key: power-key { + power_key: power-key-pins { samsung,pins = "gpx0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; @@ -496,7 +496,7 @@ }; &pinctrl_1 { - emmc_nrst_pin: emmc-nrst { + emmc_nrst_pin: emmc-nrst-pins { samsung,pins = "gpd1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 62c5928aa994..e3154a1cae23 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -113,13 +113,13 @@ #size-cells = <0>; hub@1 { - compatible = "usb0424,9514"; + compatible = "usb424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { - compatible = "usb0424,ec00"; + ethernet: ethernet@1 { + compatible = "usb424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index cecaeb69e623..a378d4937ff7 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -80,13 +80,13 @@ #size-cells = <0>; hub@1 { - compatible = "usb0424,9514"; + compatible = "usb424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { - compatible = "usb0424,ec00"; + ethernet: ethernet@1 { + compatible = "usb424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 1c24f9b35973..f5fb617f46bd 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -9,6 +9,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include <dt-bindings/sound/samsung-i2s.h> #include "exynos5422-odroidxu3-common.dtsi" @@ -21,7 +22,8 @@ compatible = "pwm-leds"; led-1 { - label = "blue:heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; max-brightness = <255>; diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi index 982752e1df24..8c0e1716c0b3 100644 --- a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi +++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi @@ -9,6 +9,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> / { led-controller-1 { @@ -16,6 +17,8 @@ led-1 { label = "green:mmc0"; + function = LED_FUNCTION_DISK_ACTIVITY; + color = <LED_COLOR_ID_GREEN>; pwms = <&pwm 1 2000000 0>; pwm-names = "pwm1"; /* @@ -27,7 +30,8 @@ }; led-2 { - label = "blue:heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; max-brightness = <255>; @@ -40,6 +44,8 @@ led-3 { label = "red:microSD"; + function = LED_FUNCTION_DISK_ACTIVITY; + color = <LED_COLOR_ID_RED>; gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "mmc1"; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 2ddb7a5f12b3..3ec43761d8b9 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -74,7 +74,8 @@ }; mct: timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5420-mct", + "samsung,exynos4210-mct"; reg = <0x101c0000 0xb00>; interrupts-extended = <&combiner 23 3>, <&combiner 23 4>, diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 77013ee586f8..0ebcb66c6319 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -59,7 +59,7 @@ pinctrl-names = "default"; pinctrl-0 = <&power_key_irq &lid_irq>; - power { + power-key { label = "Power"; gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -221,7 +221,7 @@ interrupts = <1 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&max77802_irq>, <&pmic_selb>, - <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; + <&pmic_dvs_1>, <&pmic_dvs_2>; wakeup-source; reg = <0x9>; #clock-cells = <1>; @@ -756,14 +756,14 @@ pinctrl-names = "default"; pinctrl-0 = <&mask_tpm_reset>; - wifi_en: wifi-en { + wifi_en: wifi-en-pins { samsung,pins = "gpx0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - max98091_irq: max98091-irq { + max98091_irq: max98091-irq-pins { samsung,pins = "gpx0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -771,7 +771,7 @@ }; /* We need GPX0_6 to be low at sleep time; just keep it low always */ - mask_tpm_reset: mask-tpm-reset { + mask_tpm_reset: mask-tpm-reset-pins { samsung,pins = "gpx0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -779,70 +779,70 @@ samsung,pin-val = <0>; }; - tpm_irq: tpm-irq { + tpm_irq: tpm-irq-pins { samsung,pins = "gpx1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - trackpad_irq: trackpad-irq { + trackpad_irq: trackpad-irq-pins { samsung,pins = "gpx1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - power_key_irq: power-key-irq { + power_key_irq: power-key-irq-pins { samsung,pins = "gpx1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - ec_irq: ec-irq { + ec_irq: ec-irq-pins { samsung,pins = "gpx1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - tps65090_irq: tps65090-irq { + tps65090_irq: tps65090-irq-pins { samsung,pins = "gpx2-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - dp_hpd_gpio: dp_hpd_gpio { + dp_hpd_gpio: dp-hpd-gpio-pins { samsung,pins = "gpx2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - max77802_irq: max77802-irq { + max77802_irq: max77802-irq-pins { samsung,pins = "gpx3-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - lid_irq: lid-irq { + lid_irq: lid-irq-pins { samsung,pins = "gpx3-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pmic_dvs_1: pmic-dvs-1 { + pmic_dvs_1: pmic-dvs-1-pins { samsung,pins = "gpy7-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -850,74 +850,67 @@ }; }; -&pinctrl_1 { - /* Adjust WiFi drive strengths lower for EMI */ - sd1_clk: sd1-clk { - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; - }; +/* pinctrl_1 */ +/* Adjust WiFi drive strengths lower for EMI */ +&sd1_bus1 { + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; +}; - sd1_cmd: sd1-cmd { - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; - }; +&sd1_bus4 { + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; +}; - sd1_bus1: sd1-bus-width1 { - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; - }; +&sd1_bus8 { + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; +}; - sd1_bus4: sd1-bus-width4 { - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; - }; +&sd1_clk { + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; +}; - sd1_bus8: sd1-bus-width8 { - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; - }; +&sd1_cmd { + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; &pinctrl_2 { - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpj4-2"; + pmic_dvs_2: pmic-dvs-2-pins { + samsung,pins = "gpj4-2", "gpj4-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; +}; - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpj4-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; - }; +/* pinctrl_3*/ +/* Drive SPI lines at x2 for better integrity */ +&spi2_bus { + samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; &pinctrl_3 { - /* Drive SPI lines at x2 for better integrity */ - spi2-bus { - samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; - }; - /* Drive SPI chip select at x2 for better integrity */ - ec_spi_cs: ec-spi-cs { + ec_spi_cs: ec-spi-cs-pins { samsung,pins = "gpb1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>; }; - usb300_vbus_en: usb300-vbus-en { + usb300_vbus_en: usb300-vbus-en-pins { samsung,pins = "gph0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - usb301_vbus_en: usb301-vbus-en { + usb301_vbus_en: usb301-vbus-en-pins { samsung,pins = "gph0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; - pmic_selb: pmic-selb { + pmic_selb: pmic-selb-pins { samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", "gph0-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; @@ -1072,6 +1065,16 @@ vtmu-supply = <&ldo10_reg>; }; +&usbdrd3_0 { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + +&usbdrd3_1 { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; diff --git a/arch/arm/boot/dts/gemini-ns2502.dts b/arch/arm/boot/dts/gemini-ns2502.dts index 704abd212df5..e6eeb35e8819 100644 --- a/arch/arm/boot/dts/gemini-ns2502.dts +++ b/arch/arm/boot/dts/gemini-ns2502.dts @@ -39,10 +39,6 @@ phy0: ethernet-phy@1 { reg = <1>; device_type = "ethernet-phy"; - /* We lack the knowledge of necessary GPIO to achieve - * Gigabit - */ - max-speed = <100>; }; }; }; @@ -50,7 +46,7 @@ ðernet { status = "okay"; ethernet-port@0 { - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; }; }; @@ -65,30 +61,9 @@ pinctrl-1 = <&pflash_disabled_pins>; partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00020000>; - }; - partition@20000 { - label = "kernel"; - reg = <0x00020000 0x00700000>; - }; - partition@720000 { - label = "VCTL"; - reg = <0x00720000 0x00020000>; - }; - partition@740000 { - label = "CurConf"; - reg = <0x00740000 0x000a0000>; - }; - partition@7e0000 { - label = "FIS"; - reg = <0x007e0000 0x00010000>; - }; + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; }; }; diff --git a/arch/arm/boot/dts/gemini-ssi1328.dts b/arch/arm/boot/dts/gemini-ssi1328.dts index 2b3e7db84fed..42e85f07cf76 100644 --- a/arch/arm/boot/dts/gemini-ssi1328.dts +++ b/arch/arm/boot/dts/gemini-ssi1328.dts @@ -40,10 +40,6 @@ phy0: ethernet-phy@1 { reg = <1>; device_type = "ethernet-phy"; - /* We lack the knowledge of necessary GPIO to achieve - * Gigabit - */ - max-speed = <100>; }; /* WAN ICPlus IP101A */ phy1: ethernet-phy@2 { diff --git a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts new file mode 100644 index 000000000000..3a7382ce40ef --- /dev/null +++ b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for HPE DL360Gen10 + */ + +/include/ "hpe-gxp.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "hpe,gxp-dl360gen10", "hpe,gxp"; + model = "Hewlett Packard Enterprise ProLiant dl360 Gen10"; + + aliases { + serial0 = &uartc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe-gxp.dtsi new file mode 100644 index 000000000000..cf735b3c4f35 --- /dev/null +++ b/arch/arm/boot/dts/hpe-gxp.dtsi @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for HPE GXP + */ + +/dts-v1/; +/ { + model = "Hewlett Packard Enterprise GXP BMC"; + compatible = "hpe,gxp"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L2>; + }; + }; + + clocks { + pll: clock-0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1600000000>; + }; + + iopclk: clock-1 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll>; + }; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + L2: cache-controller@b0040000 { + compatible = "arm,pl310-cache"; + reg = <0xb0040000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + ahb@c0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc0000000 0x30000000>; + dma-ranges; + + vic0: interrupt-controller@eff0000 { + compatible = "arm,pl192-vic"; + reg = <0xeff0000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + vic1: interrupt-controller@80f00000 { + compatible = "arm,pl192-vic"; + reg = <0x80f00000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uarta: serial@e0 { + compatible = "ns16550a"; + reg = <0xe0 0x8>; + interrupts = <17>; + interrupt-parent = <&vic0>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + + uartb: serial@e8 { + compatible = "ns16550a"; + reg = <0xe8 0x8>; + interrupts = <18>; + interrupt-parent = <&vic0>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + + uartc: serial@f0 { + compatible = "ns16550a"; + reg = <0xf0 0x8>; + interrupts = <19>; + interrupt-parent = <&vic0>; + clock-frequency = <1846153>; + reg-shift = <0>; + }; + + usb0: usb@efe0000 { + compatible = "hpe,gxp-ehci", "generic-ehci"; + reg = <0xefe0000 0x100>; + interrupts = <7>; + interrupt-parent = <&vic0>; + }; + + st: timer@80 { + compatible = "hpe,gxp-timer"; + reg = <0x80 0x16>; + interrupts = <0>; + interrupt-parent = <&vic0>; + clocks = <&iopclk>; + clock-names = "iop"; + }; + + usb1: usb@efe0100 { + compatible = "hpe,gxp-ohci", "generic-ohci"; + reg = <0xefe0100 0x110>; + interrupts = <6>; + interrupt-parent = <&vic0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 8cbaf1c81174..3b609d987d88 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -79,7 +79,6 @@ MX23_PAD_LCD_RESET__GPIO_1_18 MX23_PAD_PWM3__GPIO_1_29 MX23_PAD_PWM4__GPIO_1_30 - MX23_PAD_SSP1_DETECT__SSP1_DETECT >; fsl,drive-strength = <MXS_DRIVE_4mA>; fsl,voltage = <MXS_VOLTAGE_HIGH>; diff --git a/arch/arm/boot/dts/imx23-pinfunc.h b/arch/arm/boot/dts/imx23-pinfunc.h index 5c0f32ca3a93..468c079f3c2b 100644 --- a/arch/arm/boot/dts/imx23-pinfunc.h +++ b/arch/arm/boot/dts/imx23-pinfunc.h @@ -1,14 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Header providing constants for i.MX23 pinctrl bindings. * * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #ifndef __DT_BINDINGS_MX23_PINCTRL_H__ diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/imx23-xfi3.dts index a6213c590f94..b1d8210f3ecc 100644 --- a/arch/arm/boot/dts/imx23-xfi3.dts +++ b/arch/arm/boot/dts/imx23-xfi3.dts @@ -158,19 +158,19 @@ default-brightness-level = <6>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&key_pins_a>; - voldown { + key-voldown { label = "volume-down"; linux,code = <114>; gpios = <&gpio2 7 0>; debounce-interval = <20>; }; - volup { + key-volup { label = "volume-up"; linux,code = <115>; gpios = <&gpio2 8 0>; diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts index 3f38c2e60a74..c7207ea437c4 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts @@ -13,12 +13,12 @@ model = "Eukrea MBIMXSD25"; compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiokeys>; - bp1 { + button { label = "BP1"; gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; linux,code = <BTN_MISC>; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index fa8044c21cb8..5f90d72b840b 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -68,7 +68,7 @@ }; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -515,7 +515,7 @@ #interrupt-cells = <2>; }; - sdma: sdma@53fd4000 { + sdma: dma-controller@53fd4000 { compatible = "fsl,imx25-sdma"; reg = <0x53fd4000 0x4000>; clocks = <&clks 112>, <&clks 68>; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index fd525c3b16fa..e140307be2e7 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -74,14 +74,14 @@ }; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&aitc>; ranges; - aipi@10000000 { /* AIPI1 */ + aipi1: aipi@10000000 { /* AIPI1 */ compatible = "fsl,aipi-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -96,7 +96,7 @@ <&clks IMX27_CLK_DMA_AHB_GATE>; clock-names = "ipg", "ahb"; #dma-cells = <1>; - #dma-channels = <16>; + dma-channels = <16>; }; wdog: watchdog@10002000 { @@ -453,7 +453,7 @@ }; }; - aipi@10020000 { /* AIPI2 */ + aipi2: aipi@10020000 { /* AIPI2 */ compatible = "fsl,aipi-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index a92b05ef390f..9ef0d567ea48 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -327,7 +327,7 @@ }; }; - spi2 { + spi-2 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_cfa10049>; @@ -351,7 +351,7 @@ }; }; - spi3 { + spi-3 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&spi3_pins_cfa10049>; @@ -388,12 +388,12 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&rotary_btn_pins_cfa10049>; - rotary_button { + rotary-button { label = "rotary_button"; gpios = <&gpio3 26 1>; debounce-interval = <10>; diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts index d05c370dfc17..fac5bbda7a93 100644 --- a/arch/arm/boot/dts/imx28-cfa10055.dts +++ b/arch/arm/boot/dts/imx28-cfa10055.dts @@ -129,7 +129,7 @@ }; }; - spi2 { + spi-2 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_cfa10055>; diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts index c1060bd5f17f..c5f3337e8b39 100644 --- a/arch/arm/boot/dts/imx28-cfa10056.dts +++ b/arch/arm/boot/dts/imx28-cfa10056.dts @@ -88,7 +88,7 @@ }; }; - spi2 { + spi-2 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_cfa10056>; diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts index bacb846f99e3..73f521c46c1e 100644 --- a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts +++ b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts @@ -204,7 +204,7 @@ pinctrl-names = "default"; pinctrl-0 = <&enocean_button>; - enocean { + key-enocean { label = "EnOcean"; linux,code = <KEY_NEW>; gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi index 3280fddaaf0d..b285a946e2c2 100644 --- a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi +++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi @@ -19,12 +19,12 @@ default-brightness-level = <10>; }; - button-sw3 { + gpio-keys-0 { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>; - sw3 { + switch-sw3 { label = "SW3"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; linux,code = <BTN_MISC>; @@ -32,12 +32,12 @@ }; }; - button-sw4 { + gpio-keys-1 { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>; - sw4 { + switch-sw4 { label = "SW4"; gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; linux,code = <BTN_MISC>; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 7e2b0f198dfa..1053b7c584d8 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -129,7 +129,7 @@ pinctrl-0 = <&spi2_pins_a>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index f3bddc5ada4b..13acdc7916b9 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -33,7 +33,7 @@ pinctrl-0 = <&spi2_pins_a>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx28-pinfunc.h b/arch/arm/boot/dts/imx28-pinfunc.h index e11f69ba0fe4..d427e6c2fa78 100644 --- a/arch/arm/boot/dts/imx28-pinfunc.h +++ b/arch/arm/boot/dts/imx28-pinfunc.h @@ -1,14 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Header providing constants for i.MX28 pinctrl bindings. * * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #ifndef __DT_BINDINGS_MX28_PINCTRL_H__ diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts index 43be7a6a769b..90928db0df70 100644 --- a/arch/arm/boot/dts/imx28-sps1.dts +++ b/arch/arm/boot/dts/imx28-sps1.dts @@ -51,7 +51,7 @@ pinctrl-0 = <&spi2_pins_a>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "everspin,mr25h256", "mr25h256"; diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts index 097ec35c62d8..0d58da1c0cc5 100644 --- a/arch/arm/boot/dts/imx28-ts4600.dts +++ b/arch/arm/boot/dts/imx28-ts4600.dts @@ -26,7 +26,7 @@ pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg &en_sd_pwr>; - broken-cd = <1>; + broken-cd; bus-width = <4>; vmmc-supply = <®_vddio_sd0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 9e5651c7ea6b..096f246032c6 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -221,7 +221,7 @@ linux,no-autorepeat; }; - spi_gpio: spi-gpio { + spi_gpio: spi { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; @@ -338,7 +338,7 @@ }; ds1339: rtc@68 { - compatible = "mxim,ds1339"; + compatible = "dallas,ds1339"; reg = <0x68>; trickle-resistor-ohms = <250>; trickle-diode-disable; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 84d0176d5193..130b4145af82 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -110,6 +110,8 @@ interrupt-names = "bch"; clocks = <&clks 50>; clock-names = "gpmi_io"; + assigned-clocks = <&clks 13>; + assigned-clock-parents = <&clks 10>; dmas = <&dma_apbh 4>; dma-names = "rx-tx"; status = "disabled"; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 2adb923c0b27..95c05f17a6d5 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -48,7 +48,7 @@ reg = <0x68000000 0x100000>; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -63,7 +63,7 @@ ranges = <0 0x1fffc000 0x4000>; }; - bus@43f00000 { /* AIPS1 */ + aips1: bus@43f00000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -297,7 +297,7 @@ #interrupt-cells = <2>; }; - sdma: sdma@53fd4000 { + sdma: dma-controller@53fd4000 { compatible = "fsl,imx31-sdma"; reg = <0x53fd4000 0x4000>; interrupts = <34>; diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts index b1c11170ac25..7f4f812b0811 100644 --- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts @@ -13,12 +13,12 @@ model = "Eukrea CPUIMX35"; compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_bp1>; - bp1 { + button { label = "BP1"; gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; linux,code = <BTN_MISC>; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 8e41c8b7bd70..d650f54c3fc6 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -284,7 +284,7 @@ #interrupt-cells = <2>; }; - sdma: sdma@53fd4000 { + sdma: dma-controller@53fd4000 { compatible = "fsl,imx35-sdma"; reg = <0x53fd4000 0x4000>; clocks = <&clks 9>, <&clks 65>; diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts index 82ce8c43be86..51bf6117fb12 100644 --- a/arch/arm/boot/dts/imx50-kobo-aura.dts +++ b/arch/arm/boot/dts/imx50-kobo-aura.dts @@ -38,20 +38,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiokeys>; - power { + key-power { label = "Power Button"; gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; }; - hallsensor { + event-hallsensor { label = "Hallsensor"; gpios = <&gpio5 15 GPIO_ACTIVE_LOW>; linux,code = <KEY_RESERVED>; linux,input-type = <EV_SW>; }; - frontlight { + event-frontlight { label = "Frontlight"; gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_DISPLAYTOGGLE>; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index be0de0fd31f9..3d9a9f37f672 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -94,14 +94,14 @@ status = "okay"; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&tzic>; ranges; - bus@50000000 { /* AIPS1 */ + aips1: bus@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -385,7 +385,7 @@ }; }; - bus@60000000 { /* AIPS2 */ + aips2: bus@60000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -421,7 +421,7 @@ status = "disabled"; }; - sdma: sdma@63fb0000 { + sdma: dma-controller@63fb0000 { compatible = "fsl,imx50-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts index c66f274ba4e9..b61d55ca1467 100644 --- a/arch/arm/boot/dts/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/imx51-apf51dev.dts @@ -63,7 +63,7 @@ leds { compatible = "gpio-leds"; - user { + led-user { label = "Heartbeat"; gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 552196d8a60a..a1f9c6a72275 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -154,7 +154,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + key-power { label = "Power Button"; gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts index aab8d6f137c3..10cae7c3a879 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts +++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts @@ -13,6 +13,13 @@ chosen { stdout-path = &uart1; }; + + usbphy1: usbphy1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; }; &esdhc1 { @@ -63,6 +70,7 @@ &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1>; + fsl,usbphy = <&usbphy1>; dr_mode = "host"; phy_type = "ulpi"; disable-over-current; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 7d4970417dce..f0809a16a2ce 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -34,22 +34,22 @@ regulators { sw1_reg: sw1 { - regulator-min-microvolt = <1000000>; + regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; }; sw2_reg: sw2 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; + regulator-min-microvolt = <1175000>; + regulator-max-microvolt = <1275000>; regulator-boot-on; regulator-always-on; }; sw3_reg: sw3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1350000>; regulator-boot-on; regulator-always-on; }; @@ -102,18 +102,6 @@ regulator-always-on; }; - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - vgen3_reg: vgen3 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -124,8 +112,6 @@ regulator-always-on; }; - gpo1_reg: gpo1 { }; - gpo2_reg: gpo2 { }; gpo3_reg: gpo3 { }; @@ -198,6 +184,7 @@ &usbotg { phy_type = "utmi_wide"; disable-over-current; + vbus-supply = <&swbst_reg>; /* Device role is not known, keep status disabled */ }; diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts index 6ecb83e7f336..f7408722d68a 100644 --- a/arch/arm/boot/dts/imx51-ts4800.dts +++ b/arch/arm/boot/dts/imx51-ts4800.dts @@ -102,7 +102,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - rtc: m41t00@68 { + rtc: rtc@68 { compatible = "st,m41t00"; reg = <0x68>; }; @@ -174,7 +174,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_interrupt_fpga>; interrupt-parent = <&gpio2>; - interrupts= <9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; }; diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index ec8ca3ac2c1c..3140f038aa98 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -137,7 +137,7 @@ }; }; - spi_gpio: spi-gpio { + spi_gpio: spi { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 56c8d87864c3..853707574d2e 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -114,7 +114,7 @@ ports = <&ipu_di0>, <&ipu_di1>; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -171,7 +171,7 @@ }; }; - bus@70000000 { /* AIPS1 */ + aips1: bus@70000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -215,6 +215,8 @@ clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 43 5 1>, <&sdma 44 5 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -426,6 +428,8 @@ clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 18 4 1>, <&sdma 19 4 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -436,6 +440,8 @@ clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 16 4 1>, <&sdma 17 4 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -454,7 +460,7 @@ }; }; - bus@80000000 { /* AIPS2 */ + aips2: bus@80000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -498,7 +504,7 @@ status = "disabled"; }; - sdma: sdma@83fb0000 { + sdma: dma-controller@83fb0000 { compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; reg = <0x83fb0000 0x4000>; interrupts = <6>; diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index 6208fbb2e741..23a7492e2929 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts @@ -61,34 +61,34 @@ gpio-keys { compatible = "gpio-keys"; - home { + key-home { label = "Home"; gpios = <&gpio5 10 0>; linux,code = <KEY_HOME>; wakeup-source; }; - back { + key-back { label = "Back"; gpios = <&gpio5 11 0>; linux,code = <KEY_BACK>; wakeup-source; }; - program { + key-program { label = "Program"; gpios = <&gpio5 12 0>; linux,code = <KEY_PROGRAM >; wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio5 13 0>; linux,code = <KEY_VOLUMEUP>; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio4 0 0>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts index 4f88e96d81dd..d5c68d1ea707 100644 --- a/arch/arm/boot/dts/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/imx53-m53menlo.dts @@ -53,6 +53,31 @@ }; }; + lvds-decoder { + compatible = "ti,ds90cf364a", "lvds-decoder"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_decoder_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@1 { + reg = <1>; + + lvds_decoder_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + panel { compatible = "edt,etm0700g0dh6"; pinctrl-0 = <&pinctrl_display_gpio>; @@ -61,7 +86,7 @@ port { panel_in: endpoint { - remote-endpoint = <&lvds0_out>; + remote-endpoint = <&lvds_decoder_out>; }; }; }; @@ -450,7 +475,7 @@ reg = <2>; lvds0_out: endpoint { - remote-endpoint = <&panel_in>; + remote-endpoint = <&lvds_decoder_in>; }; }; }; diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index fe4244044a0f..50fef8dd3675 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -45,20 +45,20 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power Button"; gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -71,7 +71,7 @@ pinctrl-names = "default"; pinctrl-0 = <&led_pin_gpio7_7>; - user { + led-user { label = "Heartbeat"; gpios = <&gpio7 7 0>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 9be44e807188..f8d17967a67e 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -19,13 +19,13 @@ gpio-keys { compatible = "gpio-keys"; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio2 14 0>; linux,code = <KEY_VOLUMEUP>; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio2 15 0>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index 81c2726a328a..892dd1a4bac3 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -81,7 +81,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_key>; - power { + key-power { label = "Power Button"; gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; linux,code = <116>; /* KEY_POWER */ @@ -241,7 +241,7 @@ clock-frequency = <400000>; status = "okay"; - rtc1: ds1339@68 { + rtc1: rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 67487f3caee1..56b3c13f4eb7 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -132,7 +132,7 @@ status = "okay"; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -222,7 +222,7 @@ clock-names = "core_clk", "mem_iface_clk"; }; - bus@50000000 { /* AIPS1 */ + aips1: bus@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -655,7 +655,7 @@ }; }; - bus@60000000 { /* AIPS2 */ + aips2: bus@60000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -710,7 +710,7 @@ status = "disabled"; }; - sdma: sdma@63fb0000 { + sdma: dma-controller@63fb0000 { compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi index d9de9b4f0c52..d477a937b47a 100644 --- a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi +++ b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi @@ -6,7 +6,7 @@ keyboard { compatible = "gpio-keys"; - btn0 { + button-0 { gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>; label = "btn0"; linux,code = <KEY_WAKEUP>; @@ -14,7 +14,7 @@ wakeup-source; }; - btn1 { + button-1 { gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>; label = "btn1"; linux,code = <KEY_WAKEUP>; @@ -22,7 +22,7 @@ wakeup-source; }; - btn2 { + button-2 { gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>; label = "btn2"; linux,code = <KEY_WAKEUP>; @@ -30,7 +30,7 @@ wakeup-source; }; - btn3 { + button-3 { gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>; label = "btn3"; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi index ec5b66453156..337db29b0010 100644 --- a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi +++ b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi @@ -188,7 +188,7 @@ rotary-encoder-key { compatible = "gpio-keys"; - rotary-encoder-press { + rotary-encoder-event { label = "rotary-encoder press"; gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>; linux,code = <KEY_ENTER>; diff --git a/arch/arm/boot/dts/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/imx6dl-colibri-aster.dts new file mode 100644 index 000000000000..74e8a6cd8bed --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-aster.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Aster Board"; + compatible = "toradex,colibri_imx6dl-aster", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* Colibri SSP */ +&ecspi4 { + cs-gpios = < + &gpio5 2 GPIO_ACTIVE_HIGH + &gpio5 4 GPIO_ACTIVE_HIGH + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_csi_gpio_2>; + status = "okay"; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c3 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_csi_gpio_1 + &pinctrl_gpio_2 + &pinctrl_gpio_aster + &pinctrl_usbh_oc_1 + &pinctrl_usbc_id_1 + &pinctrl_weim_gpio_5 + >; + + pinctrl_gpio_aster: gpioaster { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 7da74e6f46d9..7272edd85a49 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ @@ -17,12 +17,6 @@ compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl", "fsl,imx6dl"; - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - aliases { i2c0 = &i2c2; i2c1 = &i2c3; @@ -44,67 +38,6 @@ clock-frequency = <16000000>; clock-output-names = "clk16m"; }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; -}; - -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - status = "okay"; }; /* Colibri SSP */ @@ -113,40 +46,21 @@ mcp251x0: mcp251x@0 { compatible = "microchip,mcp2515"; - reg = <0>; clocks = <&clk16m>; interrupt-parent = <&gpio3>; interrupts = <27 0x2>; + reg = <0>; spi-max-frequency = <10000000>; status = "okay"; }; }; -&hdmi { - status = "okay"; -}; - /* * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ &i2c3 { status = "okay"; - /* - * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcap_1>; - reg = <0x4a>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 */ - status = "disabled"; - }; - /* M41T0M6 real time clock on carrier board */ rtc_i2c: rtc@68 { compatible = "st,m41t0"; @@ -162,24 +76,6 @@ &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6 &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1 >; - - pinctrl_pcap_1: pcap1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */ - >; - }; - - pinctrl_mxt_ts: mxttsgrp { - fsl,pins = < - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */ - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */ - >; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; }; &pwm1 { diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts new file mode 100644 index 000000000000..3a6d3889760d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6dl-colibri-iris.dts" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Iris V2 Board"; + compatible = "toradex,colibri_imx6dl-iris-v2", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_iris &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1>; + + pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; +}; + +/* Colibri MMC */ +&usdhc1 { + cap-power-off-card; + /* uncomment the following to enable SD card UHS mode if you have a V1.1 module */ + /* /delete-property/ no-1-8-v; */ + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris.dts b/arch/arm/boot/dts/imx6dl-colibri-iris.dts new file mode 100644 index 000000000000..cf77d894f6d7 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-iris.dts @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Iris Board"; + compatible = "toradex,colibri_imx6dl-iris", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* Colibri SSP */ +&ecspi4 { + status = "okay"; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_forceoff &pinctrl_uart23_forceoff>; + + /* + * uart-a-on-x13-enable turns the UART transceiver for UART_A on. If one + * wants to turn the transceiver off, that property has to be deleted + * and the gpio handled in userspace. + * The same applies to uart-b-c-on-x14-enable where the UART_B and + * UART_C transceiver is turned on. + */ + uart-a-on-x13-enable-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ + output-high; + }; + + uart-b-c-on-x14-enable-hog { + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ + output-high; + }; +}; + +/* + * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) + */ +&i2c3 { + status = "okay"; + + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_gpio_iris + &pinctrl_usbh_oc_1 + &pinctrl_usbc_id_1 + >; + + pinctrl_gpio_iris: gpioirisgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + + pinctrl_uart1_forceoff: uart1forceoffgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + >; + }; + + pinctrl_uart23_forceoff: uart23forceoffgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + >; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts deleted file mode 100644 index 223275f028f1..000000000000 --- a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -/dts-v1/; - -#include "imx6dl-colibri-eval-v3.dts" -#include "imx6qdl-colibri-v1_1-uhs.dtsi" - -/ { - model = "Toradex Colibri iMX6DL/S V1.1 on Colibri Evaluation Board V3"; - compatible = "toradex,colibri_imx6dl-v1_1-eval-v3", - "toradex,colibri_imx6dl-v1_1", - "toradex,colibri_imx6dl-eval-v3", - "toradex,colibri_imx6dl", - "fsl,imx6dl"; -}; - -/* Colibri MMC */ -&usdhc1 { - status = "okay"; - /* - * Please make sure your carrier board does not pull-up any of - * the MMC/SD signals to 3.3 volt before attempting to activate - * UHS-I support. - * To let signaling voltage be changed to 1.8V, please - * delete no-1-8-v property (example below): - * /delete-property/no-1-8-v; - */ -}; diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts index b4a9523e325b..864dc5018451 100644 --- a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts +++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts @@ -297,7 +297,11 @@ phy-mode = "rmii"; phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; phy-handle = <&phy>; - clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&rmii_clk>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; status = "okay"; mdio { diff --git a/arch/arm/boot/dts/imx6dl-plybas.dts b/arch/arm/boot/dts/imx6dl-plybas.dts index bf72a67a9c76..c52e6caf3996 100644 --- a/arch/arm/boot/dts/imx6dl-plybas.dts +++ b/arch/arm/boot/dts/imx6dl-plybas.dts @@ -214,7 +214,7 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; + uart-has-rtscts; linux,rs485-enabled-at-boot-time; rs485-rts-delay = <0 20>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts index 60fe5f14666e..522660c912a0 100644 --- a/arch/arm/boot/dts/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/imx6dl-plym2m.dts @@ -50,6 +50,11 @@ }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&vdiv_vaccu>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -101,6 +106,64 @@ regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; }; + + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; + }; + + touch-thermal0 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp0>; + }; + + touch-thermal1 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp1>; + }; + }; + + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, + <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <64687>; + touchscreen-inverted-x; + touchscreen-inverted-y; + touchscreen-x-plate-ohms = <300>; + touchscreen-y-plate-ohms = <800>; + }; + + touch_temp0: touch-temperature-sensor0 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 736 + 85000 474>; + }; + + touch_temp1: touch-temperature-sensor1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 7>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 826 + 85000 609>; + }; + + vdiv_vaccu: voltage-divider-vaccu { + compatible = "voltage-divider"; + io-channels = <&adc_ts 2>; + output-ohms = <2500>; + full-ohms = <64000>; + #io-channel-cells = <0>; + }; }; &can1 { @@ -129,26 +192,61 @@ pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - touchscreen@0 { - compatible = "ti,tsc2046"; + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; reg = <0>; pinctrl-0 = <&pinctrl_tsc2046>; - pinctrl-names ="default"; - spi-max-frequency = <100000>; - interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; - pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + #io-channel-cells = <1>; - touchscreen-inverted-x; - touchscreen-inverted-y; - touchscreen-max-pressure = <4095>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + settling-time-us = <300>; + oversampling-ratio = <5>; + }; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; - ti,vref-delay-usecs = /bits/ 16 <100>; - ti,x-plate-ohms = /bits/ 16 <800>; - ti,y-plate-ohms = /bits/ 16 <300>; - ti,debounce-max = /bits/ 16 <3>; - ti,debounce-tol = /bits/ 16 <70>; - ti,debounce-rep = /bits/ 16 <3>; - wakeup-source; + channel@2 { + reg = <2>; + settling-time-us = <300>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + /* channel 6 is not connected */ + + channel@7 { + reg = <7>; + settling-time-us = <300>; + oversampling-ratio = <5>; + }; }; }; @@ -233,9 +331,10 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - temperature-sensor@70 { + tsens0: temperature-sensor@70 { compatible = "ti,tmp103"; reg = <0x70>; + #thermal-sensor-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/imx6dl-prtmvt.dts b/arch/arm/boot/dts/imx6dl-prtmvt.dts index a35a1c66e770..1f8cddd83ccb 100644 --- a/arch/arm/boot/dts/imx6dl-prtmvt.dts +++ b/arch/arm/boot/dts/imx6dl-prtmvt.dts @@ -51,98 +51,98 @@ pinctrl-0 = <&pinctrl_gpiokeys>; autorepeat; - power { + key-power { label = "Power Button"; gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - f1 { + key-f1 { label = "GPIO Key F1"; linux,code = <KEY_F1>; gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; }; - f2 { + key-f2 { label = "GPIO Key F2"; linux,code = <KEY_F2>; gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; }; - f3 { + key-f3 { label = "GPIO Key F3"; linux,code = <KEY_F3>; gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; }; - f4 { + key-f4 { label = "GPIO Key F4"; linux,code = <KEY_F4>; gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; }; - f5 { + key-f5 { label = "GPIO Key F5"; linux,code = <KEY_F5>; gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; }; - cycle { + key-cycle { label = "GPIO Key CYCLE"; linux,code = <KEY_CYCLEWINDOWS>; gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; }; - esc { + key-esc { label = "GPIO Key ESC"; linux,code = <KEY_ESC>; gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; }; - up { + key-up { label = "GPIO Key UP"; linux,code = <KEY_UP>; gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; }; - down { + key-down { label = "GPIO Key DOWN"; linux,code = <KEY_DOWN>; gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; }; - ok { + key-ok { label = "GPIO Key OK"; linux,code = <KEY_OK>; gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; }; - f6 { + key-f6 { label = "GPIO Key F6"; linux,code = <KEY_F6>; gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; }; - f7 { + key-f7 { label = "GPIO Key F7"; linux,code = <KEY_F7>; gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; }; - f8 { + key-f8 { label = "GPIO Key F8"; linux,code = <KEY_F8>; gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; }; - f9 { + key-f9 { label = "GPIO Key F9"; linux,code = <KEY_F9>; gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; }; - f10 { + key-f10 { label = "GPIO Key F10"; linux,code = <KEY_F10>; gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index 190d26642bc8..a1eb53851794 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-prti6q.dtsi" +#include <dt-bindings/display/sdtv-standards.h> #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/sound/fsl-imx-audmux.h> @@ -28,95 +29,124 @@ power-supply = <®_bl_12v0>; }; + display { + compatible = "fsl,imx-parallel-display"; + pinctrl-0 = <&pinctrl_ipu1_disp>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&vdiv_vaccu>; + }; + keys { compatible = "gpio-keys"; autorepeat; - esc { + key-esc { label = "GPIO Key ESC"; linux,code = <KEY_ESC>; gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; }; - up { + key-up { label = "GPIO Key UP"; linux,code = <KEY_UP>; gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; }; - down { + key-down { label = "GPIO Key DOWN"; linux,code = <KEY_DOWN>; gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; }; - enter { + key-enter { label = "GPIO Key Enter"; linux,code = <KEY_ENTER>; gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; }; - cycle { + key-cycle { label = "GPIO Key CYCLE"; linux,code = <KEY_CYCLEWINDOWS>; gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; }; - f1 { + key-f1 { label = "GPIO Key F1"; linux,code = <KEY_F1>; gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; }; - f2 { + key-f2 { label = "GPIO Key F2"; linux,code = <KEY_F2>; gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; }; - f3 { + key-f3 { label = "GPIO Key F3"; linux,code = <KEY_F3>; gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; }; - f4 { + key-f4 { label = "GPIO Key F4"; linux,code = <KEY_F4>; gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; }; - f5 { + key-f5 { label = "GPIO Key F5"; linux,code = <KEY_F5>; gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; }; - f6 { + key-f6 { label = "GPIO Key F6"; linux,code = <KEY_F6>; gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; }; - f7 { + key-f7 { label = "GPIO Key F7"; linux,code = <KEY_F7>; gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; }; - f8 { + key-f8 { label = "GPIO Key F8"; linux,code = <KEY_F8>; gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; }; - f9 { + key-f9 { label = "GPIO Key F9"; linux,code = <KEY_F9>; gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; }; - f10 { + key-f10 { label = "GPIO Key F10"; linux,code = <KEY_F10>; gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; @@ -135,6 +165,30 @@ }; }; + panel { + compatible = "innolux,g070y2-t02"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + connector { + compatible = "composite-video-connector"; + label = "Composite0"; + sdtv-standards = <SDTV_STD_PAL_B>; + + port { + comp0_out: endpoint { + remote-endpoint = <&tvp5150_comp0_in>; + }; + }; + }; + reg_bl_12v0: regulator-bl-12v0 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -146,6 +200,13 @@ enable-active-high; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_1v8: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "1v8"; @@ -179,6 +240,64 @@ frame-master; }; }; + + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; + }; + + touch-thermal0 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp0>; + }; + + touch-thermal1 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp1>; + }; + }; + + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, + <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <64687>; + touchscreen-inverted-x; + touchscreen-inverted-y; + touchscreen-x-plate-ohms = <300>; + touchscreen-y-plate-ohms = <800>; + }; + + touch_temp0: touch-temperature-sensor0 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 736 + 85000 474>; + }; + + touch_temp1: touch-temperature-sensor1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 7>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 826 + 85000 609>; + }; + + vdiv_vaccu: voltage-divider-vaccu { + compatible = "voltage-divider"; + io-channels = <&adc_ts 2>; + output-ohms = <2500>; + full-ohms = <64000>; + #io-channel-cells = <0>; + }; }; &audmux { @@ -221,22 +340,41 @@ pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - touchscreen@0 { - compatible = "ti,tsc2046"; + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; reg = <0>; pinctrl-0 = <&pinctrl_tsc>; - pinctrl-names ="default"; - spi-max-frequency = <100000>; - interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; - pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - touchscreen-max-pressure = <4095>; - ti,vref-delay-usecs = /bits/ 16 <100>; - ti,x-plate-ohms = /bits/ 16 <800>; - ti,y-plate-ohms = /bits/ 16 <300>; - ti,debounce-max = /bits/ 16 <3>; - ti,debounce-tol = /bits/ 16 <70>; - ti,debounce-rep = /bits/ 16 <3>; - wakeup-source; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; }; }; @@ -252,6 +390,31 @@ VDDIO-supply = <®_3v3>; VDDD-supply = <®_1v8>; }; + + video@5c { + compatible = "ti,tvp5150"; + reg = <0x5c>; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tvp5150_comp0_in: endpoint { + remote-endpoint = <&comp0_out>; + }; + }; + + /* Output port 2 is video output pad */ + port@2 { + reg = <2>; + + tvp5151_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + }; + }; + }; }; &i2c3 { @@ -260,6 +423,12 @@ reg = <0x51>; }; + tsens0: temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + #thermal-sensor-cells = <0>; + }; + gpio_pca: gpio@74 { compatible = "nxp,pca9539"; reg = <0x74>; @@ -275,6 +444,14 @@ status = "okay"; }; +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/imx6dl-rex-basic.dts index 0f1616bfa9a8..b72f8ea1e6f6 100644 --- a/arch/arm/boot/dts/imx6dl-rex-basic.dts +++ b/arch/arm/boot/dts/imx6dl-rex-basic.dts @@ -19,7 +19,7 @@ }; &ecspi3 { - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index e7d9bfbfd0e4..e7be05f205d3 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -90,6 +90,7 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-handle = <&rgmii_phy>; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index d37ba4ed847d..72df1dba83be 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -5,60 +5,27 @@ */ /dts-v1/; -#include <dt-bindings/display/sdtv-standards.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/media/tvp5150.h> -#include <dt-bindings/sound/fsl-imx-audmux.h> #include "imx6dl.dtsi" +#include "imx6qdl-vicut1.dtsi" / { model = "Kverneland TGO"; compatible = "kvg,victgo", "fsl,imx6dl"; - chosen { - stdout-path = &uart4; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <1>; - power-supply = <®_3v3>; - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - }; - - connector { - compatible = "composite-video-connector"; - label = "Composite0"; - sdtv-standards = <SDTV_STD_PAL_B>; - - port { - comp0_out: endpoint { - remote-endpoint = <&tvp5150_comp0_in>; - }; - }; - }; - gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiokeys>; autorepeat; - power { + key-power { label = "Power Button"; gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - enter { + key-enter { label = "Rotary Key"; gpios = <&gpio2 05 GPIO_ACTIVE_LOW>; linux,code = <KEY_ENTER>; @@ -66,36 +33,14 @@ }; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - label = "debug0"; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - label = "debug1"; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - - led-2 { - label = "power_led"; - function = LED_FUNCTION_POWER; - gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&vdiv_vaccu>, <&vdiv_hitch_pos>; }; panel { - compatible = "kyo,tcg121xglp"; - backlight = <&backlight>; + compatible = "lg,lb070wv8"; + backlight = <&backlight_lcd>; power-supply = <®_3v3>; port { @@ -111,38 +56,6 @@ clock-frequency = <50000000>; }; - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_h1_vbus: regulator-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - rotary-encoder { compatible = "rotary-encoder"; pinctrl-0 = <&pinctrl_rotary_ch>; @@ -155,86 +68,69 @@ wakeup-source; }; - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "prti6q-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Line", "Line In Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "External Speaker", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - system-clock-frequency = <0>; + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; }; - simple-audio-card,codec { - sound-dai = <&codec>; - bitclock-master; - frame-master; + touch-thermal0 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp0>; }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN 0 - IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TFSDIR 0 - IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; + touch-thermal1 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp1>; + }; }; - mux-pins3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) - 0 IMX_AUDMUX_V2_PDCR_TXRXEN - >; + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, + <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <64687>; + touchscreen-inverted-y; + touchscreen-x-plate-ohms = <300>; + touchscreen-y-plate-ohms = <800>; }; -}; -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; + touch_temp0: touch-temperature-sensor0 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 736 + 85000 474>; + }; -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; -}; + touch_temp1: touch-temperature-sensor1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 7>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 826 + 85000 609>; + }; -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; + vdiv_vaccu: voltage-divider-vaccu { + compatible = "voltage-divider"; + io-channels = <&adc_ts 2>; + output-ohms = <2500>; + full-ohms = <64000>; + #io-channel-cells = <0>; + }; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; + vdiv_hitch_pos: voltage-divider-hitch-pos { + compatible = "voltage-divider"; + io-channels = <&adc_ts 6>; + output-ohms = <3300>; + full-ohms = <13300>; + #io-channel-cells = <0>; }; }; @@ -244,22 +140,41 @@ pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - touchscreen@0 { - compatible = "ti,tsc2046"; + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; reg = <0>; - pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touchscreen>; - spi-max-frequency = <200000>; - interrupts-extended = <&gpio5 8 IRQ_TYPE_EDGE_FALLING>; - pendown-gpio = <&gpio5 8 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-y; - touchscreen-max-pressure = <4095>; - ti,vref-delay-usecs = /bits/ 16 <100>; - ti,x-plate-ohms = /bits/ 16 <800>; - ti,y-plate-ohms = /bits/ 16 <300>; - wakeup-source; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; }; }; @@ -295,36 +210,19 @@ "CAM2_MIRROR", "", "", "SMBALERT", "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", - "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", - "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH", - "POWER_LED", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", - "CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ", - "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", - "YACO_RESET"; + "SD1_DATA3", "ETH_MDIO", "", + "", "", "", "", "", "", "", "ETH_MDC"; }; &gpio4 { gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "", "", "", - "CPU_LIGHT_ON", "", "ETH_RESET", "CPU_CONTACT_IN", "BL_EN", - "BL_PWM", "ETH_INTRP", "ISB_LED"; + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "ETH_RESET", "CONTACT_IN", "BL_EN", + "BL_PWM", "ETH_INT", "ISB_LED"; }; &gpio5 { @@ -332,51 +230,22 @@ "", "", "", "", "", "", "", "", "TSC_PENIRQ", "TSC_BUSY", "ECSPI2_MOSI", "ECSPI2_MISO", "ECSPI2_SS0", "ECSPI2_SCLK", "", "", - "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; }; -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0xa>; - #sound-dai-cells = <0>; - clocks = <&clks 201>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <®_3v3>; - VDDD-supply = <®_1v8>; - }; - - video-decoder@5c { - compatible = "ti,tvp5150"; - reg = <0x5c>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tvp5150_comp0_in: endpoint { - remote-endpoint = <&comp0_out>; - }; - }; - - /* Output port 2 is video output pad */ - port@2 { - reg = <2>; - - tvp5151_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - }; - }; - }; +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; +&i2c1 { keypad@70 { compatible = "holtek,ht16k33"; pinctrl-names = "default"; @@ -400,224 +269,9 @@ MATRIX_KEY(6, 1, KEY_F1) >; }; - - /* additional i2c devices are added automatically by the boot loader */ -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@5 { - reg = <5>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@6 { - reg = <6>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@7 { - reg = <7>; - ti,gain = <3>; - ti,datarate = <3>; - }; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - }; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; - status = "okay"; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&ssi1 { - #sound-dai-cells = <0>; - fsl,mode = "ac97-slave"; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_h1_vbus>; - pinctrl-names = "default"; - phy_type = "utmi"; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - phy_type = "utmi"; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - disable-wp; - cap-sd-highspeed; - no-mmc; - no-sdio; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sd; - no-sdio; - status = "okay"; }; &iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 - /* CAN1_TERM */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 - /* CAN2_SR */ - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - pinctrl_ecspi2: ecspi2grp { fsl,pins = < MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 @@ -656,113 +310,12 @@ >; }; - pinctrl_hog: hoggrp { - fsl,pins = < - /* ITU656_nRESET */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - /* CAM1_MIRROR */ - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 - /* CAM2_MIRROR */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 - /* CAM_nDETECT */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* ISB_IN1 */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 - /* ISB_nIN2 */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 - /* WARN_LIGHT */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 - /* ON2_FB */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 - /* YACO_nIRQ */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 - /* YACO_BOOT0 */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 - /* YACO_nRESET */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 - /* FORCE_ON1 */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - /* AUDIO_nRESET */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 - /* ITU656_nPDN */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - - /* HW revision detect */ - /* REV_ID0 */ - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - /* REV_ID1 is shared with PWM3 */ - /* REV_ID2 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - /* REV_ID3 */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - /* REV_ID4 */ - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - - /* New in HW revision 1 */ - /* ON1_FB */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 - /* DIP1_FB */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; - pinctrl_keypad: keypadgrp { fsl,pins = < MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 >; }; - pinctrl_leds: ledsgrp { - fsl,pins = < - /* DEBUG0 */ - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 - /* DEBUG1 */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 - /* POWER_LED */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 - >; - }; - pinctrl_rotary_ch: rotarychgrp { fsl,pins = < MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 @@ -776,77 +329,4 @@ MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 >; }; - - /* YaCO AUX Uart */ - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - /* YaCO Touchscreen UART */ - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6dl-vicut1.dts b/arch/arm/boot/dts/imx6dl-vicut1.dts index 174fd913bf96..5035d303447d 100644 --- a/arch/arm/boot/dts/imx6dl-vicut1.dts +++ b/arch/arm/boot/dts/imx6dl-vicut1.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-vicut1.dtsi" +#include "imx6qdl-vicut1-12inch.dtsi" / { model = "Kverneland UT1 Board"; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index 674af39c884a..52162e8c7274 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -55,6 +55,7 @@ panel: panel { compatible = "dataimage,scf0700c48ggu18"; power-supply = <&sw2_reg>; + backlight = <&backlight>; status = "disabled"; port { diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index fdd81fdc3f35..dc919e09a505 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -80,10 +80,13 @@ }; }; - soc { + soc: soc { ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index a0683b4aeca1..fa160a389870 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ @@ -30,89 +30,26 @@ stdout-path = "serial0:115200n8"; }; - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - power-supply = <®_3v3_sw>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - reg_pcie_switch: regulator-pcie-switch { compatible = "regulator-fixed"; - regulator-name = "pcie_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + enable-active-high; gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "pcie_switch"; startup-delay-us = <100000>; - enable-active-high; status = "okay"; }; reg_3v3_sw: regulator-3v3-sw { compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_SW"; }; }; -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - power-supply = <®_3v3_sw>; - status = "okay"; -}; - &can1 { xceiver-supply = <®_3v3_sw>; status = "okay"; @@ -123,27 +60,10 @@ status = "okay"; }; -&hdmi { - status = "okay"; -}; - /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ &i2c1 { status = "okay"; - /* - * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */ - status = "disabled"; - }; - pcie-switch@58 { compatible = "plx,pex8605"; reg = <0x58>; @@ -164,14 +84,6 @@ status = "okay"; }; -&ipu1_di1_disp1 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; -}; - &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reset_moci>; @@ -198,11 +110,11 @@ status = "okay"; }; -®_usb_otg_vbus { +®_usb_host_vbus { status = "okay"; }; -®_usb_host_vbus { +®_usb_otg_vbus { status = "okay"; }; @@ -246,28 +158,13 @@ /* MMC1 */ &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; - cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; status = "okay"; }; /* SD1 */ &usdhc2 { + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; status = "okay"; }; - -&iomuxc { - /* - * Mux the Apalis GPIOs - */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 - &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 - &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 - &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 - >; -}; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts index 86e84781cf5d..44637d606e61 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts @@ -1,274 +1,37 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include "imx6q.dtsi" -#include "imx6qdl-apalis.dtsi" +#include "imx6q-apalis-ixora-v1.2.dts" / { model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1"; - compatible = "toradex,apalis_imx6q-ixora-v1.1", - "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q", + compatible = "toradex,apalis_imx6q-ixora-v1.1", "toradex,apalis_imx6q", "fsl,imx6q"; - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - - led4-green { - label = "LED_4_GREEN"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - - led4-red { - label = "LED_4_RED"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - led5-green { - label = "LED_5_GREEN"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - led5-red { - label = "LED_5_RED"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - }; - }; }; -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - status = "okay"; -}; +/delete-node/ &eeprom; +/delete-node/ ®_3v3_vmmc; +/delete-node/ ®_can1_supply; +/delete-node/ ®_can2_supply; &can1 { - status = "okay"; + /delete-property/ xceiver-supply; }; &can2 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ -&i2c1 { - status = "okay"; - - /* - * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */ - status = "disabled"; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - status = "okay"; -}; - -&ipu1_di1_disp1 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - /* active-high meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_otg_vbus { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sound_spdif { - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; + /delete-property/ xceiver-supply; }; /* MMC1 */ &usdhc1 { + /delete-property/ cap-power-off-card; + /delete-property/ pinctrl-1; + /delete-property/ vmmc-supply; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; - cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - /* - * Mux the Apalis GPIOs - */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 - &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 - &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 - &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 - >; - - pinctrl_leds_ixora: ledsixoragrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts new file mode 100644 index 000000000000..f9f7d99bd4db --- /dev/null +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2014-2022 Toradex + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6q.dtsi" +#include "imx6qdl-apalis.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.2"; + compatible = "toradex,apalis_imx6q-ixora-v1.2", "toradex,apalis_imx6q", + "fsl,imx6q"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c3; + i2c2 = &i2c2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + + led4-green { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + label = "LED_4_GREEN"; + }; + + led4-red { + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + label = "LED_4_RED"; + }; + + led5-green { + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + label = "LED_5_GREEN"; + }; + + led5-red { + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + label = "LED_5_RED"; + }; + }; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3_vmmc"; + startup-delay-us = <100>; + }; + + reg_can1_supply: regulator-can1-supply { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can1_power>; + regulator-name = "can1_supply"; + }; + + reg_can2_supply: regulator-can2-supply { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can2_power>; + regulator-name = "can2_supply"; + }; +}; + +&can1 { + xceiver-supply = <®_can1_supply>; + status = "okay"; +}; + +&can2 { + xceiver-supply = <®_can2_supply>; + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart24_forceoff>; + + /* + * uart-2-4-on-x21-enable-hog enables the UART transceiver for Apalis + * UART2 and UART3. If one wants to disable the transceiver force + * the GPIO to output-low, if one wants to control the transceiver + * from user space delete the hog node. + */ + uart-2-4-on-x21-enable-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; /* MXM3 180 */ + output-high; + }; +}; + +/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* + * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier + * board) + */ +&i2c3 { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + /* active-high meaning opposite of regular PERST# active-low polarity */ + reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpio-active-high; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +®_usb_otg_vbus { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sound_spdif { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +/* MMC1 */ +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_4bit_sleep &pinctrl_mmc_cd_sleep>; + bus-width = <4>; + cap-power-off-card; + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; + + pinctrl_enable_can1_power: enablecan1powergrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + >; + }; + + pinctrl_enable_can2_power: enablecan2powergrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0 + >; + }; + + pinctrl_uart24_forceoff: uart24forceoffgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + >; + }; + + pinctrl_leds_ixora: ledsixoragrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; + + pinctrl_mmc_cd_sleep: mmccdslpgrp { + fsl,pins = < + /* MMC1 CD */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0 + >; + }; + + pinctrl_usdhc1_4bit_sleep: usdhc1-4bitslpgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 62e72773e53b..ce39c6a3f640 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ @@ -30,95 +30,33 @@ stdout-path = "serial0:115200n8"; }; - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - leds { compatible = "gpio-leds"; - pinctrl-names = "default"; pinctrl-0 = <&pinctrl_leds_ixora>; led4-green { - label = "LED_4_GREEN"; gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + label = "LED_4_GREEN"; }; led4-red { - label = "LED_4_RED"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + label = "LED_4_RED"; }; led5-green { - label = "LED_5_GREEN"; gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + label = "LED_5_GREEN"; }; led5-red { - label = "LED_5_RED"; gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + label = "LED_5_RED"; }; }; }; -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - status = "okay"; -}; - &can1 { status = "okay"; }; @@ -127,27 +65,10 @@ status = "okay"; }; -&hdmi { - status = "okay"; -}; - /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ &i2c1 { status = "okay"; - /* - * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */ - status = "disabled"; - }; - eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -168,14 +89,6 @@ status = "okay"; }; -&ipu1_di1_disp1 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; -}; - &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reset_moci>; @@ -201,11 +114,11 @@ status = "okay"; }; -®_usb_otg_vbus { +®_usb_host_vbus { status = "okay"; }; -®_usb_host_vbus { +®_usb_otg_vbus { status = "okay"; }; @@ -249,21 +162,13 @@ /* SD1 */ &usdhc2 { + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; status = "okay"; }; &iomuxc { - /* Mux the Apalis GPIOs */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 - &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 - &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 - &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 - >; - pinctrl_leds_ixora: ledsixoragrp { fsl,pins = < MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index 0b40f52268b3..75586299d9ca 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -178,6 +178,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi index 6330d75f8f39..f266f1b7e0cf 100644 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi @@ -142,7 +142,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: n25q032@0 { + flash: flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6q-bosch-acc.dts b/arch/arm/boot/dts/imx6q-bosch-acc.dts new file mode 100644 index 000000000000..8263bfef9bf8 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-bosch-acc.dts @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for the i.MX6-based Bosch ACC board. + * + * Copyright (C) 2016 Garz & Fricke GmbH + * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de> + * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie <lusus@denx.de> + * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com> + * Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include "imx6q.dtsi" + +/ { + model = "Bosch ACC"; + compatible = "bosch,imx6q-acc", "fsl,imx6q"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc4; + mmc1 = &usdhc2; + serial0 = &uart2; + serial1 = &uart1; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 200000>; + brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>; + num-interpolated-steps = <10>; + default-brightness-level = <60>; + power-supply = <®_lcd>; + }; + + panel { + compatible = "dataimage,fg1001l0dsswmg01"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + refclk: refclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "12mhz_refclk"; + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_PODF>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates = <0>, <12000000>, <0>; + }; + + cpus { + cpu0: cpu@0 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + + cpu1: cpu@1 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led_red: led-0 { + color = <LED_COLOR_ID_RED>; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm2 0 500000>; + }; + + led_white: led-1 { + color = <LED_COLOR_ID_WHITE>; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm3 0 500000>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_gpio_led>; + + led-2 { + color = <LED_COLOR_ID_RED>; + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_5p0: regulator-5p0 { + compatible = "regulator-fixed"; + regulator-name = "5p0"; + }; + + reg_vin: regulator-vin { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <4500000>; + regulator-max-microvolt = <4500000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_usb_h2_vbus: regulator-usb-h2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5p0> ; + regulator-always-on; + }; + + reg_vsnvs: regulator-vsnvs { + compatible = "regulator-fixed"; + regulator-name = "VSNVS_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "LCD0 POWER"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_enable>; + gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_dac: regulator-dac { + compatible = "regulator-fixed"; + regulator-name = "vref_dac"; + regulator-min-microvolt = <20000>; + regulator-max-microvolt = <20000>; + vin-supply = <®_5p0> ; + regulator-boot-on; + }; + + reg_sw4: regulator-sw4 { + compatible = "regulator-fixed"; + regulator-name = "SW4_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_sys: regulator-sys { + compatible = "regulator-fixed"; + regulator-name = "SYS_4V2"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; +}; + +®_arm { + vin-supply = <&sw2_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +®_vdd1p1 { + vin-supply = <®_vsnvs>; +}; + +®_vdd2p5 { + vin-supply = <®_vsnvs>; +}; + +®_vdd3p0 { + vin-supply = <®_vsnvs>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; + phy-mode = "rmii"; + phy-supply = <®_sw4>; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpu_vg { + status = "disabled"; +}; + +&gpu_2d { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1c_reg: sw1c { + regulator-name = "VDD_SOC (sw1abc)"; + regulator-min-microvolt = <1275000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-name = "VDD_ARM (sw2)"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5a"; + regulator-boot-on; + regulator-always-on; + + }; + + sw3b_reg: sw3b { + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5b"; + regulator-boot-on; + regulator-always-on; + + }; + + sw4_reg: sw4 { + regulator-name = "AUX 3V15 (sw4)"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + lm75: sensor@49 { + compatible = "national,lm75b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm75>; + reg = <0x49>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@51 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + eeprom_ext: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + usb3503: usb@8 { + compatible = "smsc,usb3503"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503>; + reg = <0x08>; + connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */ + intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */ + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */ + initial-mode = <1>; + clocks = <&refclk>; + clock-names = "refclk"; + refclk-frequency = <12000000>; + }; + + exc3000: touchscreen@2a { + compatible = "eeti,exc3000"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctouch>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + }; + + vcnl4035: light-sensor@60 { + compatible = "vishay,vcnl4035"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_proximity>; + reg = <0x60>; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_idle>; + pinctrl-1 = <&pinctrl_usbh2_active>; + vbus-supply = <®_usb_h2_vbus>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usb_otg_vbus>; + disable-over-current; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphynop1 { + clocks = <&clks IMX6QDL_CLK_USBPHY1>; + clock-names = "main_clk"; + vcc-supply = <®_usb_h1_vbus>; +}; + +&usbphynop2 { + vcc-supply = <®_usb_h2_vbus>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + voltage-ranges = <3300 3300>; + vmmc-supply = <®_sw4>; + fsl,wp-controller; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + voltage-ranges = <3300 3300>; + vmmc-supply = <®_sw4>; + fsl,wp-controller; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + timeout-sec = <10>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */ + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_reset_gpio_led: reset-gpio-led-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_lcd_enable: lcdenablegrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* lcd enable */ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /* sel6_8 */ + >; + }; + + pinctrl_lm75: lm75grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_proximity: proximitygrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001b0b0 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* RTC INT */ + >; + }; + + pinctrl_ctouch: ctouch-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* CTOUCH_INT */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001b0b0 /* CTOUCH_RESET */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh2_idle: usbh2-idle-grp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018 + >; + }; + + pinctrl_usbh2_active: usbh2-active-grp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018 + >; + }; + + pinctrl_usb3503: usb3503-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USB INT */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001b0b0 /* USB Reset */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 /* USB Connect */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059 + >; + }; + + pinctrl_wdog1: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index 10922375c51e..ead83091e193 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -160,7 +160,7 @@ pinctrl-0 = <&pinctrl_ecspi5>; status = "okay"; - m25_eeprom: m25p80@0 { + m25_eeprom: flash@0 { compatible = "atmel,at25"; spi-max-frequency = <10000000>; size = <0x8000>; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index bfb530f29d9d..1ad41c944b4b 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -260,7 +260,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index c713ac03b3b9..9591848cbd37 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -102,7 +102,7 @@ cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "m25p80", "jedec,spi-nor"; spi-max-frequency = <40000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/imx6q-dms-ba16.dts index 48fb47e715f6..137db38f0d27 100644 --- a/arch/arm/boot/dts/imx6q-dms-ba16.dts +++ b/arch/arm/boot/dts/imx6q-dms-ba16.dts @@ -47,7 +47,7 @@ pinctrl-0 = <&pinctrl_ecspi5>; status = "okay"; - m25_eeprom: m25p80@0 { + m25_eeprom: flash@0 { compatible = "atmel,at25256B", "atmel,at25"; spi-max-frequency = <20000000>; size = <0x8000>; diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index c63f371ede8b..78d941fef5df 100644 --- a/arch/arm/boot/dts/imx6q-evi.dts +++ b/arch/arm/boot/dts/imx6q-evi.dts @@ -146,6 +146,7 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts index ccc2487d47ca..2fda68f9d3f6 100644 --- a/arch/arm/boot/dts/imx6q-gk802.dts +++ b/arch/arm/boot/dts/imx6q-gk802.dts @@ -1,10 +1,5 @@ -/* - * Copyright (C) 2013 Philipp Zabel - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2013 Philipp Zabel /dts-v1/; #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 4cde45d5c90c..e894faba571f 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -137,7 +137,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,w25q256", "jedec,spi-nor"; spi-max-frequency = <30000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts index 05ee28388229..cc1801002394 100644 --- a/arch/arm/boot/dts/imx6q-marsboard.dts +++ b/arch/arm/boot/dts/imx6q-marsboard.dts @@ -100,7 +100,7 @@ cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts index 55692c73943d..f08b37010291 100644 --- a/arch/arm/boot/dts/imx6q-mccmon6.dts +++ b/arch/arm/boot/dts/imx6q-mccmon6.dts @@ -100,8 +100,10 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index 225cf6b7a7a4..ee8c0bd3ecfd 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -86,7 +86,7 @@ linux,code = <KEY_POWER>; }; - lid { + lid-event { label = "Lid"; gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; linux,input-type = <5>; /* EV_SW */ @@ -99,7 +99,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_leds_novena>; - heartbeat { + led-heartbeat { label = "novena:white:panel"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts index 7a33e54cc0f1..bad8d831e64e 100644 --- a/arch/arm/boot/dts/imx6q-pistachio.dts +++ b/arch/arm/boot/dts/imx6q-pistachio.dts @@ -100,7 +100,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + key-power { label = "Power Button"; gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; wakeup-source; diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/imx6q-rex-pro.dts index 1767e1a3cd53..271f4b2d9b9f 100644 --- a/arch/arm/boot/dts/imx6q-rex-pro.dts +++ b/arch/arm/boot/dts/imx6q-rex-pro.dts @@ -19,7 +19,7 @@ }; &ecspi3 { - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,sst25vf032b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index dc51262e7b2f..7c6a2f234ccb 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -1,43 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts b/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts index 7f1f19b74bfa..a3f247c722b4 100644 --- a/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts +++ b/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts @@ -125,3 +125,9 @@ >; }; }; + +®_tft_vcom { + regulator-min-microvolt = <3160000>; + regulator-max-microvolt = <3160000>; + voltage-table = <3160000 73>; +}; diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index 343364d3e4f7..8daef65d5bb3 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -159,7 +159,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - rtc: ds1307@68 { + rtc: rtc@68 { compatible = "dallas,ds1307"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts index d16ff2083d62..ad59b23ef27a 100644 --- a/arch/arm/boot/dts/imx6q-utilite-pro.dts +++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts @@ -89,7 +89,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + key-power { label = "Power Button"; gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts index 63550351340d..2290c1237634 100644 --- a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts +++ b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts @@ -28,7 +28,7 @@ compatible = "gpio-keys"; autorepeat; - back { + key-back { gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; label = "Key Back"; @@ -37,7 +37,7 @@ wakeup-source; }; - home { + key-home { gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; label = "Key Home"; @@ -46,7 +46,7 @@ wakeup-source; }; - menu { + key-menu { gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; label = "Key Menu"; diff --git a/arch/arm/boot/dts/imx6q-vicut1.dts b/arch/arm/boot/dts/imx6q-vicut1.dts index 0a4e251be162..dd91aff3f9e2 100644 --- a/arch/arm/boot/dts/imx6q-vicut1.dts +++ b/arch/arm/boot/dts/imx6q-vicut1.dts @@ -6,12 +6,9 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-vicut1.dtsi" +#include "imx6qdl-vicut1-12inch.dtsi" / { model = "Kverneland UT1Q Board"; compatible = "kvg,vicut1q", "fsl,imx6q"; }; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-yapp4-crux.dts b/arch/arm/boot/dts/imx6q-yapp4-crux.dts index 15f4824a5142..bddf3822ebf7 100644 --- a/arch/arm/boot/dts/imx6q-yapp4-crux.dts +++ b/arch/arm/boot/dts/imx6q-yapp4-crux.dts @@ -33,6 +33,10 @@ status = "okay"; }; +®_pu { + regulator-always-on; +}; + ®_usb_h1_vbus { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 9caba4529c71..df86049a695b 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -159,14 +159,17 @@ }; }; - soc { + soc: soc { ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x40000>; + ranges = <0 0x00900000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - bus@2000000 { /* AIPS1 */ + aips1: bus@2000000 { /* AIPS1 */ spba-bus@2000000 { ecspi5: spi@2018000 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index ed2739e39085..7c17b91f0965 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -1,11 +1,12 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> / { model = "Toradex Apalis iMX6Q/D Module"; @@ -19,88 +20,182 @@ backlight: backlight { compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm4 0 5000000>; - enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + power-supply = <®_module_3v3>; + pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + clk_ov5640_osc: clk-ov5640-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + debounce-interval = <10>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "disabled"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di1_disp1>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel_dpi: panel-dpi { + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + panel_lvds: panel-lvds { + compatible = "panel-lvds"; + backlight = <&backlight>; status = "disabled"; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; }; reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3"; }; reg_module_3v3_audio: regulator-module-3v3-audio { compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO"; - regulator-min-microvolt = <3300000>; + regulator-always-on; regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_AUDIO"; + }; + + reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd { + compatible = "regulator-fixed"; regulator-always-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "DOVDD/DVDD_1.8V"; + /* Note: The CSI module uses on-board 3.3V_SW supply */ + vin-supply = <®_module_3v3>; + }; + + reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "AVDD/AFVDD_2.8V"; + /* Note: The CSI module uses on-board 3.3V_SW supply */ + vin-supply = <®_module_3v3>; }; reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_otg_vbus"; status = "disabled"; }; /* on module USB hub */ reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; - regulator-name = "usb_host_vbus_hub"; - regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_host_vbus_hub"; startup-delay-us = <2000>; - enable-active-high; status = "okay"; }; reg_usb_host_vbus: regulator-usb-host-vbus { compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_host_vbus"; vin-supply = <®_usb_host_vbus_hub>; status = "disabled"; }; sound { compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6q-apalis-sgtl5000"; - ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = "LINE_IN", "Line In Jack", "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; + model = "imx6q-apalis-sgtl5000"; mux-ext-port = <4>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; }; sound_spdif: sound-spdif { compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; spdif-controller = <&spdif>; spdif-in; spdif-out; + model = "imx-spdif"; status = "disabled"; }; }; @@ -125,6 +220,10 @@ status = "disabled"; }; +&clks { + fsl,pmic-stby-poweroff; +}; + /* Apalis SPI1 */ &ecspi1 { cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; @@ -141,6 +240,214 @@ status = "disabled"; }; +&gpio1 { + gpio-line-names = "MXM3_84", + "MXM3_4", + "MXM3_15/GPIO7", + "MXM3_96", + "MXM3_37", + "", + "MXM3_17/GPIO8", + "MXM3_14", + "MXM3_12", + "MXM3_2", + "MXM3_184", + "MXM3_180", + "MXM3_178", + "MXM3_176", + "MXM3_188", + "MXM3_186", + "MXM3_160", + "MXM3_162", + "MXM3_150", + "MXM3_144", + "MXM3_154", + "MXM3_146", + "", + "", + "MXM3_72"; +}; + +&gpio2 { + gpio-line-names = "MXM3_148", + "MXM3_152", + "MXM3_156", + "MXM3_158", + "MXM3_1/GPIO1", + "MXM3_3/GPIO2", + "MXM3_5/GPIO3", + "MXM3_7/GPIO4", + "MXM3_95", + "MXM3_6", + "MXM3_8", + "MXM3_123", + "MXM3_126", + "MXM3_128", + "MXM3_130", + "MXM3_132", + "MXM3_253", + "MXM3_251", + "MXM3_283", + "MXM3_281", + "MXM3_279", + "MXM3_277", + "MXM3_243", + "MXM3_235", + "MXM3_231", + "MXM3_229", + "MXM3_233", + "MXM3_198", + "MXM3_275", + "MXM3_273", + "MXM3_207", + "MXM3_122"; +}; + +&gpio3 { + gpio-line-names = "MXM3_271", + "MXM3_269", + "MXM3_301", + "MXM3_299", + "MXM3_297", + "MXM3_295", + "MXM3_293", + "MXM3_291", + "MXM3_289", + "MXM3_287", + "MXM3_249", + "MXM3_247", + "MXM3_245", + "MXM3_286", + "MXM3_239", + "MXM3_35", + "MXM3_205", + "MXM3_203", + "MXM3_201", + "MXM3_116", + "MXM3_114", + "MXM3_262", + "MXM3_274", + "MXM3_124", + "MXM3_110", + "MXM3_120", + "MXM3_263", + "MXM3_265", + "", + "MXM3_135", + "MXM3_261", + "MXM3_259"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "MXM3_194", + "MXM3_136", + "MXM3_134", + "MXM3_140", + "MXM3_138", + "", + "MXM3_220", + "", + "", + "MXM3_18", + "MXM3_16", + "", + "", + "MXM3_214", + "MXM3_216", + "MXM3_164"; +}; + +&gpio5 { + gpio-line-names = "MXM3_159", + "", + "", + "", + "MXM3_257", + "", + "", + "", + "", + "", + "MXM3_200", + "MXM3_196", + "MXM3_204", + "MXM3_202", + "", + "", + "", + "", + "MXM3_191", + "MXM3_197", + "MXM3_77", + "MXM3_195", + "MXM3_221", + "MXM3_225", + "MXM3_223", + "MXM3_227", + "MXM3_209", + "MXM3_211", + "MXM3_118", + "MXM3_112", + "MXM3_187", + "MXM3_185"; +}; + +&gpio6 { + gpio-line-names = "MXM3_183", + "MXM3_181", + "MXM3_179", + "MXM3_177", + "MXM3_175", + "MXM3_173", + "MXM3_255", + "MXM3_83", + "MXM3_91", + "MXM3_13/GPIO6", + "MXM3_11/GPIO5", + "MXM3_79", + "", + "", + "MXM3_190", + "MXM3_193", + "MXM3_89"; +}; + +&gpio7 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_99", + "MXM3_85", + "MXM3_217", + "MXM3_215"; +}; + +&gpr { + ipu1_csi0_mux { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@1 { + reg = <1>; + ipu1_csi0_mux_from_parallel_sensor: endpoint { + remote-endpoint = <&adv7280_to_ipu1_csi0_mux>; + }; + }; + }; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; @@ -177,6 +484,16 @@ scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; + + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + /* These GPIOs are muxed with the iomuxc node */ + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* MXM3_11 */ + reg = <0x4a>; + reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* MXM3_13 */ + status = "disabled"; + }; }; /* @@ -192,101 +509,105 @@ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; + fsl,pmic-stby-poweroff; reg = <0x08>; regulators { sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; regulator-ramp-delay = <6250>; }; sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; regulator-ramp-delay = <6250>; }; sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1975000>; + regulator-min-microvolt = <400000>; }; swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5150000>; + regulator-min-microvolt = <5000000>; }; snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <1000000>; }; vref_reg: vrefddr { - regulator-boot-on; regulator-always-on; + regulator-boot-on; }; vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1550000>; + regulator-min-microvolt = <800000>; }; vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1550000>; + regulator-min-microvolt = <800000>; }; vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; }; vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; }; }; codec: sgtl5000@a { compatible = "fsl,sgtl5000"; - reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; VDDA-supply = <®_module_3v3_audio>; VDDIO-supply = <®_module_3v3>; VDDD-supply = <&vgen4_reg>; @@ -295,15 +616,15 @@ /* STMPE811 touch screen controller */ stmpe811@41 { compatible = "st,stmpe811"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch_int>; - reg = <0x41>; + blocks = <0x5>; + id = <0>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio4>; interrupt-controller; - id = <0>; - blocks = <0x5>; + interrupt-parent = <&gpio4>; irq-trigger = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + reg = <0x41>; /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; /* 12-bit ADC */ @@ -313,7 +634,7 @@ /* ADC conversion time: 80 clocks */ st,sample-time = <4>; - stmpe_touchscreen: stmpe-touchscreen { + stmpe_ts: stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ st,ave-ctrl = <3>; @@ -328,13 +649,14 @@ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; + status = "disabled"; }; - stmpe_adc: stmpe-adc { + stmpe_adc: stmpe_adc { compatible = "st,stmpe-adc"; + #io-channel-cells = <1>; /* forbid to use ADC channels 3-0 (touch) */ st,norequest-mask = <0x0F>; - #io-channel-cells = <1>; }; }; }; @@ -351,6 +673,90 @@ scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; + + adv_7280: adv7280@21 { + compatible = "adi,adv7280"; + adv,force-bt656-4; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + reg = <0x21>; + status = "disabled"; + + port { + adv7280_to_ipu1_csi0_mux: endpoint { + bus-width = <8>; + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + }; + }; + }; + + ov5640_csi_cam: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + AVDD-supply = <®_ov5640_2v8_a_vdd>; + DOVDD-supply = <®_ov5640_1v8_d_o_vdd>; + DVDD-supply = <®_ov5640_1v8_d_o_vdd>; + clock-names = "xclk"; + clocks = <&clks IMX6QDL_CLK_CKO2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cam_mclk>; + /* These GPIOs are muxed with the iomuxc node */ + powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + reg = <0x3c>; + reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + status = "disabled"; + + port { + ov5640_to_mipi_csi2: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&mipi_csi_from_ov5640>; + }; + }; + }; +}; + +&ipu1_di1_disp1 { + remote-endpoint = <&lcd_display_in>; +}; + +&ldb { + lvds-channel@0 { + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + }; + }; + }; +}; + +&mipi_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_csi_from_ov5640: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&ov5640_to_mipi_csi2>; + }; + }; }; &pwm1 { @@ -372,7 +778,6 @@ }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "disabled"; @@ -389,72 +794,73 @@ }; &uart1 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; - fsl,dte-mode; uart-has-rtscts; status = "disabled"; }; &uart2 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2_dte>; - fsl,dte-mode; uart-has-rtscts; status = "disabled"; }; &uart4 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4_dte>; - fsl,dte-mode; status = "disabled"; }; &uart5 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5_dte>; - fsl,dte-mode; status = "disabled"; }; &usbotg { + disable-over-current; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; status = "disabled"; }; /* MMC1 */ &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; - vqmmc-supply = <®_module_3v3>; bus-width = <8>; + cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; disable-wp; no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; + vqmmc-supply = <®_module_3v3>; status = "disabled"; }; /* SD1 */ &usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vqmmc-supply = <®_module_3v3>; bus-width = <4>; disable-wp; no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vqmmc-supply = <®_module_3v3>; status = "disabled"; }; /* eMMC */ &usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_module_3v3>; bus-width = <8>; no-1-8-v; non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vqmmc-supply = <®_module_3v3>; status = "okay"; }; @@ -463,49 +869,57 @@ }; &iomuxc { - pinctrl_apalis_gpio1: gpio2io04grp { + /* Mux the Apalis GPIOs */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 + &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 + &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 + &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 + >; + + pinctrl_apalis_gpio1: apalisgpio1grp { fsl,pins = < MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 >; }; - pinctrl_apalis_gpio2: gpio2io05grp { + pinctrl_apalis_gpio2: apalisgpio2grp { fsl,pins = < MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 >; }; - pinctrl_apalis_gpio3: gpio2io06grp { + pinctrl_apalis_gpio3: apalisgpio3grp { fsl,pins = < MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 >; }; - pinctrl_apalis_gpio4: gpio2io07grp { + pinctrl_apalis_gpio4: apalisgpio4grp { fsl,pins = < MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 >; }; - pinctrl_apalis_gpio5: gpio6io10grp { + pinctrl_apalis_gpio5: apalisgpio5grp { fsl,pins = < MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 >; }; - pinctrl_apalis_gpio6: gpio6io09grp { + pinctrl_apalis_gpio6: apalisgpio6grp { fsl,pins = < MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 >; }; - pinctrl_apalis_gpio7: gpio1io02grp { + pinctrl_apalis_gpio7: apalisgpio7grp { fsl,pins = < MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 >; }; - pinctrl_apalis_gpio8: gpio1io06grp { + pinctrl_apalis_gpio8: apalisgpio8grp { fsl,pins = < MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 >; @@ -517,8 +931,6 @@ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 >; }; @@ -600,7 +1012,7 @@ >; }; - pinctrl_gpio_bl_on: gpioblon { + pinctrl_gpio_bl_on: gpioblongrp { fsl,pins = < MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 >; @@ -745,7 +1157,7 @@ >; }; - pinctrl_mmc_cd: gpiommccdgrp { + pinctrl_mmc_cd: mmccdgrp { fsl,pins = < /* MMC1 CD */ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 @@ -776,41 +1188,47 @@ >; }; - pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { + pinctrl_regulator_usbh_pwr: regusbhpwrgrp { fsl,pins = < /* USBH_EN */ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 >; }; - pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp { + pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp { fsl,pins = < /* USBH_HUB_EN */ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 >; }; - pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp { + pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp { fsl,pins = < /* USBO1 power en */ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 >; }; - pinctrl_reset_moci: gpioresetmocigrp { + pinctrl_reset_moci: resetmocigrp { fsl,pins = < /* RESET_MOCI control */ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 >; }; - pinctrl_sd_cd: gpiosdcdgrp { + pinctrl_sd_cd: sdcdgrp { fsl,pins = < /* SD1 CD */ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 >; }; + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 + >; + }; + pinctrl_spdif: spdifgrp { fsl,pins = < MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 @@ -818,13 +1236,22 @@ >; }; - pinctrl_touch_int: gpiotouchintgrp { + pinctrl_touch_int: touchintgrp { fsl,pins = < /* STMPE811 interrupt */ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 >; }; + /* Additional DTR, DSR, DCD */ + pinctrl_uart1_ctrl: uart1ctrlgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + pinctrl_uart1_dce: uart1dcegrp { fsl,pins = < MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 @@ -842,15 +1269,6 @@ >; }; - /* Additional DTR, DSR, DCD */ - pinctrl_uart1_ctrl: uart1ctrlgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 - >; - }; - pinctrl_uart2_dce: uart2dcegrp { fsl,pins = < MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 @@ -904,7 +1322,7 @@ >; }; - pinctrl_usdhc1_4bit: usdhc1grp_4bit { + pinctrl_usdhc1_4bit: usdhc1-4bitgrp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 @@ -915,7 +1333,7 @@ >; }; - pinctrl_usdhc1_8bit: usdhc1grp_8bit { + pinctrl_usdhc1_8bit: usdhc1-8bitgrp { fsl,pins = < MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi index e21f6ac864e5..baa197c90060 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi @@ -96,7 +96,7 @@ pinctrl-0 = <&pinctrl_ecspi4>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q128a11", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi index 563bf9d44fe0..6b64b2fc3995 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi @@ -131,7 +131,7 @@ pinctrl-0 = <&pinctrl_ecspi4>; status = "okay"; - flash: m25p80@1 { + flash: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q128a11", "jedec,spi-nor"; @@ -154,112 +154,112 @@ regulators { bcore1 { regulator-name = "bcore1"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; bcore2 { regulator-name = "bcore2"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; bpro { regulator-name = "bpro"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; bperi { regulator-name = "bperi"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; bmem { regulator-name = "bmem"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; ldo2 { regulator-name = "ldo2"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1800000>; }; ldo3 { regulator-name = "ldo3"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; ldo4 { regulator-name = "ldo4"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; ldo5 { regulator-name = "ldo5"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; ldo6 { regulator-name = "ldo6"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; ldo7 { regulator-name = "ldo7"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; ldo8 { regulator-name = "ldo8"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; ldo9 { regulator-name = "ldo9"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; ldo10 { regulator-name = "ldo10"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; ldo11 { regulator-name = "ldo11"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <300000>; regulator-max-microvolt = <3300000>; }; bio { regulator-name = "bio"; - regulator-always-on = <1>; + regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi b/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi deleted file mode 100644 index 7672fbfc29be..000000000000 --- a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -&iomuxc { - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 - >; - }; -}; - -/* Colibri MMC */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; - vmmc-supply = <®_module_3v3>; - vqmmc-supply = <&vgen3_reg>; - wakeup-source; - keep-power-in-suspend; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; -}; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 4e2a309c93fa..023e76215064 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> / { model = "Toradex Colibri iMX6DL/S Module"; @@ -13,11 +14,77 @@ backlight: backlight { compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm3 0 5000000>; - enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + power-supply = <®_module_3v3>; + pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + debounce-interval = <10>; + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ + label = "Wake-Up"; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + + panel_dpi: panel-dpi { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; }; reg_module_3v3: regulator-module-3v3 { @@ -38,36 +105,36 @@ reg_usb_host_vbus: regulator-usb-host-vbus { compatible = "regulator-fixed"; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ + regulator-min-microvolt = <5000000>; + regulator-name = "usb_host_vbus"; status = "disabled"; }; sound { compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6dl-colibri-sgtl5000"; - ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HP_OUT", "LINE_IN", "Line In Jack", "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias"; + model = "imx6dl-colibri-sgtl5000"; mux-int-port = <1>; mux-ext-port = <5>; + ssi-controller = <&ssi1>; }; /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ sound_spdif: sound-spdif { compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; spdif-controller = <&spdif>; spdif-in; spdif-out; + model = "imx-spdif"; status = "disabled"; }; }; @@ -92,6 +159,10 @@ status = "disabled"; }; +&clks { + fsl,pmic-stby-poweroff; +}; + /* Colibri SSP */ &ecspi4 { cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; @@ -101,10 +172,10 @@ }; &fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; phy-handle = <ðphy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; status = "okay"; mdio { @@ -118,6 +189,224 @@ }; }; +&gpio1 { + gpio-line-names = "", + "SODIMM_67", + "SODIMM_180", + "SODIMM_196", + "SODIMM_174", + "SODIMM_176", + "SODIMM_194", + "SODIMM_55", + "SODIMM_63", + "SODIMM_28", + "SODIMM_93", + "SODIMM_69", + "SODIMM_99", + "SODIMM_130", + "SODIMM_106", + "SODIMM_98", + "SODIMM_192", + "SODIMM_49", + "SODIMM_190", + "SODIMM_51", + "SODIMM_47", + "SODIMM_53", + "", + "SODIMM_22"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_132", + "SODIMM_134", + "SODIMM_135", + "SODIMM_133", + "SODIMM_102", + "SODIMM_43", + "SODIMM_127", + "SODIMM_37", + "SODIMM_104", + "SODIMM_59", + "SODIMM_30", + "SODIMM_100", + "SODIMM_38", + "SODIMM_34", + "SODIMM_32", + "SODIMM_36", + "SODIMM_59", + "SODIMM_67", + "SODIMM_97", + "SODIMM_79", + "SODIMM_103", + "SODIMM_101", + "SODIMM_45", + "SODIMM_105", + "SODIMM_107", + "SODIMM_91", + "SODIMM_89", + "SODIMM_150", + "SODIMM_126", + "SODIMM_128", + "", + "SODIMM_94"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_111", + "SODIMM_113", + "SODIMM_115", + "SODIMM_117", + "SODIMM_119", + "SODIMM_121", + "SODIMM_123", + "SODIMM_125", + "SODIMM_110", + "SODIMM_112", + "SODIMM_114", + "SODIMM_116", + "SODIMM_118", + "SODIMM_120", + "SODIMM_122", + "SODIMM_124", + "", + "SODIMM_96", + "SODIMM_77", + "SODIMM_25", + "SODIMM_27", + "SODIMM_88", + "SODIMM_90", + "SODIMM_31", + "SODIMM_23", + "SODIMM_29", + "SODIMM_71", + "SODIMM_73", + "SODIMM_92", + "SODIMM_81", + "SODIMM_131", + "SODIMM_129"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "SODIMM_168", + "", + "", + "", + "", + "SODIMM_184", + "SODIMM_186", + "HDMI_15", + "HDMI_16", + "SODIMM_178", + "SODIMM_188", + "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "SODIMM_24", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_95", + "", + "SODIMM_86", + "", + "SODIMM_65", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_136", + "SODIMM_138", + "SODIMM_140", + "SODIMM_142", + "SODIMM_144", + "SODIMM_146", + "SODIMM_172", + "SODIMM_170", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153", + "SODIMM_155", + "SODIMM_157", + "SODIMM_159", + "SODIMM_161", + "SODIMM_163", + "SODIMM_33", + "SODIMM_35", + "SODIMM_165", + "SODIMM_167"; +}; + +&gpio6 { + gpio-line-names = "SODIMM_169", + "SODIMM_171", + "SODIMM_173", + "SODIMM_175", + "SODIMM_177", + "SODIMM_179", + "SODIMM_85", + "SODIMM_166", + "SODIMM_160", + "SODIMM_162", + "SODIMM_158", + "SODIMM_164", + "", + "", + "SODIMM_156", + "SODIMM_75", + "SODIMM_154", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_152"; +}; + +&gpio7 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_19", + "SODIMM_21", + "", + "SODIMM_137"; +}; + &hdmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi_ddc>; @@ -132,65 +421,66 @@ clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-0 = <&pinctrl_i2c2_gpio>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; + fsl,pmic-stby-poweroff; reg = <0x08>; regulators { sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; regulator-ramp-delay = <6250>; }; sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; regulator-ramp-delay = <6250>; }; sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1975000>; + regulator-min-microvolt = <400000>; }; swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5150000>; + regulator-min-microvolt = <5000000>; }; snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <1000000>; }; vref_reg: vrefddr { - regulator-boot-on; regulator-always-on; + regulator-boot-on; }; /* vgen1: unused */ vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1550000>; + regulator-min-microvolt = <800000>; }; /* @@ -198,57 +488,60 @@ * the i.MX 6 NVCC_SD1. */ vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; }; vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; }; }; codec: sgtl5000@a { compatible = "fsl,sgtl5000"; - reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; + lrclk-strength = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDIO-supply = <®_module_3v3>; VDDD-supply = <&vgen4_reg>; - lrclk-strength = <3>; }; /* STMPE811 touch screen controller */ stmpe811@41 { compatible = "st,stmpe811"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch_int>; - reg = <0x41>; + blocks = <0x5>; interrupts = <20 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio6>; interrupt-controller; id = <0>; - blocks = <0x5>; irq-trigger = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + reg = <0x41>; /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; /* 12-bit ADC */ @@ -258,7 +551,7 @@ /* ADC converstion time: 80 clocks */ st,sample-time = <4>; - stmpe_touchscreen { + stmpe_ts: stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ st,ave-ctrl = <3>; @@ -273,9 +566,10 @@ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; + status = "disabled"; }; - stmpe_adc { + stmpe_adc: stmpe_adc { compatible = "st,stmpe-adc"; /* forbid to use ADC channels 3-0 (touch) */ st,norequest-mask = <0x0F>; @@ -294,6 +588,21 @@ scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; + + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + interrupt-parent = <&gpio2>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_conn>; + reg = <0x4a>; + reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* SODIMM 106 */ + status = "disabled"; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; }; /* Colibri PWM<B> */ @@ -312,7 +621,6 @@ /* Colibri PWM<A> */ &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "disabled"; @@ -338,27 +646,27 @@ /* Colibri UART_A */ &uart1 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; - fsl,dte-mode; uart-has-rtscts; status = "disabled"; }; /* Colibri UART_B */ &uart2 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2_dte>; - fsl,dte-mode; uart-has-rtscts; status = "disabled"; }; /* Colibri UART_C */ &uart3 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_dte>; - fsl,dte-mode; status = "disabled"; }; @@ -370,24 +678,28 @@ /* Colibri MMC */ &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ - disable-wp; - vqmmc-supply = <®_module_3v3>; bus-width = <4>; no-1-8-v; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; + pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <&vgen3_reg>; status = "disabled"; }; /* eMMC */ &usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_module_3v3>; bus-width = <8>; no-1-8-v; non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vqmmc-supply = <®_module_3v3>; status = "okay"; }; @@ -405,14 +717,34 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh_oc_1>; + /* Atmel MXT touchsceen + Capacitive Touch Adapter */ + /* NOTE: This pin group conflicts with pin groups + * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously. + */ + pinctrl_atmel_adap: atmeladaptergrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */ + >; + }; + + /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ + /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and + * pinctrl_weim_cs2. Don't use them simultaneously. + */ + pinctrl_atmel_conn: atmelconnectorgrp { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */ + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */ + >; + }; + pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 >; }; @@ -423,28 +755,52 @@ >; }; + /* CSI pins used as GPIOs */ + pinctrl_csi_gpio_1: csigpio1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + + pinctrl_csi_gpio_2: csigpio2grp { + fsl,pins = < + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 + >; + }; + pinctrl_ecspi4: ecspi4grp { fsl,pins = < + /* SPI CS */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - /* SPI CS */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 >; }; pinctrl_enet: enetgrp { fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) + MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) >; }; @@ -462,13 +818,32 @@ >; }; - pinctrl_gpio_bl_on: gpioblon { + pinctrl_gpio_1: gpio1grp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; + pinctrl_gpio_2: gpio2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_gpio_bl_on: gpioblongrp { fsl,pins = < MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 >; }; - pinctrl_gpio_keys: gpiokeys { + pinctrl_gpio_keys: gpiokeysgrp { fsl,pins = < MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 >; @@ -483,15 +858,15 @@ pinctrl_i2c2: i2c2grp { fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 >; }; - pinctrl_i2c2_gpio: i2c2grp { + pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = < - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 >; }; @@ -523,8 +898,8 @@ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 /* Disable PWM pins on camera interface */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 >; }; @@ -555,19 +930,34 @@ >; }; - pinctrl_mic_gnd: gpiomicgnd { + pinctrl_lvds_transceiver: lvdstxgrp { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */ + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */ + >; + }; + + pinctrl_mic_gnd: micgndgrp { fsl,pins = < /* Controls Mic GND, PU or '1' pull Mic GND to GND */ MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 >; }; - pinctrl_mmc_cd: gpiommccd { + pinctrl_mmc_cd: mmccdgrp { fsl,pins = < MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 >; }; + pinctrl_mmc_cd_sleep: mmccdslpgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 @@ -576,15 +966,15 @@ pinctrl_pwm2: pwm2grp { fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 >; }; pinctrl_pwm3: pwm3grp { fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 >; }; @@ -601,10 +991,10 @@ >; }; - pinctrl_usbh_oc_1: usbhoc1grp { + pinctrl_sgtl5000: sgtl5000grp { fsl,pins = < - /* USBH_OC */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 >; }; @@ -650,9 +1040,9 @@ pinctrl_uart2_dte: uart2dtegrp { fsl,pins = < MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 >; }; @@ -667,20 +1057,27 @@ fsl,pins = < /* USBC_DET */ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* USBC_DET_EN */ - MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 /* USBC_DET_OVERWRITE */ MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 + /* USBC_DET_EN */ + MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 >; }; - pinctrl_usbc_id_1: usbc_id-1 { + pinctrl_usbc_id_1: usbcid1grp { fsl,pins = < /* USBC_ID */ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 >; }; + pinctrl_usbh_oc_1: usbhoc1grp { + fsl,pins = < + /* USBH_OC */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 @@ -692,6 +1089,40 @@ >; }; + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 + >; + }; + + /* avoid backfeeding with removed card power */ + pinctrl_usdhc1_sleep: usdhc1sleepgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -730,135 +1161,136 @@ >; }; - pinctrl_weim_sram: weimsramgrp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 - /* Data */ - MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 - MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 - MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 - MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 - MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 - /* Address */ - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 - >; - }; - - pinctrl_weim_rdnwr: weimrdnwr { - fsl,pins = < - MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 - MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 - >; - }; - - pinctrl_weim_npwe: weimnpwe { - fsl,pins = < - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 - MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 - >; - }; - /* ADDRESS[16:18] [25] used as GPIO */ - pinctrl_weim_gpio_1: weimgpio-1 { + pinctrl_weim_gpio_1: weimgpio1grp { fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 >; }; /* ADDRESS[19:24] used as GPIO */ - pinctrl_weim_gpio_2: weimgpio-2 { + pinctrl_weim_gpio_2: weimgpio2grp { fsl,pins = < - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 >; }; /* DATA[16:31] used as GPIO */ - pinctrl_weim_gpio_3: weimgpio-3 { + pinctrl_weim_gpio_3: weimgpio3grp { fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 >; }; /* DQM[0:3] used as GPIO */ - pinctrl_weim_gpio_4: weimgpio-4 { + pinctrl_weim_gpio_4: weimgpio4grp { fsl,pins = < MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 >; }; /* RDY used as GPIO */ - pinctrl_weim_gpio_5: weimgpio-5 { + pinctrl_weim_gpio_5: weimgpio5grp { fsl,pins = < MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 >; }; /* ADDRESS[16] DATA[30] used as GPIO */ - pinctrl_weim_gpio_6: weimgpio-6 { + pinctrl_weim_gpio_6: weimgpio6grp { fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_weim_npwe: weimnpwegrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 + >; + }; + + pinctrl_weim_sram: weimsramgrp { + fsl,pins = < + /* Data */ + MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 + /* Address */ + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + /* Ctrl */ + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 + >; + }; + + pinctrl_weim_rdnwr: weimrdnwrgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 >; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi index 648f5fcb72e6..2c1d6f28e695 100644 --- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi @@ -35,7 +35,7 @@ pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf040b", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi index dc89b554e694..6248b126b557 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi @@ -4,7 +4,10 @@ * Copyright (C) 2018 Marek Vasut <marex@denx.de> */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> / { chosen { @@ -329,37 +332,4 @@ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */ >; }; - - pinctrl_ipu1_lcdif: ipu1-lcdif-grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi index 5befbe13d1a3..eaa87b333164 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi @@ -667,6 +667,39 @@ >; }; + pinctrl_ipu1_lcdif: ipu1-lcdif-grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 + >; + }; + pinctrl_pcie: pcie-grp { fsl,pins = < MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */ diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index b1df2beb2832..728810b9d677 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -137,6 +137,16 @@ regulator-always-on; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg_vbus"; @@ -170,6 +180,7 @@ &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; status = "okay"; }; @@ -612,7 +623,6 @@ fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ >; }; @@ -702,6 +712,12 @@ >; }; + pinctrl_reg_can1: regcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index a0710d562766..6c0c109046d8 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -129,6 +129,16 @@ regulator-always-on; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usb_h1_vbus: regulator-usb-h1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_h1_vbus"; @@ -170,6 +180,7 @@ &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; status = "okay"; }; @@ -600,7 +611,6 @@ fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ >; }; @@ -691,6 +701,12 @@ >; }; + pinctrl_reg_can1: regcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index cda48bf2f168..a9b04f9f1c2b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -137,6 +137,16 @@ regulator-always-on; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usb_h1_vbus: regulator@2 { compatible = "regulator-fixed"; reg = <2>; @@ -200,6 +210,7 @@ &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; status = "okay"; }; @@ -687,7 +698,6 @@ fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ >; }; @@ -786,6 +796,12 @@ >; }; + pinctrl_reg_can1: regcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi index 68e5ab2e27e2..6bb4855d13ce 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi @@ -29,7 +29,7 @@ user-pb { label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi index 8e23cec7149e..696427b487f0 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi @@ -26,7 +26,7 @@ user-pb { label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi index b167b33bd108..85aeebc9485d 100644 --- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi @@ -51,16 +51,6 @@ vin-supply = <®_3p3v_s5>; }; - reg_3p3v_s0: regulator-3p3v-s0 { - compatible = "regulator-fixed"; - regulator-name = "V_3V3_S0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <®_3p3v_s5>; - }; - reg_3p3v_s5: regulator-3p3v-s5 { compatible = "regulator-fixed"; regulator-name = "V_3V3_S5"; @@ -258,8 +248,8 @@ status = "okay"; /* default boot source: workaround #1 for errata ERR006282 */ - smarc_flash: spi-flash@0 { - compatible = "winbond,w25q16dw", "jedec,spi-nor"; + smarc_flash: flash@0 { + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; }; @@ -270,7 +260,23 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + phy-handle = <ðphy>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; }; &i2c_intern { @@ -397,7 +403,7 @@ /* HDMI_CTRL */ &i2c2 { - clock-frequency = <375000>; + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; }; diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/imx6qdl-mba6.dtsi index daf76345b179..78555a618851 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-mba6.dtsi @@ -17,6 +17,7 @@ mmc1 = &usdhc2; /delete-property/ mmc2; /delete-property/ mmc3; + rtc0 = &rtc0; }; chosen { @@ -39,18 +40,21 @@ label = "s6"; linux,code = <KEY_F6>; gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + wakeup-source; }; button2 { label = "s7"; linux,code = <KEY_F7>; gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + wakeup-source; }; button3 { label = "s8"; linux,code = <KEY_F8>; gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; @@ -82,6 +86,8 @@ reg_pcie: regulator-pcie { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regpcie>; regulator-name = "supply-pcie"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -238,7 +244,6 @@ status = "okay"; }; - &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; @@ -392,7 +397,6 @@ pinctrl_hog: hoggrp { fsl,pins = < - /* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 @@ -433,8 +437,6 @@ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */ - /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */ >; }; @@ -459,6 +461,13 @@ >; }; + pinctrl_regpcie: regpciegrp { + fsl,pins = < + /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */ + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 diff --git a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi index a61f2705a340..df8fa169e9f6 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi +++ b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi @@ -6,12 +6,6 @@ * Author: Markus Niebel <Markus.Niebel@tq-group.com> */ -/ { - aliases { - rtc0 = &rtc0; - }; -}; - &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>; diff --git a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi index 9f9f7037c9e4..7d1cd7454c7f 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi +++ b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi @@ -6,12 +6,6 @@ * Author: Markus Niebel <Markus.Niebel@tq-group.com> */ -/ { - aliases { - rtc0 = &rtc0; - }; -}; - &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; @@ -19,8 +13,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_recovery>; + scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index ac34709e9741..a53a5d0766a5 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -179,7 +179,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; @@ -192,6 +192,7 @@ phy-mode = "rgmii"; phy-handle = <ðphy>; phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index c96f4d7e1e0d..57c21a01f126 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -321,7 +321,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; @@ -334,6 +334,7 @@ phy-mode = "rgmii"; phy-handle = <ðphy>; phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index 92d09a3ebe0e..000e9dc97b1a 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -252,7 +252,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; @@ -263,6 +263,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 49da30d7510c..731759bdd7f5 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -237,7 +237,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; @@ -267,6 +267,7 @@ phy-mode = "rgmii"; phy-handle = <ðphy>; phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi index 393475cb0f4d..0020dbb1722c 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi @@ -64,7 +64,7 @@ interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_NONE>; status = "disabled"; - }; + }; }; &ipu1_di0_disp0 { diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index f3236204cb5a..768bc0e3a2b3 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -47,12 +47,12 @@ pinctrl-0 = <&pinctrl_leds>; compatible = "gpio-leds"; - green { + led_green: green { label = "phyflex:green"; gpios = <&gpio1 30 0>; }; - red { + led_red: red { label = "phyflex:red"; gpios = <&gpio2 31 0>; }; @@ -205,6 +205,19 @@ regulator-always-on; }; }; + + da9063_rtc: rtc { + compatible = "dlg,da9063-rtc"; + }; + + da9063_wdog: watchdog { + compatible = "dlg,da9063-watchdog"; + }; + + onkey { + compatible = "dlg,da9063-onkey"; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi index 94b254bfd054..28a805384668 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi @@ -116,6 +116,16 @@ dlg,use-sw-pm; }; + thermal { + compatible = "dlg,da9062-thermal"; + status = "disabled"; + }; + + gpio { + compatible = "dlg,da9062-gpio"; + status = "disabled"; + }; + regulators { vdd_arm: buck1 { regulator-name = "vdd_arm"; diff --git a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi index 19578f660b09..f0db0d4471f4 100644 --- a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi +++ b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi @@ -94,6 +94,9 @@ pinctrl-0 = <&pinctrl_usdhc3>; bus-width = <8>; non-removable; + no-1-8-v; + no-sd; + no-sdio; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 5e58740d40c5..3dbb460ef102 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -272,7 +272,7 @@ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; status = "disabled"; /* pin conflict with WEIM NOR */ - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p32", "jedec,spi-nor"; @@ -295,6 +295,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index eb9a0b104f1c..22f8e2783cdf 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -1,43 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/clock/imx6qdl-clock.h> @@ -313,7 +278,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 0c0105468a2f..37482a9023fc 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -197,7 +197,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi b/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi index 69ae430a53bd..b81799d7076a 100644 --- a/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi +++ b/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi @@ -2,35 +2,60 @@ // // Copyright (C) 2020 Pengutronix, Ulrich Oelmann <kernel@pengutronix.de> +/ { + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <65000>; + touchscreen-inverted-y; + touchscreen-swapped-x-y; + touchscreen-x-plate-ohms = <300>; + touchscreen-y-plate-ohms = <800>; + }; +}; + &ecspi4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; status = "okay"; - touchscreen@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch>; - compatible = "ti,tsc2046"; + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; reg = <0>; + pinctrl-0 = <&pinctrl_touch>; + pinctrl-names ="default"; spi-max-frequency = <1000000>; interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>; - vcc-supply = <®_3v3>; - pendown-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = /bits/ 16 <850>; - ti,y-plate-ohms = /bits/ 16 <295>; - ti,pressure-min = /bits/ 16 <2>; - ti,pressure-max = /bits/ 16 <1500>; - ti,vref-mv = /bits/ 16 <3300>; - ti,settle-delay-usec = /bits/ 16 <15>; - ti,vref-delay-usecs = /bits/ 16 <0>; - ti,penirq-recheck-delay-usecs = /bits/ 16 <100>; - ti,debounce-max = /bits/ 16 <100>; - ti,debounce-tol = /bits/ 16 <(~0)>; - ti,debounce-rep = /bits/ 16 <4>; - touchscreen-swapped-x-y; - touchscreen-inverted-y; - wakeup-source; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi index 77a91a97e6cf..3def1b621c8e 100644 --- a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi +++ b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi @@ -149,6 +149,16 @@ gpio = <&gpio4 11 GPIO_ACTIVE_LOW>; }; + reg_tft_vcom: regulator-tft-vcom { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 20000 0>; + regulator-name = "tft_vcom"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + voltage-table = <3600000 26>; + }; + reg_vcc_mmc: regulator-vcc-mmc { compatible = "regulator-fixed"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi index f86efd0ccc40..ce543e325cd3 100644 --- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi @@ -83,6 +83,16 @@ qca,clk-out-frequency = <125000000>; qca,smarteee-tw-us-1g = <24>; }; + + /* + * ADIN1300 (som rev 1.9 or later) is always at address 1. It + * will be enabled automatically by U-Boot if detected. + */ + ethernet-phy@1 { + reg = <1>; + adi,phy-output-clock = "125mhz-free-running"; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi index 51a3a5392c95..344ea935c7da 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi @@ -52,6 +52,13 @@ >; }; + pinctrl_i2c1_recovery: i2c1recoverygrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b899 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b899 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899 @@ -59,6 +66,13 @@ >; }; + pinctrl_i2c3_recovery: i2c3recoverygrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b899 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b899 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */ diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi index bfb67da64b96..aff46f3040c1 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi @@ -4,15 +4,21 @@ * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> */ +#include <dt-bindings/gpio/gpio.h> + &fec { + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_recovery>; + scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; status = "okay"; @@ -30,6 +36,7 @@ compatible = "st,24c64", "atmel,24c64"; reg = <0x50>; pagesize = <32>; + vcc-supply = <®_3p3v>; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi index 49c472285c06..a3f6543c3aaa 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi @@ -4,9 +4,14 @@ * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> */ +#include <dt-bindings/gpio/gpio.h> + &i2c3 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_recovery>; + scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; status = "okay"; @@ -24,5 +29,6 @@ compatible = "st,24c64", "atmel,24c64"; reg = <0x50>; pagesize = <32>; + vcc-supply = <®_3p3v>; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi index fded07f370b3..c096d25a6f5b 100644 --- a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi @@ -192,6 +192,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; @@ -226,7 +227,7 @@ reg = <0x28>; #gpio-cells = <2>; gpio-controller; - ngpio = <32>; + ngpios = <62>; }; sgtl5000: codec@a { diff --git a/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi index 410972e1dca9..99ec7a838f8d 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi @@ -85,7 +85,7 @@ }; &i2c3 { - rtc: mcp7940x@6f { + rtc: rtc@6f { compatible = "microchip,mcp7940x"; reg = <0x6f>; }; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index bcc5bbcce769..f41f86a76ea9 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -264,11 +264,6 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", "enet_out"; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; phy-reset-post-delay = <10>; diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi index d07d8f83456d..93a8123da27d 100644 --- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi @@ -5,6 +5,8 @@ * Author: Fabio Estevam <fabio.estevam@freescale.com> */ +#include <dt-bindings/gpio/gpio.h> + / { aliases { backlight = &backlight; @@ -226,6 +228,7 @@ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 >; }; @@ -292,7 +295,7 @@ pinctrl-0 = <&pinctrl_usbh>; vbus-supply = <®_usb_h1_vbus>; clocks = <&clks IMX6QDL_CLK_CKO>; - status = "okay"; + status = "disabled"; }; &usbotg { @@ -304,7 +307,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - non-removable; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi new file mode 100644 index 000000000000..f505f2704530 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 Protonic Holland + */ + +/ { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + power { + label = "Power Button"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", + "CAM2_MIRROR", "", "", "SMBALERT", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", + "SD1_DATA3", "ETH_MDIO", "", + "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", + "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", + "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +}; + +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", + "RGMII_TD3", + "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", + "RGMII_RD2", "RGMII_RD3", "", ""; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index b9e305774fed..c4e6cf0527ba 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -16,18 +16,37 @@ stdout-path = &uart4; }; - backlight: backlight { + backlight_lcd: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 16 64 255>; num-interpolated-steps = <16>; - default-brightness-level = <1>; + default-brightness-level = <48>; power-supply = <®_3v3>; enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; + backlight_led: backlight-led { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + }; + + /* only for backwards compatibility with old HW */ + backlight_isb: backlight-isb { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 5000000 0>; + brightness-levels = <0 8 48 255>; + num-interpolated-steps = <5>; + default-brightness-level = <0>; + power-supply = <®_3v3>; + }; + connector { compatible = "composite-video-connector"; label = "Composite0"; @@ -61,54 +80,37 @@ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; }; - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - power { - label = "Power Button"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - wakeup-source; - }; - }; - leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_leds>; led-0 { - label = "LED_DI0_DEBUG_0"; + label = "debug0"; function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; led-1 { - label = "LED_DI0_DEBUG_1"; + label = "debug1"; function = LED_FUNCTION_DISK; - gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "disk-activity"; }; led-2 { - label = "POWER_LED"; + label = "power_led"; function = LED_FUNCTION_POWER; gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; default-state = "on"; }; - }; - - panel { - compatible = "kyo,tcg121xglp"; - backlight = <&backlight>; - power-supply = <®_3v3>; - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; + led-3 { + label = "isb_led"; + function = LED_FUNCTION_POWER; + gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; }; @@ -126,15 +128,6 @@ regulator-max-microvolt = <3300000>; }; - reg_h1_vbus: regulator-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - reg_otg_vbus: regulator-otg-vbus { compatible = "regulator-fixed"; regulator-name = "otg-vbus"; @@ -144,18 +137,6 @@ enable-active-high; }; - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_npd>; - regulator-name = "wifi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <70000>; - }; - sound { compatible = "simple-audio-card"; simple-audio-card,name = "prti6q-sgtl5000"; @@ -182,6 +163,14 @@ frame-master; }; }; + + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; + }; + }; }; &audmux { @@ -212,6 +201,8 @@ &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1>; + termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + termination-ohms = <150>; status = "okay"; }; @@ -239,47 +230,13 @@ }; }; -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ9031RNX PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", - "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "SDIO_SCK", "SDIO_CMD", "SDIO_D3", - "SDIO_D2", "SDIO_D1", "SDIO_D0", - "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "", "", - "", "ETH_RESET", "WIFI_PD", "WIFI_BT_RST", "ETH_INT", "", - "WL_IRQ", "ETH_MDC"; -}; - &gpio2 { gpio-line-names = - "count0", "count1", "count2", "", "", "", "", "", - "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", - "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", - "", "", "", "", "", "", "", "ON_SWITCH", - "POWER_LED", "", "ECSPI2_SS0", "", "", "", "", ""; + "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", + "", "LED_PWM", "", "", "", + "", "", "", + "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", + "POWER_LED", "", "", "", "", "", "", ""; }; &gpio3 { @@ -288,37 +245,8 @@ "", "", "", "", "", "", "", "", "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", - "CAN2_SR", "CAN2_TX", "CAN2_RX", - "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "", "", "", - "", "", "", "", "BL_EN", "BL_PWM", "", ""; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_W_DIS", - "PCIE_RESET", "", "", "", "", "", "", "", - "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", - "I2S_BITCLK", "I2S_DOUT", - "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", - "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; -}; - -&gpio6 { - gpio-line-names = - "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", - "ITU656_D6", "ITU656_D7", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", - "RGMII_TD3", - "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", - "RGMII_RD2", "RGMII_RD3", "", ""; + "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", + "YACO_RESET"; }; &gpio7 { @@ -413,9 +341,10 @@ reg = <0x51>; }; - temperature-sensor@70 { + tsens0: temperature-sensor@70 { compatible = "ti,tmp103"; reg = <0x70>; + #thermal-sensor-cells = <0>; }; }; @@ -445,13 +374,21 @@ }; }; -&pcie { +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; -&pwm1 { +&pwm2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; }; @@ -467,12 +404,6 @@ status = "okay"; }; -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; @@ -492,7 +423,6 @@ }; &usbh1 { - vbus-supply = <®_h1_vbus>; pinctrl-names = "default"; phy_type = "utmi"; dr_mode = "host"; @@ -521,26 +451,6 @@ status = "okay"; }; -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_wifi>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - no-1-8-v; - no-mmc; - no-sd; - status = "okay"; - - wifi { - compatible = "ti,wl1271"; - interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = "38400000"; - tcxo-clock-frequency = "19200000"; - }; -}; - &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -621,29 +531,6 @@ >; }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - >; - }; - pinctrl_hog: hoggrp { fsl,pins = < /* ITU656_nRESET */ @@ -654,8 +541,6 @@ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* CAM_nDETECT */ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 /* ISB_IN1 */ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 /* ISB_nIN2 */ @@ -677,27 +562,11 @@ /* ITU656_nPDN */ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - /* HW revision detect */ - /* REV_ID0 */ - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - /* REV_ID1 */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* REV_ID2 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - /* REV_ID3 */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - /* REV_ID4 */ - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - /* New in HW revision 1 */ /* ON1_FB */ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 /* DIP1_FB */ MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - - /* New in UT2: FIXME: ISB PWM should start off, PD */ - /* ISB_LED_PWM */ - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x130b0 >; }; @@ -737,6 +606,8 @@ MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 /* POWER_LED */ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 + /* ISB_LED */ + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 >; }; @@ -746,20 +617,23 @@ >; }; - /* YaCO AUX Uart */ - pinctrl_uart1: uart1grp { + pinctrl_pwm2: pwm2grp { fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b0 >; }; - pinctrl_uart2: uart2grp { + pinctrl_pwm3: pwm3grp { fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 + >; + }; + + /* YaCO AUX Uart */ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 >; }; @@ -805,19 +679,6 @@ >; }; - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - /* WL12xx IRQ */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 @@ -833,10 +694,4 @@ MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 >; }; - - pinctrl_wifi_npd: wifinpdgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index d27beb47f9a3..ff1e0173b39b 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -143,7 +143,7 @@ #phy-cells = <0>; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -290,7 +290,7 @@ status = "disabled"; }; - bus@2000000 { /* AIPS1 */ + aips1: bus@2000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -762,7 +762,7 @@ regulator-name = "vddpu"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; - regulator-enable-ramp-delay = <150>; + regulator-enable-ramp-delay = <380>; anatop-reg-offset = <0x140>; anatop-vol-bit-shift = <9>; anatop-vol-bit-width = <5>; @@ -929,7 +929,7 @@ interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; }; - sdma: sdma@20ec000 { + sdma: dma-controller@20ec000 { compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; @@ -941,7 +941,7 @@ }; }; - bus@2100000 { /* AIPS2 */ + aips2: bus@2100000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts index 480e73183f6b..f69eec18d865 100644 --- a/arch/arm/boot/dts/imx6qp-sabresd.dts +++ b/arch/arm/boot/dts/imx6qp-sabresd.dts @@ -50,8 +50,12 @@ }; }; +&vgen3_reg { + regulator-always-on; +}; + &pcie { - status = "disabled"; + status = "okay"; }; &sata { diff --git a/arch/arm/boot/dts/imx6qp-vicutp.dts b/arch/arm/boot/dts/imx6qp-vicutp.dts index 7bad7ca6b12e..49ff145fffe5 100644 --- a/arch/arm/boot/dts/imx6qp-vicutp.dts +++ b/arch/arm/boot/dts/imx6qp-vicutp.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "imx6qp.dtsi" #include "imx6qdl-vicut1.dtsi" +#include "imx6qdl-vicut1-12inch.dtsi" / { model = "Kverneland UT1P Board"; diff --git a/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts b/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts index cea165f2161a..afaf4a6759d4 100644 --- a/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts +++ b/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts @@ -33,6 +33,10 @@ status = "okay"; }; +®_pu { + regulator-always-on; +}; + ®_usb_h1_vbus { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index 050365513836..fc164991d2ae 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -9,12 +9,18 @@ ocram2: sram@940000 { compatible = "mmio-sram"; reg = <0x00940000 0x20000>; + ranges = <0 0x00940000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; ocram3: sram@960000 { compatible = "mmio-sram"; reg = <0x00960000 0x20000>; + ranges = <0 0x00960000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 25f6f2fb1555..f16c830f1e91 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -137,7 +137,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts index a17b8bbbdb95..663ee9df79e6 100644 --- a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts +++ b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts @@ -27,7 +27,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - cover { + key-cover { label = "Cover"; gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; linux,code = <SW_LID>; @@ -35,19 +35,19 @@ wakeup-source; }; - fl { + key-fl { label = "Frontlight"; gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; linux,code = <KEY_BRIGHTNESS_CYCLE>; }; - home { + key-home { label = "Home"; gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; }; - power { + key-power { label = "Power"; gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -60,7 +60,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - on { + led-0 { label = "tolinoshine2hd:white:on"; gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c7d907c5c352..28111efb19a6 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -50,7 +50,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0x0>; @@ -61,10 +61,10 @@ <792000 1175000>, <396000 975000>; fsl,soc-operating-points = - /* ARM kHz SOC-PU uV */ - <996000 1225000>, - <792000 1175000>, - <396000 1175000>; + /* ARM kHz SOC-PU uV */ + <996000 1225000>, + <792000 1175000>, + <396000 1175000>; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, @@ -115,6 +115,9 @@ ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6SL_CLK_OCRAM>; }; @@ -222,7 +225,7 @@ uart5: serial@2018000 { compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02018000 0x4000>; interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, @@ -235,7 +238,7 @@ uart1: serial@2020000 { compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, @@ -248,7 +251,7 @@ uart2: serial@2024000 { compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02024000 0x4000>; interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, @@ -309,7 +312,7 @@ uart3: serial@2034000 { compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02034000 0x4000>; interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, @@ -322,7 +325,7 @@ uart4: serial@2038000 { compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02038000 0x4000>; interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, @@ -711,7 +714,7 @@ #power-domain-cells = <0>; power-supply = <®_pu>; clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; + <&clks IMX6SL_CLK_GPU2D_PODF>; }; pd_disp: power-domain@2 { @@ -747,7 +750,7 @@ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; }; - sdma: sdma@20ec000 { + sdma: dma-controller@20ec000 { compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index d4a000c3dde7..2873369a57c0 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -115,6 +115,9 @@ ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; }; intc: interrupt-controller@a01000 { diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index 66af78e83b70..a2c79bcf9a11 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -107,7 +107,7 @@ pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index dce5dcf96c25..7dda42553f4b 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -123,7 +123,7 @@ pinctrl-0 = <&pinctrl_qspi2>; status = "okay"; - flash0: s25fl128s@0 { + flash0: flash@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; @@ -133,7 +133,7 @@ spi-tx-bus-width = <4>; }; - flash1: s25fl128s@2 { + flash1: flash@2 { reg = <2>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 99f4cf777a38..969cfe920d25 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -108,7 +108,7 @@ pinctrl-0 = <&pinctrl_qspi2>; status = "okay"; - flash0: n25q256a@0 { + flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; @@ -118,7 +118,7 @@ reg = <0>; }; - flash1: n25q256a@2 { + flash1: flash@2 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi index ee645655090d..c84ea1fac5e9 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi +++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi @@ -183,6 +183,27 @@ status = "okay"; }; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; + + hdmi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + interrupts-extended = <&gpio3 27 IRQ_TYPE_LEVEL_LOW>; + + ports { + port { + hdmi: endpoint { + remote-endpoint = <&lcdc>; + }; + }; + }; + }; +}; + &i2c4 { /* Onboard Motion sensors */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; @@ -190,10 +211,22 @@ status = "disabled"; }; +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + + port { + lcdc: endpoint { + remote-endpoint = <&hdmi>; + }; + }; +}; + &iomuxc { pinctrl_bt_reg: btreggrp { fsl,pins = - <MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>; + <MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>; }; pinctrl_enet1: enet1grp { @@ -227,12 +260,52 @@ <MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1>; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = + <MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1>, + <MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1>; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = <MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x4001b8b1>, <MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x4001b8b1>; }; + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = <MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1>, @@ -273,24 +346,23 @@ pinctrl_otg1_reg: otg1grp { fsl,pins = - <MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0>; + <MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0>; }; - pinctrl_otg2_reg: otg2grp { fsl,pins = - <MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x10b0>; + <MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x10b0>; }; pinctrl_usb_otg1: usbotg1grp { fsl,pins = - <MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059>, - <MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x10b0>; + <MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059>, + <MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x10b0>; }; pinctrl_usb_otg2: usbot2ggrp { fsl,pins = - <MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x10b0>; + <MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x10b0>; }; pinctrl_usdhc2: usdhc2grp { diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index fc6334336b3d..abc3572d699e 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -154,7 +154,7 @@ #phy-cells = <0>; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -164,12 +164,18 @@ ocram_s: sram@8f8000 { compatible = "mmio-sram"; reg = <0x008f8000 0x4000>; + ranges = <0 0x008f8000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6SX_CLK_OCRAM_S>; }; ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6SX_CLK_OCRAM>; }; @@ -842,7 +848,7 @@ reg = <0x020e4000 0x4000>; }; - sdma: sdma@20ec000 { + sdma: dma-controller@20ec000 { compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index a3fde3316c73..c83e64a62d8a 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -82,7 +82,7 @@ "AMIC", "MICB"; }; - spi4 { + spi-4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; @@ -286,7 +286,7 @@ pinctrl-0 = <&pinctrl_qspi>; status = "okay"; - flash0: n25q256a@0 { + flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts b/arch/arm/boot/dts/imx6ul-kontron-bl-43.dts index 5bfad4655b22..0c643706a158 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts +++ b/arch/arm/boot/dts/imx6ul-kontron-bl-43.dts @@ -5,12 +5,12 @@ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> */ -#include "imx6ul-kontron-n6310-s.dts" +#include "imx6ul-kontron-bl.dts" / { - model = "Kontron N6310 S 43"; - compatible = "kontron,imx6ul-n6310-s-43", "kontron,imx6ul-n6310-s", - "kontron,imx6ul-n6310-som", "fsl,imx6ul"; + model = "Kontron BL i.MX6UL 43 (N631X S 43)"; + compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul", + "kontron,sl-imx6ul", "fsl,imx6ul"; backlight { compatible = "pwm-backlight"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-bl-common.dtsi index 770f59b23102..43868311f48a 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-bl-common.dtsi @@ -72,7 +72,6 @@ &adc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc1>; - num-channels = <3>; vref-supply = <®_vref_adc>; status = "okay"; }; @@ -178,7 +177,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts b/arch/arm/boot/dts/imx6ul-kontron-bl.dts index 5a3e06d6219b..dadf6d3d5f52 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts +++ b/arch/arm/boot/dts/imx6ul-kontron-bl.dts @@ -7,11 +7,10 @@ /dts-v1/; -#include "imx6ul-kontron-n6310-som.dtsi" -#include "imx6ul-kontron-n6x1x-s.dtsi" +#include "imx6ul-kontron-sl.dtsi" +#include "imx6ul-kontron-bl-common.dtsi" / { - model = "Kontron N6310 S"; - compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som", - "fsl,imx6ul"; + model = "Kontron BL i.MX6UL (N631X S)"; + compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul"; }; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi deleted file mode 100644 index 47d3ce5d255f..000000000000 --- a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> - */ - -#include "imx6ul.dtsi" -#include "imx6ul-kontron-n6x1x-som-common.dtsi" - -/ { - model = "Kontron N6310 SOM"; - compatible = "kontron,imx6ul-n6310-som", "fsl,imx6ul"; - - memory@80000000 { - reg = <0x80000000 0x10000000>; - device_type = "memory"; - }; -}; - -&qspi { - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <108000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - - partition@8000000 { - label = "ubi2"; - reg = <0x08000000 0x08000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts b/arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts deleted file mode 100644 index 239a1af3aeaa..000000000000 --- a/arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx6ul-kontron-n6311-som.dtsi" -#include "imx6ul-kontron-n6x1x-s.dtsi" - -/ { - model = "Kontron N6311 S"; - compatible = "kontron,imx6ul-n6311-s", "kontron,imx6ul-n6311-som", - "fsl,imx6ul"; -}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi deleted file mode 100644 index a095a7654ac6..000000000000 --- a/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -#include "imx6ul.dtsi" -#include "imx6ul-kontron-n6x1x-som-common.dtsi" - -/ { - model = "Kontron N6311 SOM"; - compatible = "kontron,imx6ul-n6311-som", "fsl,imx6ul"; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - device_type = "memory"; - }; -}; - -&qspi { - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <104000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - - partition@8000000 { - label = "ubi2"; - reg = <0x08000000 0x18000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi b/arch/arm/boot/dts/imx6ul-kontron-sl-common.dtsi index 2a449a3c1ae2..dcf88f610346 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-sl-common.dtsi @@ -11,6 +11,11 @@ chosen { stdout-path = &uart4; }; + + memory@80000000 { + reg = <0x80000000 0x10000000>; + device_type = "memory"; + }; }; &ecspi2 { @@ -19,7 +24,7 @@ pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; @@ -55,6 +60,16 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + }; }; &wdog1 { diff --git a/arch/arm/boot/dts/imx6ul-kontron-sl.dtsi b/arch/arm/boot/dts/imx6ul-kontron-sl.dtsi new file mode 100644 index 000000000000..0580d043e5ae --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-kontron-sl.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> + */ + +#include "imx6ul.dtsi" +#include "imx6ul-kontron-sl-common.dtsi" + +/ { + model = "Kontron SL i.MX6UL (N631X SOM)"; + compatible = "kontron,sl-imx6ul", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi index 7cda6944501d..ec042648bd98 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi @@ -11,7 +11,7 @@ brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <5>; power-supply = <®_backlight_en>; - pwms = <&pwm3 0 5000000>; + pwms = <&pwm3 0 5000000 0>; status = "disabled"; }; @@ -72,8 +72,8 @@ st,settling = <2>; st,fraction-z = <7>; st,i-drive = <1>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; + touchscreen-inverted-x; + touchscreen-inverted-y; }; }; }; @@ -91,7 +91,6 @@ }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index 0d4ba9494cf2..38ea4dcfa228 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -83,11 +83,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc1>; vref-supply = <®_adc1_vref_3v3>; - /* - * driver can not separate a specific channel so we request 4 channels - * here - we need only the fourth channel - */ - num-channels = <4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi new file mode 100644 index 000000000000..eca94ed6451b --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +/* + * Common for + * - TQMa6ULx + * - TQMa6ULxL + * - TQMa6ULLx + * - TQMa6ULLxL + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_recovery>; + scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pfuze3000: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + reg_sw1a: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-ramp-delay = <6250>; + /* not used */ + }; + + reg_sw1b_core: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + reg_sw2: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sw3_ddr: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_swbst: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + /* not used */ + }; + + reg_snvs_3v0: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + reg_vccsd: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + }; + + reg_v33_3v3: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vldo1_3v3: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* not used */ + }; + + reg_vldo2: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + /* not used */ + }; + + reg_vldo3: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* not used */ + }; + + reg_vldo4: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; + + jc42_1a: eeprom-temperature-sensor@1a { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1a>; + }; + + m24c64_50: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + m24c02_52: eeprom@52 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + read-only; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + /* + * PMIC & temperature sensor IRQ + * Both do currently not use IRQ + * potentially dangerous if used on baseboard + */ + pmic-int-hog { + gpio-hog; + gpios = <24 0>; + input; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <33000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + reg = <0>; + }; +}; + +/* eMMC */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz" , "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + + bus-width = <8>; + disable-wp; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4_recovery: i2c4recoverygrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x4001b8b0 + >; + }; + + pinctrl_pmic: pmic { + fsl,pins = < + /* PMIC irq */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts new file mode 100644 index 000000000000..f2a5f17f312e --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul1.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; +}; + +/* + * Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage) + * and need to be disabled here again + */ +&can2 { + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <0>; + }; + }; +}; + +&fec2 { + /delete-property/ phy-handle; + /delete-node/ mdio; +}; + +&iomuxc { + pinctrl_enet1_mdc: enet1mdcgrp { + fsl,pins = < + /* mdio */ + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi new file mode 100644 index 000000000000..24192d012ef7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +#include "imx6ul-tqma6ul2.dtsi" + +/ { + model = "TQ-Systems TQMa6UL1 SoM"; + compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; +}; + +/* + * There are no module specific differences compared to TQMa6UL2, + * only external interfaces differ + */ + +/* + * Devices not available on i.MX6ULG1 and should not be enabled on + * mainboard level (again) + */ +&can2 { + status = "disabled"; +}; + +&csi { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; + +&lcdif { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts new file mode 100644 index 000000000000..0757df2b8f48 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULx SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2-mba6ulx", "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi new file mode 100644 index 000000000000..e2e95dd92263 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2 SoM"; + compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step = <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170e1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170e1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170e1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170e1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170e1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170e1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170e1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170e1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170e1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts new file mode 100644 index 000000000000..9d9b6b744a1c --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi new file mode 100644 index 000000000000..4b87e2dc70dc --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2L SoM"; + compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step = <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi new file mode 100644 index 000000000000..5afb9046c202 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +/* + * Common for + * - TQMa6ULx + * - TQMa6ULLx + */ + +&m24c64_50 { + vcc-supply = <®_sw2>; +}; + +&m24c02_52 { + vcc-supply = <®_sw2>; +}; + +®_sw2 { + regulator-boot-on; + regulator-always-on; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_sw2>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70b9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70b9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70b9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi new file mode 100644 index 000000000000..ba84a4f70ebd --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +/* + * Common for + * - TQMa6ULxL + * - TQMa6ULLxL + */ + +/ { + reg_vin: reg-vin { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&m24c64_50 { + vcc-supply = <®_vin>; +}; + +&m24c02_52 { + vcc-supply = <®_vin>; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_vin>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts index 97686097a86e..92ac0edcb608 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts +++ b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts @@ -119,7 +119,7 @@ /delete-node/ codec@a; /delete-node/ touchscreen@48; - rtc: mcp7940x@6f { + rtc: rtc@6f { compatible = "microchip,mcp7940x"; reg = <0x6f>; }; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index c485d058e079..15ee0275feaf 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -212,7 +212,7 @@ enable-active-high; }; - spi_gpio: spi-gpio { + spi_gpio: spi { #address-cells = <1>; #size-cells = <0>; compatible = "spi-gpio"; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index afeec01f6522..2b5996395701 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -64,20 +64,18 @@ clock-frequency = <696000000>; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; - operating-points = < + operating-points = /* kHz uV */ - 696000 1275000 - 528000 1175000 - 396000 1025000 - 198000 950000 - >; - fsl,soc-operating-points = < + <696000 1275000>, + <528000 1175000>, + <396000 1025000>, + <198000 950000>; + fsl,soc-operating-points = /* KHz uV */ - 696000 1275000 - 528000 1175000 - 396000 1175000 - 198000 1175000 - >; + <696000 1275000>, + <528000 1175000>, + <396000 1175000>, + <198000 1175000>; clocks = <&clks IMX6UL_CLK_ARM>, <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_PLL2_PFD2>, @@ -139,7 +137,7 @@ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -149,6 +147,9 @@ ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; }; intc: interrupt-controller@a01000 { @@ -543,7 +544,7 @@ }; kpp: keypad@20b8000 { - compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; + compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_KPP>; @@ -743,7 +744,7 @@ status = "disabled"; }; - sdma: sdma@20ec000 { + sdma: dma-controller@20ec000 { compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; @@ -923,7 +924,6 @@ reg = <0x02198000 0x4000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_ADC1>; - num-channels = <2>; clock-names = "adc"; fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; @@ -998,7 +998,7 @@ }; csi: csi@21c4000 { - compatible = "fsl,imx6ul-csi", "fsl,imx7-csi"; + compatible = "fsl,imx6ul-csi"; reg = <0x021c4000 0x4000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_CSI>; @@ -1007,7 +1007,7 @@ }; lcdif: lcdif@21c8000 { - compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; + compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif"; reg = <0x021c8000 0x4000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, @@ -1028,7 +1028,7 @@ qspi: spi@21e0000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; + compatible = "fsl,imx6ul-qspi"; reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-aster.dts new file mode 100644 index 000000000000..d3f2fb7c6c1e --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Aster"; + compatible = "toradex,colibri-imx6ull-aster", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi new file mode 100644 index 000000000000..c9133ba2d705 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&ecspi1 { + status = "okay"; + + num-cs = <2>; + cs-gpios = < + &gpio3 26 GPIO_ACTIVE_HIGH /* SODIMM 86 LCD_DATA21 */ + &gpio4 28 GPIO_ACTIVE_HIGH /* SODIMM 65 CSI_DATA07 */ + >; +}; + +/* + * Following SODIMM Pins should not be accessed as GPIO on Aster board: + * 134 - AIN5_SCL (no connection) + * 127 - Voltage Level Translator OE# signal (IC11 and IC12) + * + * To configure GPIO to LED5, please disable FEC2 and uncomment the following: + * &iomuxc { + * pinctrl-names = "default"; + * pinctrl-0 = < + * &pinctrl_gpio1 + * &pinctrl_gpio2 + * &pinctrl_gpio3 + * &pinctrl_gpio4 + * &pinctrl_gpio6 - for non-WiFi modules only + * &pinctrl_gpio7 + * &pinctrl_gpio_aster + * >; + * + * pinctrl_gpio_aster: gpio-aster { + * fsl,pins = < + * MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x1b0b0 + * >; + * }; + * }; + */ + +&i2c1 { + status = "okay"; + + m41t0m6: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* PWM <A> */ +&pwm4 { + status = "okay"; +}; + +/* PWM <B> */ +&pwm5 { + status = "okay"; +}; + +/* PWM <C> */ +&pwm6 { + status = "okay"; +}; + +/* PWM <D> */ +&pwm7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usdhc1 { + vmmc-supply = <®_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts new file mode 100644 index 000000000000..919c0464d6cb --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster"; + compatible = "toradex,colibri-imx6ull-emmc-aster", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts new file mode 100644 index 000000000000..b9060c2f7977 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2"; + compatible = "toradex,colibri-imx6ull-iris-v2", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts new file mode 100644 index 000000000000..0ab71f2f5daa --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris"; + compatible = "toradex,colibri-imx6ull-emmc-iris", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi index a099abfdfa27..ea238525d5c0 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2021 Toradex + * Copyright 2022 Toradex */ #include "imx6ull-colibri.dtsi" @@ -8,7 +8,7 @@ / { aliases { mmc0 = &usdhc2; /* eMMC */ - mmc1 = &usdhc1; /* MMC 4bit slot */ + mmc1 = &usdhc1; /* MMC 4-bit slot */ }; memory@80000000 { @@ -154,6 +154,7 @@ "SODIMM_127"; }; +/* NAND */ &gpmi { status = "disabled"; }; @@ -170,6 +171,7 @@ pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>; }; +/* eMMC */ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2emmc>; diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts index 08669a18349e..9bf7111d7b00 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2022 Toradex */ /dts-v1/; @@ -9,6 +9,6 @@ #include "imx6ull-colibri-eval-v3.dtsi" / { - model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3"; + model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index a78849fd2afa..e29907428c20 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017 Toradex AG + * Copyright 2017-2022 Toradex */ / { @@ -8,20 +8,6 @@ stdout-path = "serial0:115200n8"; }; - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpiokeys>; - - power { - label = "Wake-Up"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - /* fixed crystal dedicated to mcp2515 */ clk16m: clk16m { compatible = "fixed-clock"; @@ -29,18 +15,6 @@ clock-frequency = <16000000>; }; - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3.3V"; @@ -71,14 +45,6 @@ status = "okay"; }; -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3v3>; - pwms = <&pwm4 0 5000000 1>; - status = "okay"; -}; - &ecspi1 { status = "okay"; @@ -107,16 +73,6 @@ }; }; -&lcdif { - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - /* PWM <A> */ &pwm4 { status = "okay"; @@ -150,6 +106,7 @@ }; &usbotg1 { + vbus-supply = <®_usbh_vbus>; status = "okay"; }; @@ -159,20 +116,6 @@ }; &usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - disable-wp; - wakeup-source; - keep-power-in-suspend; vmmc-supply = <®_3v3>; - vqmmc-supply = <®_sd1_vmmc>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts new file mode 100644 index 000000000000..afc1e0119783 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256M/512B on Colibri Iris V2"; + compatible = "toradex,colibri-imx6ull-iris-v2", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&gpio1 { + /* This turns the LVDS transceiver on */ + lvds-power-on { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; +}; + +&gpio5 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi new file mode 100644 index 000000000000..93649cad0cc0 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +#include "imx6ull-colibri-iris.dtsi" + +/ { + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; +}; + + +&usdhc1 { + cap-power-off-card; + vmmc-supply = <®_3v3_vmmc>; + /delete-property/ keep-power-in-suspend; + /delete-property/ no-1-8-v; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-iris.dts new file mode 100644 index 000000000000..4fb97b0fe30b --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Iris"; + compatible = "toradex,colibri-imx6ull-iris", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi new file mode 100644 index 000000000000..7f3b37baba88 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&gpio1 { + /* + * uart25_tx_on turns the UART transceiver on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled + * in userspace. + * The same applies to uart1_tx_on. + */ + uart25_tx_on { + gpio-hog; + gpios = <15 0>; + output-high; + }; +}; + +&gpio2 { + uart1_tx_on { + gpio-hog; + gpios = <7 0>; + output-high; + }; +}; + +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + m41t0m6: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* PWM <A> */ +&pwm4 { + status = "okay"; +}; + +/* PWM <B> */ +&pwm5 { + status = "okay"; +}; + +/* PWM <C> */ +&pwm6 { + status = "okay"; +}; + +/* PWM <D> */ +&pwm7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usdhc1 { + vmmc-supply = <®_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi index 95a11b8bcbdb..88901db255d6 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2022 Toradex */ #include "imx6ull-colibri.dtsi" @@ -12,13 +12,150 @@ }; }; +&gpio1 { + gpio-line-names = "SODIMM_8", + "SODIMM_6", + "SODIMM_129", + "SODIMM_89", + "SODIMM_19", + "SODIMM_21", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184", + "SODIMM_4", + "SODIMM_2", + "SODIMM_106", + "SODIMM_71", + "SODIMM_23", + "SODIMM_31", + "SODIMM_99", + "SODIMM_102", + "SODIMM_33", + "SODIMM_35", + "SODIMM_25", + "SODIMM_27", + "SODIMM_36", + "SODIMM_38", + "SODIMM_32", + "SODIMM_34", + "SODIMM_135", + "SODIMM_77", + "SODIMM_100", + "SODIMM_186", + "SODIMM_196", + "SODIMM_194"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_55", + "SODIMM_63", + "SODIMM_178", + "SODIMM_188", + "SODIMM_73", + "SODIMM_30", + "SODIMM_67", + "SODIMM_104", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_190", + "SODIMM_47", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_29", + "SODIMM_37", + "SODIMM_88", + "SODIMM_86", + "SODIMM_92", + "SODIMM_90"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_59", + "", + "", + "SODIMM_133", + "", + "SODIMM_28", + "SODIMM_75", + "SODIMM_96", + "SODIMM_81", + "SODIMM_94", + "SODIMM_101", + "SODIMM_103", + "SODIMM_79", + "SODIMM_97", + "SODIMM_69", + "SODIMM_98", + "SODIMM_85", + "SODIMM_65"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_43", + "SODIMM_45", + "SODIMM_137", + "SODIMM_95", + "SODIMM_107", + "SODIMM_131", + "SODIMM_93", + "", + "SODIMM_138", + "", + "SODIMM_105", + "SODIMM_127"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 - &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>; + &pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7>; }; &iomuxc_snvs { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>; + pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts new file mode 100644 index 000000000000..b4f65e8c5857 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster"; + compatible = "toradex,colibri-imx6ull-wifi-aster", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts index df72ce1ae2cb..1d64d1a5d8a7 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2022 Toradex */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts new file mode 100644 index 000000000000..ce02f8a9ddd3 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2"; + compatible = "toradex,colibri-imx6ull-wifi-iris-v2", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&gpio1 { + /* This turns the LVDS transceiver on */ + lvds-power-on { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; +}; + +&gpio5 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts new file mode 100644 index 000000000000..5ac1aa298ce7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris"; + compatible = "toradex,colibri-imx6ull-wifi-iris", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi index 9f1e38282bee..db59ee6b1c86 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2022 Toradex */ #include "imx6ull-colibri.dtsi" @@ -23,16 +23,152 @@ clock-frequency = <792000000>; }; +&gpio1 { + gpio-line-names = "SODIMM_8", + "SODIMM_6", + "SODIMM_129", + "", + "SODIMM_19", + "SODIMM_21", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184", + "SODIMM_4", + "SODIMM_2", + "SODIMM_106", + "SODIMM_71", + "SODIMM_23", + "SODIMM_31", + "SODIMM_99", + "SODIMM_102", + "SODIMM_33", + "SODIMM_35", + "SODIMM_25", + "SODIMM_27", + "SODIMM_36", + "SODIMM_38", + "SODIMM_32", + "SODIMM_34", + "SODIMM_135", + "SODIMM_77", + "SODIMM_100", + "SODIMM_186", + "SODIMM_196", + "SODIMM_194"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_55", + "SODIMM_63", + "SODIMM_178", + "SODIMM_188", + "SODIMM_73", + "SODIMM_30", + "SODIMM_67", + "SODIMM_104", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_190", + "SODIMM_47", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_29", + "SODIMM_37", + "SODIMM_88", + "SODIMM_86", + "SODIMM_92", + "SODIMM_90"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_59", + "", + "", + "SODIMM_133", + "", + "SODIMM_28", + "SODIMM_75", + "SODIMM_96", + "", + "", + "", + "", + "", + "", + "SODIMM_69", + "SODIMM_98", + "SODIMM_85", + "SODIMM_65"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_43", + "SODIMM_45", + "SODIMM_137", + "SODIMM_95", + "SODIMM_107", + "SODIMM_131", + "", + "", + "", + "", + "SODIMM_105"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 - &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>; + &pinctrl_gpio4 &pinctrl_gpio7>; }; &iomuxc_snvs { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>; + pinctrl-0 = <&pinctrl_snvs_gpio1>; }; &usdhc2 { diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 7f35a06dff95..577a424b0e1d 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -1,22 +1,54 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018-2021 Toradex + * Copyright 2018-2022 Toradex */ #include "imx6ull.dtsi" / { + /* Ethernet aliases to ensure correct MAC addresses */ aliases { ethernet0 = &fec2; ethernet1 = &fec1; }; - bl: backlight { + backlight: backlight { compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; - enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - status = "disabled"; + power-supply = <®_3v3>; + pwms = <&pwm4 0 5000000 1>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + wakeup { + debounce-interval = <10>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ + label = "Wake-Up"; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + panel_dpi: panel-dpi { + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + power-supply = <®_3v3>; + status = "okay"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; }; reg_module_3v3: regulator-module-3v3 { @@ -35,9 +67,9 @@ regulator-max-microvolt = <3300000>; }; - reg_sd1_vmmc: regulator-sd1-vmmc { + reg_sd1_vqmmc: regulator-sd1-vqmmc { compatible = "regulator-gpio"; - gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_snvs_reg_sd>; regulator-always-on; @@ -47,11 +79,24 @@ states = <1800000 0x1 3300000 0x0>; vin-supply = <®_module_3v3>; }; + + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed-clock"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "+V3.3_ETH"; + regulator-type = "voltage"; + vin-supply = <®_module_3v3>; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + startup-delay-us = <150000>; + }; }; &adc1 { - num-channels = <10>; vref-supply = <®_module_3v3_avdd>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; }; &can1 { @@ -73,12 +118,14 @@ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; }; +/* Ethernet */ &fec2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_enet2>; pinctrl-1 = <&pinctrl_enet2_sleep>; phy-mode = "rmii"; phy-handle = <ðphy1>; + phy-supply = <®_eth_phy>; status = "okay"; mdio { @@ -93,9 +140,11 @@ }; }; +/* NAND */ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; + fsl,use-minimum-ecc; nand-on-flash-bbt; nand-ecc-mode = "hw"; nand-ecc-strength = <8>; @@ -103,15 +152,35 @@ status = "okay"; }; +/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>; + reg = <0x4a>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ + status = "disabled"; + }; }; +/* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ &i2c2 { + /* Use low frequency to compensate for the high pull-up values. */ + clock-frequency = <40000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; @@ -119,7 +188,7 @@ scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - ad7879@2c { + ad7879_ts: touchscreen@2c { compatible = "adi,ad7879-1"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_snvs_ad7879_int>; @@ -140,23 +209,33 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + + port { + lcdif_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; }; +/* PWM <A> */ &pwm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; }; +/* PWM <B> */ &pwm5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm5>; }; +/* PWM <C> */ &pwm6 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm6>; }; +/* PWM <D> */ &pwm7 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm7>; @@ -170,6 +249,7 @@ status = "disabled"; }; +/* Colibri UART_A */ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; @@ -177,6 +257,7 @@ fsl,dte-mode; }; +/* Colibri UART_B */ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -184,12 +265,14 @@ fsl,dte-mode; }; +/* Colibri UART_C */ &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; fsl,dte-mode; }; +/* Colibri USBC */ &usbotg1 { dr_mode = "otg"; srp-disable; @@ -197,14 +280,28 @@ adp-disable; }; +/* Colibri USBH */ &usbotg2 { dr_mode = "host"; }; +/* Colibri MMC/SD */ &usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; assigned-clock-rates = <0>, <198000000>; + bus-width = <4>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ + disable-wp; + keep-power-in-suspend; + no-1-8-v; + vqmmc-supply = <®_sd1_vqmmc>; + wakeup-source; }; &wdog1 { @@ -214,13 +311,35 @@ }; &iomuxc { - pinctrl_can_int: canint-grp { + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */ + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */ + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */ + >; + }; + + pinctrl_atmel_adap: atmeladapgrp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */ + MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */ + >; + }; + + pinctrl_atmel_conn: atmelconngrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ + >; + }; + + pinctrl_can_int: canintgrp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ >; }; - pinctrl_enet2: enet2-grp { + pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 @@ -235,7 +354,7 @@ >; }; - pinctrl_enet2_sleep: enet2sleepgrp { + pinctrl_enet2_sleep: enet2-sleepgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 @@ -250,13 +369,13 @@ >; }; - pinctrl_ecspi1_cs: ecspi1-cs-grp { + pinctrl_ecspi1_cs: ecspi1csgrp { fsl,pins = < MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ >; }; - pinctrl_ecspi1: ecspi1-grp { + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ @@ -264,27 +383,27 @@ >; }; - pinctrl_flexcan1: flexcan1-grp { + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 >; }; - pinctrl_flexcan2: flexcan2-grp { + pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 >; }; - pinctrl_gpio_bl_on: gpio-bl-on-grp { + pinctrl_gpio_bl_on: gpioblongrp { fsl,pins = < MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ >; }; - pinctrl_gpio1: gpio1-grp { + pinctrl_gpio1: gpio1grp { fsl,pins = < MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ @@ -297,7 +416,7 @@ >; }; - pinctrl_gpio2: gpio2-grp { /* Camera */ + pinctrl_gpio2: gpio2grp { /* Camera */ fsl,pins = < MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ @@ -307,26 +426,20 @@ >; }; - pinctrl_gpio3: gpio3-grp { /* CAN2 */ + pinctrl_gpio3: gpio3grp { /* CAN2 */ fsl,pins = < MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ >; }; - pinctrl_gpio4: gpio4-grp { + pinctrl_gpio4: gpio4grp { fsl,pins = < MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ >; }; - pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */ - fsl,pins = < - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ - >; - }; - - pinctrl_gpio6: gpio6-grp { /* Wifi pins */ + pinctrl_gpio6: gpio6grp { /* Wifi pins */ fsl,pins = < MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ @@ -338,7 +451,7 @@ >; }; - pinctrl_gpio7: gpio7-grp { /* CAN1 */ + pinctrl_gpio7: gpio7grp { /* CAN1 */ fsl,pins = < MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ @@ -347,9 +460,9 @@ /* * With an eMMC instead of a raw NAND device the following pins - * are available at SODIMM pins + * are available at SODIMM pins. */ - pinctrl_gpmi_gpio: gpmi-gpio-grp { + pinctrl_gpmi_gpio: gpmigpiogrp { fsl,pins = < MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */ MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */ @@ -358,7 +471,7 @@ >; }; - pinctrl_gpmi_nand: gpmi-nand-grp { + pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 @@ -377,35 +490,35 @@ >; }; - pinctrl_i2c1: i2c1-grp { + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ >; }; - pinctrl_i2c1_gpio: i2c1-gpio-grp { + pinctrl_i2c1_gpio: i2c1-gpiogrp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ >; }; - pinctrl_i2c2: i2c2-grp { + pinctrl_i2c2: i2c2grp { fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 >; }; - pinctrl_i2c2_gpio: i2c2-gpio-grp { + pinctrl_i2c2_gpio: i2c2-gpiogrp { fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 >; }; - pinctrl_lcdif_dat: lcdif-dat-grp { + pinctrl_lcdif_dat: lcdifdatgrp { fsl,pins = < MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ @@ -428,7 +541,7 @@ >; }; - pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + pinctrl_lcdif_ctrl: lcdifctrlgrp { fsl,pins = < MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ @@ -437,31 +550,31 @@ >; }; - pinctrl_pwm4: pwm4-grp { + pinctrl_pwm4: pwm4grp { fsl,pins = < MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ >; }; - pinctrl_pwm5: pwm5-grp { + pinctrl_pwm5: pwm5grp { fsl,pins = < MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ >; }; - pinctrl_pwm6: pwm6-grp { + pinctrl_pwm6: pwm6grp { fsl,pins = < MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ >; }; - pinctrl_pwm7: pwm7-grp { + pinctrl_pwm7: pwm7grp { fsl,pins = < MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ >; }; - pinctrl_uart1: uart1-grp { + pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ @@ -470,16 +583,16 @@ >; }; - pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ + pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */ fsl,pins = < - MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 */ - MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 */ - MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 */ - MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 */ + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */ + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */ + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */ >; }; - pinctrl_uart2: uart2-grp { + pinctrl_uart2: uart2grp { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ @@ -487,23 +600,23 @@ MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ >; }; - pinctrl_uart5: uart5-grp { + pinctrl_uart5: uart5grp { fsl,pins = < MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ >; }; - pinctrl_usbh_reg: gpio-usbh-reg { + pinctrl_usbh_reg: usbhreggrp { fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */ + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */ >; }; - pinctrl_usdhc1: usdhc1-grp { + pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */ - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */ + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ @@ -511,10 +624,10 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 @@ -522,25 +635,25 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >; }; - pinctrl_usdhc2: usdhc2-grp { + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17069 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 >; @@ -561,7 +674,7 @@ >; }; - pinctrl_wdog: wdog-grp { + pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 >; @@ -569,65 +682,65 @@ }; &iomuxc_snvs { - pinctrl_snvs_gpio1: snvs-gpio1-grp { + pinctrl_atmel_snvs_conn: atmelsnvsconngrp { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ - MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ - MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 */ - MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ >; }; - pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */ + pinctrl_snvs_gpio1: snvsgpio1grp { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */ + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ >; }; - pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ + pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */ fsl,pins = < MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ >; }; - pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */ + pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */ fsl,pins = < MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 >; }; - pinctrl_snvs_reg_sd: snvs-reg-sd-grp { + pinctrl_snvs_reg_sd: snvsregsdgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 >; }; - pinctrl_snvs_usbc_det: snvs-usbc-det-grp { + pinctrl_snvs_usbc_det: snvsusbcdetgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 >; }; - pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { + pinctrl_snvs_gpiokeys: snvsgpiokeysgrp { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */ + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */ >; }; - pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { + pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 */ + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */ >; }; - pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp { + pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 >; }; - pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { + pinctrl_snvs_wifi_pdn: snvswifipdngrp { fsl,pins = < MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 >; diff --git a/arch/arm/boot/dts/imx6ull-kontron-bl.dts b/arch/arm/boot/dts/imx6ull-kontron-bl.dts new file mode 100644 index 000000000000..fa016465cdbc --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-kontron-bl.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx6ull-kontron-sl.dtsi" +#include "imx6ul-kontron-bl-common.dtsi" + +/ { + model = "Kontron BL i.MX6ULL (N641X S)"; + compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts b/arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts deleted file mode 100644 index 57588a5e1e34..000000000000 --- a/arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2019 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx6ull-kontron-n6411-som.dtsi" -#include "imx6ul-kontron-n6x1x-s.dtsi" - -/ { - model = "Kontron N6411 S"; - compatible = "kontron,imx6ull-n6411-s", "kontron,imx6ull-n6411-som", - "fsl,imx6ull"; -}; diff --git a/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi b/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi deleted file mode 100644 index b7e984284e1a..000000000000 --- a/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -#include "imx6ull.dtsi" -#include "imx6ul-kontron-n6x1x-som-common.dtsi" - -/ { - model = "Kontron N6411 SOM"; - compatible = "kontron,imx6ull-n6311-som", "fsl,imx6ull"; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - device_type = "memory"; - }; -}; - -&qspi { - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <104000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - - partition@8000000 { - label = "ubi2"; - reg = <0x08000000 0x18000000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/imx6ull-kontron-sl.dtsi b/arch/arm/boot/dts/imx6ull-kontron-sl.dtsi new file mode 100644 index 000000000000..93f10eb3494f --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-kontron-sl.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include "imx6ull.dtsi" +#include "imx6ul-kontron-sl-common.dtsi" + +/ { + model = "Kontron SL i.MX6ULL (N641X SOM)"; + compatible = "kontron,sl-imx6ull", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts new file mode 100644 index 000000000000..14adb87da911 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer <a.bauer@phytec.de> + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-emmc", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* EMMC-Version */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts new file mode 100644 index 000000000000..ae396ac63443 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer <a.bauer@phytec.de> + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-nand", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* NAND-Version */ +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi new file mode 100644 index 000000000000..5464a52a1f94 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer <a.bauer@phytec.de> + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-phytec-phycore-som.dtsi" + +/ { + + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-key"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key { + label = "KEY-A"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = <KEY_A>; + wakeup-source; + }; + }; + + reg_adc1_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_s25fl064_hold: regulator-s25fl064-hold { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_s25fl064_hold>; + compatible = "regulator-fixed"; + regulator-name = "s25fl064_hold"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_hub_vbus: regulator-hub-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhubpwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_hub_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>, + <&pinctrl_user_leds_snvs>; + + user-led1 { + label = "yellow"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + + user-led2 { + label = "red"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, + <&pinctrl_ecspi1_cs>; + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>, + <&gpio3 10 GPIO_ACTIVE_LOW>, + <&gpio3 11 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm_tis: tpm@1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + compatible = "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + }; + + s25fl064: flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = " jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <40000000>; + m25p,fast-read; + status = "disabled"; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + dmas = <&sdma 7 8 0>, + <&sdma 8 8 0>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + tmp102: tmp@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + interrupt-parent = <&gpio5>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + i2c_rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + compatible = "microcrystal,rv4162"; + reg = <0x68>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + status = "okay"; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* UART4 * RS485 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* UART5 * RS232 */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_hub_vbus>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&iomuxc_snvs { + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_usbhubpwr: usbhubpwrgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059 + >; + }; + + pinctrl_user_leds_snvs: user_ledsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; +}; + +&iomuxc { + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0 + >; + }; + + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0 + >; + }; + + princtrl_flexcan2_en: flexcan2engrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0 + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0 + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0 + MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0 + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm6: pwm6grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0 + >; + }; + + pinctrl_s25fl064_hold: s25fl064holdgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80 + >; + }; + + pinctrl_usbotg1pwr: usbotg1pwrgrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_user_leds: userledsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts new file mode 100644 index 000000000000..e593b7036fc7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi new file mode 100644 index 000000000000..8541cb3f3b3e --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM"; + compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step = <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts new file mode 100644 index 000000000000..33437aae9822 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi new file mode 100644 index 000000000000..be593d47e3b1 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM"; + compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step = <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index 9bf67490ac49..2bccd45e9fc2 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -50,7 +50,7 @@ }; / { - soc { + soc: soc { aips3: bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts index 59bcfc9a6b10..c92e4e2f6ab9 100644 --- a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts +++ b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts @@ -29,6 +29,10 @@ status = "okay"; }; +&snvs_poweroff { + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/imx7-colibri-aster.dtsi index 139188eb9f40..fa488a6de0d4 100644 --- a/arch/arm/boot/dts/imx7-colibri-aster.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-aster.dtsi @@ -1,169 +1,79 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017-2020 Toradex AG - * + * Copyright 2017-2022 Toradex */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - power { - label = "Wake-Up"; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; - +/* Colibri AD0 to AD3 */ &adc1 { status = "okay"; }; -/* - * ADC2 is not available on the Aster board and - * conflicts with AD7879 resistive touchscreen. - */ -&adc2 { - status = "disabled"; -}; - -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3v3>; +/* Colibri SSP */ +&ecspi3 { + cs-gpios = < + &gpio4 11 GPIO_ACTIVE_LOW /* SODIMM 86 / regular SSPFRM as UNO_SPI_CS or */ + &gpio4 23 GPIO_ACTIVE_LOW /* SODIMM 65 / already muxed pinctrl_gpio2 as SPI_CE0_N */ + &gpio4 22 GPIO_ACTIVE_LOW /* SODIMM 85 / already muxed pinctrl_gpio2 as SPI_CE1_N */ + >; status = "okay"; }; +/* Colibri Fast Ethernet */ &fec1 { status = "okay"; }; +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ &i2c4 { status = "okay"; - - /* Microchip/Atmel maxtouch controller */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiotouch>; - reg = <0x4a>; - interrupt-parent = <&gpio2>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ - reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 */ - }; - - /* M41T0M6 real time clock on carrier board */ - rtc: m41t0m6@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl_gpiotouch: touchgpios { - fsl,pins = < - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 - >; - }; -}; - -&lcdif { - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; }; +/* Colibri PWM<A> */ &pwm1 { status = "okay"; }; +/* Colibri PWM<B> */ &pwm2 { status = "okay"; }; +/* Colibri PWM<C> */ &pwm3 { status = "okay"; }; +/* Colibri PWM<D> */ &pwm4 { status = "okay"; }; +/* M41T0M6 real time clock */ +&rtc { + status = "okay"; +}; + +/* Colibri UART_A */ &uart1 { status = "okay"; }; +/* Colibri UART_B */ &uart2 { status = "okay"; }; +/* Colibri UART_C */ &uart3 { status = "okay"; }; +/* Colibri USBC */ &usbotg1 { status = "okay"; }; +/* Colibri MMC/SD */ &usdhc1 { - keep-power-in-suspend; - no-1-8-v; - wakeup-source; - vmmc-supply = <®_3v3>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi index 3caf450735d7..826f13da5b81 100644 --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi @@ -1,194 +1,110 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2016-2020 Toradex + * Copyright 2016-2022 Toradex */ / { - aliases { - rtc0 = &rtc; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* fixed crystal dedicated to mpc258x */ + /* Fixed crystal dedicated to MCP2515. */ clk16m: clk16m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <16000000>; }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - power { - label = "Wake-Up"; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; - -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3v3>; - - status = "okay"; }; +/* Colibri AD0 to AD3 */ &adc1 { status = "okay"; }; -&adc2 { - status = "okay"; +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 / INT */ + pinctrl-0 = <&pinctrl_atmel_adapter>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 / RST */ + status = "disabled"; }; +/* Colibri SSP */ &ecspi3 { status = "okay"; mcp2515: can@0 { + clocks = <&clk16m>; compatible = "microchip,mcp2515"; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can_int>; reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; spi-max-frequency = <10000000>; vdd-supply = <®_3v3>; xceiver-supply = <®_5v0>; - status = "okay"; }; }; +/* Colibri Fast Ethernet */ &fec1 { status = "okay"; }; +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ &i2c4 { status = "okay"; - - /* - * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiotouch>; - reg = <0x4a>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ - reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 */ - status = "disabled"; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc: m41t0m6@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -&lcdif { - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; }; +/* Colibri PWM<A> */ &pwm1 { status = "okay"; }; +/* Colibri PWM<B> */ &pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ status = "okay"; }; +/* Colibri PWM<C> */ &pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ status = "okay"; }; +/* Colibri PWM<D> */ &pwm4 { status = "okay"; }; +/* M41T0M6 real time clock */ +&rtc { + status = "okay"; +}; + +/* Colibri UART_A */ &uart1 { status = "okay"; }; +/* Colibri UART_B */ &uart2 { status = "okay"; }; +/* Colibri UART_C */ &uart3 { status = "okay"; }; +/* Colibri USBC */ &usbotg1 { status = "okay"; }; +/* Colibri MMC/SD */ &usdhc1 { - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; status = "okay"; }; - -&iomuxc { - pinctrl_gpiotouch: touchgpios { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 - MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi new file mode 100644 index 000000000000..6e199613583c --- /dev/null +++ b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/ { + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* SODIMM 100 */ + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3_vmmc"; + startup-delay-us = <100>; + }; +}; + +/* Colibri AD0 to AD3 */ +&adc1 { + status = "okay"; +}; + +/* Colibri SSP */ +&ecspi3 { + status = "okay"; +}; + +/* Colibri Fast Ethernet */ +&fec1 { + status = "okay"; +}; + +&gpio2 { + /* + * uart_b_c_on_x14_enable turns the UART transceiver for UART2 and 5 on. If one wants to + * turn the transceiver off, that property has to be deleted and the gpio handled in + * userspace. + * The same applies to uart_a_on_x13_enable where the UART_A transceiver is turned on. + */ + uart-b-c-on-x14-enable-hog { + gpio-hog; + gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ + output-high; + }; +}; + +&gpio5 { + uart-a-on-x13-enable-hog { + gpio-hog; + gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ + output-high; + }; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c4 { + status = "okay"; +}; + +/* Colibri PWM<A> */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM<B> */ +&pwm2 { + status = "okay"; +}; + +/* Colibri PWM<C> */ +&pwm3 { + status = "okay"; +}; + +/* Colibri PWM<D> */ +&pwm4 { + status = "okay"; +}; + +/* M41T0M6 real time clock */ +&rtc { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + status = "okay"; +}; + +/* Colibri UART_B */ +&uart2 { + status = "okay"; +}; + +/* Colibri UART_C */ +&uart3 { + status = "okay"; +}; + +/* Colibri USBC */ +&usbotg1 { + status = "okay"; +}; + +/* Colibri MMC/SD, UHS-I capable uSD slot */ +&usdhc1 { + cap-power-off-card; + /delete-property/ keep-power-in-suspend; + /delete-property/ no-1-8-v; + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7-colibri-iris.dtsi b/arch/arm/boot/dts/imx7-colibri-iris.dtsi new file mode 100644 index 000000000000..175c5d478d2e --- /dev/null +++ b/arch/arm/boot/dts/imx7-colibri-iris.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/* Colibri AD0 to AD3 */ +&adc1 { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 / INT */ + pinctrl-0 = <&pinctrl_atmel_adapter>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 / RST */ +}; + +/* Colibri SSP */ +&ecspi3 { + status = "okay"; +}; + +/* Colibri Fast Ethernet */ +&fec1 { + status = "okay"; +}; + +&gpio2 { + /* + * uart25 turns the UART transceiver for UART2 and 5 on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled in userspace. + * The same applies to uart1_tx_on where the UART1 transceiver is turned on. + */ + uart25-tx-on-hog { + gpio-hog; + gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ + output-high; + }; +}; + +&gpio5 { + uart1-tx-on-hog { + gpio-hog; + gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ + output-high; + }; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c4 { + status = "okay"; +}; + +/* Colibri PWM<A> */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM<B> */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM<C> */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM<D> */ +&pwm4 { + status = "okay"; +}; + +/* M41T0M6 real time clock */ +&rtc { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + status = "okay"; +}; + +/* Colibri UART_B */ +&uart2 { + status = "okay"; +}; + +/* Colibri UART_C */ +&uart3 { + status = "okay"; +}; + +/* Colibri USBC */ +&usbotg1 { + status = "okay"; +}; + +/* Colibri MMC/SD */ +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 62b771c1d5a9..a8c31ee65623 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -1,96 +1,198 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2016-2020 Toradex + * Copyright 2016-2022 Toradex */ +#include <dt-bindings/pwm/pwm.h> + / { - bl: backlight { + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + + backlight: backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; compatible = "pwm-backlight"; + default-brightness-level = <4>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm1 0 5000000 0>; - enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + power-supply = <®_module_3v3>; + pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; }; - reg_module_3v3: regulator-module-3v3 { + chosen { + stdout-path = "serial0:115200n8"; + }; + + extcon_usbc_det: usbc-det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + wakeup { + debounce-interval = <10>; + gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ + label = "Wake-Up"; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + panel_dpi: panel-dpi { + backlight = <&backlight>; + compatible = "edt,et057090dhu"; + power-supply = <®_3v3>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; + + reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; + regulator-always-on; regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V"; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "5V"; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3"; }; reg_module_3v3_avdd: regulator-module-3v3-avdd { compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; regulator-name = "+V3.3_AVDD_AUDIO"; + }; + + reg_module_3v3_eth: regulator-module-3v3-eth { + compatible = "regulator-fixed"; + off-on-delay-us = <200000>; + regulator-name = "+V3.3_ETH"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; + regulator-boot-on; + startup-delay-us = <200000>; + vin-supply = <®_LDO1>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "VCC_USB[1-4]"; + vin-supply = <®_5v0>; }; sound { compatible = "simple-audio-card"; - simple-audio-card,name = "imx7-sgtl5000"; - simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx7-sgtl5000"; + simple-audio-card,cpu { sound-dai = <&sai1>; }; dailink_master: simple-audio-card,codec { + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; sound-dai = <&codec>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; }; }; }; +/* Colibri AD0 to AD3 */ &adc1 { vref-supply = <®_DCDC3>; }; -&adc2 { - vref-supply = <®_DCDC3>; -}; +/* ADC2 is not available as it conflicts with AD7879 resistive touchscreen. */ &cpu0 { cpu-supply = <®_DCDC2>; }; +/* Colibri SSP */ &ecspi3 { + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* SODIMM 86 / SSPFRM */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; - cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; }; +/* Colibri Fast Ethernet */ &fec1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_enet1>; - pinctrl-1 = <&pinctrl_enet1_sleep>; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; - clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; assigned-clock-rates = <0>, <100000000>; - phy-mode = "rmii"; - phy-supply = <®_LDO1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; fsl,magic-packet; + phy-handle = <ðphy0>; + phy-mode = "rmii"; + phy-supply = <®_module_3v3_eth>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-1 = <&pinctrl_enet1_sleep>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Micrel KSZ8041RNL */ + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + micrel,led-mode = <0>; + reg = <0>; + }; + }; }; &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; }; &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; - status = "disabled"; }; &gpio1 { @@ -271,14 +373,16 @@ "SODIMM_137"; }; +/* NAND on such SKUs */ &gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; fsl,use-minimum-ecc; - nand-on-flash-bbt; nand-ecc-mode = "hw"; + nand-on-flash-bbt; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; }; +/* On-module Power I2C */ &i2c1 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; @@ -286,33 +390,33 @@ pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>; scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; #sound-dai-cells = <0>; - reg = <0x0a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1_mclk>; + reg = <0xa>; VDDA-supply = <®_module_3v3_avdd>; - VDDIO-supply = <®_module_3v3>; VDDD-supply = <®_DCDC3>; + VDDIO-supply = <®_module_3v3>; }; - ad7879@2c { + ad7879_ts: touchscreen@2c { + adi,acquisition-time = /bits/ 8 <1>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,median-filter-size = /bits/ 8 <2>; + adi,resistance-plate-x = <120>; compatible = "adi,ad7879-1"; - reg = <0x2c>; interrupt-parent = <&gpio1>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + reg = <0x2c>; touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; + status = "disabled"; }; pmic@33 { @@ -320,71 +424,81 @@ reg = <0x33>; regulators { - reg_DCDC1: DCDC1 { /* V1.0_SOC */ - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; + reg_DCDC1: DCDC1 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1000000>; + regulator-name = "+V1.0_SOC"; }; - reg_DCDC2: DCDC2 { /* V1.1_ARM */ - regulator-min-microvolt = <975000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; + reg_DCDC2: DCDC2 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <975000>; + regulator-name = "+V1.1_ARM"; }; - reg_DCDC3: DCDC3 { /* V1.8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; + reg_DCDC3: DCDC3 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8"; }; - reg_DCDC4: DCDC4 { /* V1.35_DRAM */ - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; + reg_DCDC4: DCDC4 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <1350000>; + regulator-name = "+V1.35_DRAM"; }; - reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + reg_LDO1: LDO1 { regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PWR_EN_+V3.3_ETH"; }; - reg_LDO2: LDO2 { /* +V1.8_SD */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; + reg_LDO2: LDO2 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SD"; }; - reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; + reg_LDO3: LDO3 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PWR_EN_+V3.3_LPSR"; }; - reg_LDO4: LDO4 { /* V1.8_LPSR */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; + reg_LDO4: LDO4 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_LPSR"; }; - reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; + reg_LDO5: LDO5 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PWR_EN_+V3.3"; }; }; }; }; +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ &i2c4 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; @@ -392,36 +506,69 @@ pinctrl-1 = <&pinctrl_i2c4_recovery>; scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "disabled"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_connector>; + reg = <0x4a>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + status = "disabled"; + }; }; &lcdif { + assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + status = "disabled"; + + port { + lcdif_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; }; +/* Colibri PWM<A> */ &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; }; +/* Colibri PWM<B> */ &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; }; +/* Colibri PWM<C> */ &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; }; +/* Colibri PWM<D> */ &pwm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; }; ®_1p0d { - vin-supply = <®_DCDC3>; + vin-supply = <®_DCDC3>; /* VDDA_1P8_IN */ }; &sai1 { @@ -430,237 +577,257 @@ status = "okay"; }; +/* Colibri UART_A */ &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>; assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - uart-has-rtscts; fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>; + uart-has-rtscts; }; +/* Colibri UART_B */ &uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - uart-has-rtscts; fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; }; +/* Colibri UART_C */ &uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; }; +/* Colibri USBC */ &usbotg1 { - dr_mode = "host"; + dr_mode = "otg"; + extcon = <0>, <&extcon_usbc_det>; }; +/* Colibri MMC/SD */ &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; disable-wp; + no-1-8-v; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>; + pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>; + vmmc-supply = <®_3v3>; vqmmc-supply = <®_LDO2>; + wakeup-source; }; +/* eMMC on 1GB (eMMC) SKUs */ &usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; assigned-clock-rates = <400000000>; bus-width = <8>; fsl,tuning-step = <2>; - vmmc-supply = <®_module_3v3>; - vqmmc-supply = <®_DCDC3>; non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; sdhci-caps-mask = <0x80000000 0x0>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <®_DCDC3>; }; &iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4 - &pinctrl_gpio7 &pinctrl_usbc_det>; - - pinctrl_gpio1: gpio1-grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */ - MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */ - MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ - MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */ - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */ - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */ - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */ - MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */ - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */ - MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ - MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ - MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ - MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */ - MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ - MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ - MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ - MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ - MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ - MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */ - MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */ - MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */ - MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */ - MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */ - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */ - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */ - MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */ - MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */ - MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */ - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */ - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */ - MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */ - MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */ - >; - }; - - pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */ - fsl,pins = < - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */ - MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ - MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ - MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ - MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */ - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */ - MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */ - MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */ - MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */ - MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */ - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */ - >; - }; - - pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */ + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>; + + /* + * Atmel MXT touchsceen + Capacitive Touch Adapter + * NOTE: This pin group conflicts with pin groups pinctrl_pwm2/pinctrl_pwm3. + * Don't use them simultaneously. + */ + pinctrl_atmel_adapter: atmelconnectorgrp { fsl,pins = < - MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */ - MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ - MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ - MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ - MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */ - MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 /* SODIMM 28 / INT */ + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 /* SODIMM 30 / RST */ >; }; - pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */ + /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ + pinctrl_atmel_connector: atmeladaptergrp { fsl,pins = < - MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */ - MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 / RST */ + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 / INT */ >; }; - pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */ + pinctrl_can_int: canintgrp { fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ - MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ >; }; - pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */ + pinctrl_ecspi3: ecspi3grp { fsl,pins = < - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79 + MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 /* SODIMM 90 */ + MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 /* SODIMM 92 */ + MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 /* SODIMM 88 */ >; }; - pinctrl_can_int: can-int-grp { + pinctrl_ecspi3_cs: ecspi3csgrp { fsl,pins = < - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 /* SODIMM 86 */ >; }; pinctrl_enet1: enet1grp { fsl,pins = < - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 - - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 MX7D_PAD_SD2_WP__ENET1_MDC 0x3 >; }; - pinctrl_enet1_sleep: enet1sleepgrp { + pinctrl_enet1_sleep: enet1-sleepgrp { fsl,pins = < - MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0 MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0 MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0 - - MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0 + MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0 MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0 MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0 + MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0 MX7D_PAD_SD2_WP__GPIO5_IO10 0x0 >; }; - pinctrl_ecspi3_cs: ecspi3-cs-grp { + pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 + MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */ + MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */ >; }; - pinctrl_ecspi3: ecspi3-grp { + pinctrl_flexcan2: flexcan2grp { fsl,pins = < - MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 - MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 - MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */ + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */ >; }; - pinctrl_flexcan1: flexcan1-grp { + pinctrl_gpio1: gpio1grp { fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */ - MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */ + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */ + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */ + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */ + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */ + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */ + MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */ + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */ + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */ + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */ + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */ + MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */ + MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ + MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */ + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */ + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */ + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */ + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ + MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */ + MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */ + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */ + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */ + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */ + MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */ + MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */ + MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ + MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ + MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ >; }; - pinctrl_flexcan2: flexcan2-grp { + pinctrl_gpio2: gpio2grp { /* On X22 Camera interface */ fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */ - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */ + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */ + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */ + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */ + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */ + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */ + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */ + MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */ + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */ + >; + }; + + pinctrl_gpio3: gpio3grp { /* LCD 18-23 */ + fsl,pins = < + MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */ + MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ + MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ + MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */ + MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */ + >; + }; + + pinctrl_gpio4: gpio4grp { /* Alternatively CAN2 */ + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */ + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */ + >; + }; + + pinctrl_gpio7: gpio7grp { /* Alternatively CAN1 */ + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ >; }; - pinctrl_gpio_bl_on: gpio-bl-on { + pinctrl_gpio_bl_on: gpioblongrp { fsl,pins = < MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ >; }; - pinctrl_gpmi_nand: gpmi-nand-grp { + pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < - MX7D_PAD_SD3_CLK__NAND_CLE 0x71 - MX7D_PAD_SD3_CMD__NAND_ALE 0x71 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 - MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 - MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 @@ -669,13 +836,21 @@ MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 >; }; - pinctrl_i2c4: i2c4-grp { + pinctrl_i2c1_int: i2c1intgrp { /* PMIC / TOUCH */ fsl,pins = < - MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f - MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f /* SODIMM 196 */ + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f /* SODIMM 194 */ >; }; @@ -686,155 +861,176 @@ >; }; - pinctrl_lcdif_dat: lcdif-dat-grp { + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 /* SODIMM 76 */ + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 /* SODIMM 70 */ + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 /* SODIMM 60 */ + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 /* SODIMM 58 */ + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 /* SODIMM 78 */ + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 /* SODIMM 72 */ + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 /* SODIMM 80 */ + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 /* SODIMM 46 */ + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 /* SODIMM 62 */ + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 /* SODIMM 48 */ + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 /* SODIMM 74 */ + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 /* SODIMM 50 */ + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 /* SODIMM 52 */ + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 /* SODIMM 54 */ + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 /* SODIMM 66 */ + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 /* SODIMM 64 */ + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 /* SODIMM 57 */ + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 /* SODIMM 61 */ + >; + }; + + pinctrl_lcdif_dat_24: lcdifdat24grp { fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 /* SODIMM 136 */ + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 /* SODIMM 138 */ + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 /* SODIMM 140 */ + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 /* SODIMM 142 */ + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 /* SODIMM 144 */ + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 /* SODIMM 146 */ >; }; - pinctrl_lcdif_dat_24: lcdif-dat-24-grp { + pinctrl_lcdif_ctrl: lcdifctrlgrp { fsl,pins = < - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 /* SODIMM 56 */ + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 /* SODIMM 44 */ + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 /* SODIMM 68 */ + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 /* SODIMM 82 */ >; }; - pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + pinctrl_lvds_transceiver: lvdstx { fsl,pins = < - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */ + MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ >; }; - pinctrl_pwm1: pwm1-grp { + pinctrl_pwm1: pwm1grp { fsl,pins = < - MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 /* SODIMM 59 */ + MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 /* SODIMM 59 */ >; }; - pinctrl_pwm2: pwm2-grp { + pinctrl_pwm2: pwm2grp { fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 + MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 /* SODIMM 28 */ >; }; - pinctrl_pwm3: pwm3-grp { + pinctrl_pwm3: pwm3grp { fsl,pins = < - MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 + MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 /* SODIMM 30 */ >; }; - pinctrl_pwm4: pwm4-grp { + pinctrl_pwm4: pwm4grp { fsl,pins = < - MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 - MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 /* SODIMM 67 */ + MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 /* SODIMM 67 */ >; }; - pinctrl_uart1: uart1-grp { + pinctrl_uart1: uart1grp { fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 - MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 - MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 /* SODIMM 25 */ + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 /* SODIMM 27 */ + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 /* SODIMM 35 */ + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 /* SODIMM 33 */ >; }; - pinctrl_uart1_ctrl1: uart1-ctrl1-grp { + pinctrl_uart1_ctrl1: uart1ctrl1grp { fsl,pins = < - MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ - MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ + MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* SODIMM 23 / DTR */ + MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* SODIMM 31 / DCD */ >; }; - pinctrl_uart2: uart2-grp { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 /* SODIMM 32 / CTS */ + MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 /* SODIMM 34 / RTS */ + MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 /* SODIMM 38 */ + MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 /* SODIMM 36 */ + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < - MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 - MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 - MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 - MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 /* SODIMM 21 */ + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 /* SODIMM 19 */ >; }; - pinctrl_uart3: uart3-grp { + + pinctrl_usbc_det: usbcdetgrp { fsl,pins = < - MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 - MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 /* SODIMM 137 / USBC_DET */ >; }; - pinctrl_usbc_det: gpio-usbc-det { + pinctrl_usbh_reg: usbhreggrp { fsl,pins = < - MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 / USBH_PEN */ >; }; - pinctrl_usbh_reg: gpio-usbh-vbus { + pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */ + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 /* SODIMM 47 */ + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 /* SODIMM 190 */ + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 /* SODIMM 192 */ + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 /* SODIMM 49 */ + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 /* SODIMM 51 */ + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 /* SODIMM 53 */ >; }; - pinctrl_usdhc1: usdhc1-grp { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a >; }; - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b >; }; - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + /* Avoid backfeeding with removed card power. */ + pinctrl_usdhc1_sleep: usdhc1-slpgrp { fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + MX7D_PAD_SD1_CMD__SD1_CMD 0x10 + MX7D_PAD_SD1_CLK__SD1_CLK 0x10 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x10 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x10 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x10 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x10 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 @@ -847,10 +1043,10 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a @@ -863,10 +1059,10 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b @@ -879,16 +1075,16 @@ >; }; - pinctrl_sai1: sai1-grp { + pinctrl_sai1: sai1grp { fsl,pins = < - MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f >; }; - pinctrl_sai1_mclk: sai1grp_mclk { + pinctrl_sai1_mclk: sai1mclkgrp { fsl,pins = < MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f >; @@ -899,23 +1095,35 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_lpsr>; - pinctrl_gpio_lpsr: gpio1-grp { + pinctrl_cd_usdhc1: cdusdhc1grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 - MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 + MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* SODIMM 43 / MMC_CD */ + >; + }; + + pinctrl_cd_usdhc1_sleep: cdusdhc1-slpgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0 + >; + }; + + pinctrl_gpio_lpsr: gpiolpsrgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 /* SODIMM 135 */ + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 /* SODIMM 22 */ >; }; pinctrl_gpiokeys: gpiokeysgrp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 /* SODIMM 45 / WAKE_UP */ >; }; - pinctrl_i2c1: i2c1-grp { + pinctrl_i2c1: i2c1grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f >; }; @@ -926,16 +1134,10 @@ >; }; - pinctrl_cd_usdhc1: usdhc1-cd-grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */ - >; - }; - - pinctrl_uart1_ctrl2: uart1-ctrl2-grp { + pinctrl_uart1_ctrl2: uart1ctrl2grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */ - MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */ + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* SODIMM 37 / RI */ + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* SODIMM 29 / DSR */ >; }; }; diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 49086c6b6a0a..3df6dff7734a 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -302,7 +302,7 @@ tlv320aic32x4: audio-codec@18 { compatible = "ti,tlv320aic32x4"; reg = <0x18>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; clock-names = "mclk"; ldoin-supply = <®_audio_3v3>; iov-supply = <®_audio_3v3>; diff --git a/arch/arm/boot/dts/imx7d-colibri-aster.dts b/arch/arm/boot/dts/imx7d-colibri-aster.dts index f3f0537d5a37..90aaeddfb4f6 100644 --- a/arch/arm/boot/dts/imx7d-colibri-aster.dts +++ b/arch/arm/boot/dts/imx7d-colibri-aster.dts @@ -1,7 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017-2020 Toradex AG - * + * Copyright 2017-2022 Toradex */ /dts-v1/; @@ -10,11 +9,32 @@ / { model = "Toradex Colibri iMX7D on Aster Carrier Board"; - compatible = "toradex,colibri-imx7d-aster", "toradex,colibri-imx7d", + compatible = "toradex,colibri-imx7d-aster", + "toradex,colibri-imx7d", "fsl,imx7d"; }; +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri USBH */ &usbotg2 { - vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts index 20480276cb0e..3ec9ef6baaa4 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017-2020 Toradex AG + * Copyright 2017-2022 Toradex * */ @@ -11,10 +11,12 @@ / { model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board"; compatible = "toradex,colibri-imx7d-emmc-aster", - "toradex,colibri-imx7d-emmc", "fsl,imx7d"; + "toradex,colibri-imx7d-emmc", + "toradex,colibri-imx7d", + "fsl,imx7d"; }; +/* Colibri USBH */ &usbotg2 { - vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts index 8ee73c870b12..6d505cb02aad 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017 Toradex AG + * Copyright 2017-2022 Toradex */ /dts-v1/; @@ -10,10 +10,12 @@ / { model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx7d-emmc-eval-v3", - "toradex,colibri-imx7d-emmc", "fsl,imx7d"; + "toradex,colibri-imx7d-emmc", + "toradex,colibri-imx7d", + "fsl,imx7d"; }; +/* Colibri USBH */ &usbotg2 { - vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts new file mode 100644 index 000000000000..7347659557f3 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB on Iris V2 Carrier Board"; + compatible = "toradex,colibri-imx7d-emmc-iris-v2", + "toradex,colibri-imx7d-emmc", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +/* Colibri USBH */ +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts new file mode 100644 index 000000000000..5324c92e368d --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB on Iris Carrier Board"; + compatible = "toradex,colibri-imx7d-emmc-iris", + "toradex,colibri-imx7d-emmc", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +/* Colibri USBH */ +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi index af39e5370fa1..2fb4d2133a1b 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi +++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi @@ -1,18 +1,28 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017 Toradex AG + * Copyright 2017-2022 Toradex */ #include "imx7d.dtsi" #include "imx7-colibri.dtsi" / { + aliases { + /* Required to properly pass MAC addresses from bootloader. */ + ethernet0 = &fec1; + ethernet1 = &fec2; + }; + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; }; }; +&cpu1 { + cpu-supply = <®_DCDC2>; +}; + &gpio6 { gpio-line-names = "", "", @@ -39,10 +49,13 @@ "SODIMM_34"; }; +/* Colibri USBH */ &usbotg2 { dr_mode = "host"; + vbus-supply = <®_usbh_vbus>; }; +/* eMMC */ &usdhc3 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts index 87b132bcd272..c7a8b5aa2408 100644 --- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2016-2020 Toradex + * Copyright 2016-2022 Toradex */ /dts-v1/; @@ -9,11 +9,48 @@ / { model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d", + compatible = "toradex,colibri-imx7d-eval-v3", + "toradex,colibri-imx7d", "fsl,imx7d"; }; +&ad7879_ts { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + status = "disabled"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri PWM<B> */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM<C> */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri USBH */ &usbotg2 { - vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts new file mode 100644 index 000000000000..5762f51d5f0f --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Iris V2 Carrier Board"; + compatible = "toradex,colibri-imx7d-iris-v2", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; + +&gpio7 { + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; + + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* This turns the LVDS transceiver on */ + lvds-power-on-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri USBH */ +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-iris.dts b/arch/arm/boot/dts/imx7d-colibri-iris.dts new file mode 100644 index 000000000000..9c63cb9d9a64 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-iris.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Iris Carrier Board"; + compatible = "toradex,colibri-imx7d-iris", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +&ad7879_ts { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + status = "disabled"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri PWM<B> */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM<C> */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri USBH */ +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi index 219a0404a058..531a45b176a1 100644 --- a/arch/arm/boot/dts/imx7d-colibri.dtsi +++ b/arch/arm/boot/dts/imx7d-colibri.dtsi @@ -1,12 +1,18 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2016-2020 Toradex + * Copyright 2016-2022 Toradex */ #include "imx7d.dtsi" #include "imx7-colibri.dtsi" / { + aliases { + /* Required to properly pass MAC addresses from bootloader. */ + ethernet0 = &fec1; + ethernet1 = &fec2; + }; + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; @@ -17,10 +23,13 @@ cpu-supply = <®_DCDC2>; }; +/* NAND */ &gpmi { status = "okay"; }; +/* Colibri USBH */ &usbotg2 { dr_mode = "host"; + vbus-supply = <®_usbh_vbus>; }; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index e0751e6ba3c0..a31de900139d 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -288,7 +288,7 @@ codec: wm8960@1a { compatible = "wlf,wm8960"; reg = <0x1a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; clock-names = "mclk"; wlf,shared-lrclk; }; diff --git a/arch/arm/boot/dts/imx7d-pico-hobbit.dts b/arch/arm/boot/dts/imx7d-pico-hobbit.dts index 7b2198a9372c..d917dc4f2f22 100644 --- a/arch/arm/boot/dts/imx7d-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx7d-pico-hobbit.dts @@ -31,7 +31,7 @@ dailink_master: simple-audio-card,codec { sound-dai = <&sgtl5000>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; }; }; }; @@ -41,7 +41,7 @@ #sound-dai-cells = <0>; reg = <0x0a>; compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_vref_1v8>; }; diff --git a/arch/arm/boot/dts/imx7d-pico-pi.dts b/arch/arm/boot/dts/imx7d-pico-pi.dts index 70bea95c06d8..f263e391e24c 100644 --- a/arch/arm/boot/dts/imx7d-pico-pi.dts +++ b/arch/arm/boot/dts/imx7d-pico-pi.dts @@ -31,7 +31,7 @@ dailink_master: simple-audio-card,codec { sound-dai = <&sgtl5000>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; }; }; }; @@ -41,7 +41,7 @@ #sound-dai-cells = <0>; reg = <0x0a>; compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_vref_1v8>; }; diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi index e519897fae08..e0bff39e8d3e 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -41,7 +41,7 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; enable-active-high; - }; + }; reg_wlreg_on: regulator-wlreg_on { compatible = "regulator-fixed"; @@ -432,7 +432,7 @@ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */ + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */ >; }; @@ -493,19 +493,19 @@ pinctrl_pwm1: pwm1 { fsl,pins = < - MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f + MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f >; }; pinctrl_pwm2: pwm2 { fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f + MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f >; }; pinctrl_pwm3: pwm3 { fsl,pins = < - MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f + MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f >; }; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 7813ef960f6e..f483bc0afe5e 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -24,14 +24,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -39,7 +39,7 @@ }; }; - spi4 { + spi-4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; @@ -201,17 +201,12 @@ compatible = "ti,tsc2046"; reg = <0>; spi-max-frequency = <1000000>; - pinctrl-names ="default"; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc2046_pendown>; interrupt-parent = <&gpio2>; interrupts = <29 0>; pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <0>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <0>; - ti,pressure-max = /bits/ 16 <0>; - ti,x-plate-ohms = /bits/ 16 <400>; + touchscreen-max-pressure = <255>; wakeup-source; }; }; @@ -385,14 +380,14 @@ codec: wm8960@1a { compatible = "wlf,wm8960"; reg = <0x1a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; clock-names = "mclk"; wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, <&clks IMX7D_PLL_AUDIO_POST_DIV>, - <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; assigned-clock-rates = <0>, <884736000>, <12288000>; }; diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts new file mode 100644 index 000000000000..546268b8d0b1 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-smegw01.dts @@ -0,0 +1,467 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright (C) 2020 PHYTEC Messtechnik GmbH +// Author: Jens Lang <J.Lang@phytec.de> +// Copyright (C) 2021 Fabio Estevam <festevam@denx.de> + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "imx7d.dtsi" + +/ { + model = "Storopack SMEGW01 board"; + compatible = "storopack,imx7d-smegw01", "fsl,imx7d"; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc3; + mmc2 = &usdhc2; + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_lte_on: regulator-lte-on { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lte_on>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "lte_on"; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_lte_nreset: regulator-lte-nreset { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lte_nreset>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "LTE_nReset"; + gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + regulator-name = "wifi_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_wlan_rfkill: regulator-wlan-rfkill { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-2 = <&pinctrl_rfkill>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "wlan_rfkill"; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + sram@0 { + compatible = "microchip,48l640"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + i2c_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + reg = <0x52>; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_lpsr>; + dr_mode = "otg"; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + wakeup-source; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + non-removable; + vmmc-supply = <®_wifi>; + wakeup-source; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + max-frequency = <200000000>; + bus-width = <8>; + fsl,tuning-step = <1>; + non-removable; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04 + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5 + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5 + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5 + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004 + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0 + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0 + >; + }; + + pinctrl_lte_on: lteongrp { + fsl,pins = < + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059 + >; + }; + + pinctrl_lte_nreset: ltenresetgrp { + fsl,pins = < + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059 + >; + }; + + pinctrl_rfkill: rfkillrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74 + >; + }; + + pinctrl_usbotg1_lpsr: usbotg1 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04 + >; + }; + + pinctrl_usbotg1_pwr: usbotg1-pwr { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04 + >; + }; + + pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpio { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04 + >; + }; + + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x04 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5d + MX7D_PAD_SD3_CLK__SD3_CLK 0x1d + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5e + MX7D_PAD_SD3_CLK__SD3_CLK 0x1e + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5f + MX7D_PAD_SD3_CLK__SD3_CLK 0x0f + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-zii-rmu2.dts b/arch/arm/boot/dts/imx7d-zii-rmu2.dts index 1065941807e8..1c9f25848bf7 100644 --- a/arch/arm/boot/dts/imx7d-zii-rmu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rmu2.dts @@ -24,7 +24,7 @@ pinctrl-0 = <&pinctrl_leds_debug>; pinctrl-names = "default"; - debug { + led-debug { label = "zii:green:debug1"; gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts index 893bd30aa2a3..9d29490ab4c9 100644 --- a/arch/arm/boot/dts/imx7d-zii-rpu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rpu2.dts @@ -36,7 +36,7 @@ pinctrl-0 = <&pinctrl_leds_debug>; pinctrl-names = "default"; - debug { + led-debug { label = "zii:green:debug1"; gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index b7735979b7e4..7ceb7c09f7ad 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -78,7 +78,7 @@ #phy-cells = <0>; }; - soc { + soc: soc { etm@3007d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x3007d000 0x1000>; @@ -113,6 +113,49 @@ <0x31004000 0x2000>, <0x31006000 0x2000>; }; + + pcie: pcie@33800000 { + compatible = "fsl,imx7d-pcie"; + reg = <0x33800000 0x4000>, + <0x4ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */ + <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + /* + * Reference manual lists pci irqs incorrectly + * Real hardware ordering is same as imx6: D+MSI, C, B, A + */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, + <&clks IMX7D_PCIE_PHY_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie_phy>; + resets = <&src IMX7_RESET_PCIEPHY>, + <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + status = "disabled"; + }; }; }; @@ -162,49 +205,6 @@ fsl,stop-mode = <&gpr 0x10 4>; status = "disabled"; }; - - pcie: pcie@33800000 { - compatible = "fsl,imx7d-pcie"; - reg = <0x33800000 0x4000>, - <0x4ff00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */ - <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - /* - * Reference manual lists pci irqs incorrectly - * Real hardware ordering is same as imx6: D+MSI, C, B, A - */ - interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, - <&clks IMX7D_PCIE_PHY_ROOT_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy"; - assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, - <&clks IMX7D_PCIE_PHY_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - - fsl,max-link-speed = <2>; - power-domains = <&pgc_pcie_phy>; - resets = <&src IMX7_RESET_PCIEPHY>, - <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, - <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; - fsl,imx7d-pcie-phy = <&pcie_phy>; - status = "disabled"; - }; }; &ca_funnel_in_ports { diff --git a/arch/arm/boot/dts/imx7s-colibri-aster.dts b/arch/arm/boot/dts/imx7s-colibri-aster.dts index fca4e0a95c1b..58ebb02d948a 100644 --- a/arch/arm/boot/dts/imx7s-colibri-aster.dts +++ b/arch/arm/boot/dts/imx7s-colibri-aster.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017-2020 Toradex AG + * Copyright 2017-2022 Toradex * */ @@ -10,6 +10,27 @@ / { model = "Toradex Colibri iMX7S on Aster Carrier Board"; - compatible = "toradex,colibri-imx7s-aster", "toradex,colibri-imx7s", + compatible = "toradex,colibri-imx7s-aster", + "toradex,colibri-imx7s", "fsl,imx7s"; }; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts index aa70d3f2e2e2..38de76630d6a 100644 --- a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2016-2020 Toradex + * Copyright 2016-2022 Toradex */ /dts-v1/; @@ -9,6 +9,43 @@ / { model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx7s-eval-v3", "toradex,colibri-imx7s", + compatible = "toradex,colibri-imx7s-eval-v3", + "toradex,colibri-imx7s", "fsl,imx7s"; }; + +&ad7879_ts { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + status = "disabled"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri PWM<B> */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM<C> */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts new file mode 100644 index 000000000000..72b5c17ab1ab --- /dev/null +++ b/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Iris V2 Carrier Board"; + compatible = "toradex,colibri-imx7s-iris-v2", + "toradex,colibri-imx7s", + "fsl,imx7s"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; + +&gpio7 { + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; + + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* This turns the LVDS transceiver on */ + lvds-power-on-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri-iris.dts b/arch/arm/boot/dts/imx7s-colibri-iris.dts new file mode 100644 index 000000000000..26ba72c17feb --- /dev/null +++ b/arch/arm/boot/dts/imx7s-colibri-iris.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Iris Carrier Board"; + compatible = "toradex,colibri-imx7s-iris", + "toradex,colibri-imx7s", + "fsl,imx7s"; +}; + +&ad7879_ts { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + status = "disabled"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri PWM<B> */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM<C> */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi index 94de220a5965..ef51395d3537 100644 --- a/arch/arm/boot/dts/imx7s-colibri.dtsi +++ b/arch/arm/boot/dts/imx7s-colibri.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2016-2020 Toradex + * Copyright 2016-2022 Toradex */ #include "imx7s.dtsi" @@ -13,6 +13,7 @@ }; }; +/* NAND */ &gpmi { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 4f1edef06c92..e8734d218b9d 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -75,7 +75,7 @@ dailink_master: simple-audio-card,codec { sound-dai = <&codec>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; }; }; }; @@ -232,7 +232,7 @@ #sound-dai-cells = <0>; reg = <0x0a>; compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1_mclk>; VDDA-supply = <&vgen4_reg>; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 52a9aeecdbb2..0fc9e6b8b05d 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -76,6 +76,22 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; cpu-idle-states = <&cpu_sleep_wait>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + nvmem-cells = <&fuse_grade>; + nvmem-cell-names = "speed_grade"; + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0xf>, <0xf>; }; }; @@ -104,6 +120,7 @@ compatible = "usb-nop-xceiv"; clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; clock-names = "main_clk"; + power-domains = <&pgc_hsic_phy>; #phy-cells = <0>; }; @@ -159,7 +176,7 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -430,7 +447,7 @@ status = "disabled"; }; - iomuxc_lpsr: iomuxc-lpsr@302c0000 { + iomuxc_lpsr: pinctrl@302c0000 { compatible = "fsl,imx7d-iomuxc-lpsr"; reg = <0x302c0000 0x10000>; fsl,input-sel = <&iomuxc>; @@ -1137,7 +1154,6 @@ compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b30000 0x200>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&pgc_hsic_phy>; clocks = <&clks IMX7D_USB_CTRL_CLK>; fsl,usbphy = <&usbphynop3>; fsl,usbmisc = <&usbmisc3 0>; @@ -1208,7 +1224,7 @@ status = "disabled"; }; - sdma: sdma@30bd0000 { + sdma: dma-controller@30bd0000 { compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; reg = <0x30bd0000 0x10000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index b7ea37ad4e55..7f7d2d5122fb 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -259,7 +259,7 @@ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pcc2 IMX7ULP_CLK_WDG1>; assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; timeout-sec = <40>; }; @@ -328,8 +328,9 @@ compatible = "fsl,imx7ulp-lpi2c"; reg = <0x40a40000 0x10000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; - clock-names = "ipg"; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "per", "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; assigned-clock-rates = <48000000>; @@ -340,8 +341,9 @@ compatible = "fsl,imx7ulp-lpi2c"; reg = <0x40a50000 0x10000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; - clock-names = "ipg"; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "per", "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; assigned-clock-rates = <48000000>; diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/imxrt1050-evk.dts new file mode 100644 index 000000000000..6a9c10decf52 --- /dev/null +++ b/arch/arm/boot/dts/imxrt1050-evk.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +/dts-v1/; +#include "imxrt1050.dtsi" +#include "imxrt1050-pinfunc.h" + +/ { + model = "NXP IMXRT1050-evk board"; + compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + serial0 = &lpuart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x2000000>; + }; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 + MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 + MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 + MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imxrt1050-pinfunc.h b/arch/arm/boot/dts/imxrt1050-pinfunc.h new file mode 100644 index 000000000000..22c14a3262ad --- /dev/null +++ b/arch/arm/boot/dts/imxrt1050-pinfunc.h @@ -0,0 +1,993 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H + +#define IMX_PAD_SION 0x40000000 + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ + +#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4 +#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3 +#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4 + +#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4 + +#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2 + +#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0 + +#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi new file mode 100644 index 000000000000..03e6a858a7be --- /dev/null +++ b/arch/arm/boot/dts/imxrt1050.dtsi @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +#include "armv7-m.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/imxrt1050-clock.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + clocks { + osc: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + osc3M: osc3M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3000000>; + }; + }; + + soc { + lpuart1: serial@40184000 { + compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x40184000 0x4000>; + interrupts = <20>; + clocks = <&clks IMXRT1050_CLK_LPUART1>; + clock-names = "ipg"; + status = "disabled"; + }; + + iomuxc: pinctrl@401f8000 { + compatible = "fsl,imxrt1050-iomuxc"; + reg = <0x401f8000 0x4000>; + fsl,mux_mask = <0x7>; + }; + + anatop: anatop@400d8000 { + compatible = "fsl,imxrt-anatop"; + reg = <0x400d8000 0x4000>; + }; + + clks: clock-controller@400fc000 { + compatible = "fsl,imxrt1050-ccm"; + reg = <0x400fc000 0x4000>; + interrupts = <95>, <96>; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, + <&clks IMXRT1050_CLK_PLL1_BYPASS>, + <&clks IMXRT1050_CLK_PLL2_BYPASS>, + <&clks IMXRT1050_CLK_PLL3_BYPASS>, + <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, + <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, + <&clks IMXRT1050_CLK_PLL1_ARM>, + <&clks IMXRT1050_CLK_PLL2_SYS>, + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, + <&clks IMXRT1050_CLK_PLL2_SYS>; + }; + + edma1: dma-controller@400e8000 { + #dma-cells = <2>; + compatible = "fsl,imx7ulp-edma"; + reg = <0x400e8000 0x4000>, + <0x400ec000 0x4000>; + dma-channels = <32>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; + clock-names = "dma", "dmamux0"; + clocks = <&clks IMXRT1050_CLK_DMA>, + <&clks IMXRT1050_CLK_DMA_MUX>; + }; + + usdhc1: mmc@402c0000 { + compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x402c0000 0x4000>; + interrupts = <110>; + clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, + <&clks IMXRT1050_CLK_OSC>, + <&clks IMXRT1050_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,wp-controller; + no-1-8-v; + max-frequency = <4000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + gpio1: gpio@401b8000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401b8000 0x4000>; + interrupts = <80>, <81>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@401bc000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401bc000 0x4000>; + interrupts = <82>, <83>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@401c0000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401c0000 0x4000>; + interrupts = <84>, <85>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@401c4000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401c4000 0x4000>; + interrupts = <86>, <87>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@400c0000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x400c0000 0x4000>; + interrupts = <88>, <89>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpt: timer@401ec000 { + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; + reg = <0x401ec000 0x4000>; + interrupts = <100>; + clocks = <&osc3M>; + clock-names = "per"; + }; + }; +}; diff --git a/arch/arm/boot/dts/imxrt1170-pinfunc.h b/arch/arm/boot/dts/imxrt1170-pinfunc.h new file mode 100644 index 000000000000..3b9fff2f08e1 --- /dev/null +++ b/arch/arm/boot/dts/imxrt1170-pinfunc.h @@ -0,0 +1,1561 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 + * Author(s): Jesse Taube <Mr.Bossman075@gmail.com> + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H + +#define IMX_PAD_SION 0x40000000 + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ + +#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 +#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 +#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0 +#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0 +#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x004 0x044 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x008 0x048 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x008 0x048 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0 +#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0 + +#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x00C 0x04C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x00C 0x04C 0x094 0x1 0x0 +#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0 +#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x00C 0x04C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0 +#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x010 0x050 0x0A0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0 +#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x010 0x050 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x014 0x054 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0 +#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0 +#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1 +#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0 +#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0 + +#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0 +#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1 +#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x018 0x058 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x018 0x058 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x018 0x058 0x0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x018 0x058 0x0 0x7 0x0 +#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x018 0x058 0x0 0x8 0x0 +#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x018 0x058 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x01C 0x05C 0x08C 0x0 0x0 +#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x01C 0x05C 0x0CC 0x2 0x0 +#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x01C 0x05C 0x0AC 0x3 0x1 +#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x01C 0x05C 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x01C 0x05C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x01C 0x05C 0x080 0x6 0x1 +#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x01C 0x05C 0x0 0x7 0x0 +#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x01C 0x05C 0x0 0x8 0x0 +#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x01C 0x05C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x020 0x060 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x020 0x060 0x0A8 0x0 0x1 +#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x020 0x060 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x020 0x060 0x0D4 0x2 0x0 +#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x020 0x060 0x0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x020 0x060 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x020 0x060 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x020 0x060 0x088 0x6 0x1 +#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x020 0x060 0x0 0x7 0x0 +#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x020 0x060 0x0 0x8 0x0 + +#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x024 0x064 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x024 0x064 0x0A4 0x0 0x1 +#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x024 0x064 0x080 0x1 0x2 +#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x024 0x064 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x024 0x064 0x0B4 0x3 0x1 +#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x024 0x064 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x024 0x064 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x024 0x064 0x084 0x6 0x1 +#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x024 0x064 0x0 0x7 0x0 + +#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x028 0x068 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x028 0x068 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x028 0x068 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x028 0x068 0x090 0x2 0x1 +#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x028 0x068 0x0B8 0x3 0x0 +#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x028 0x068 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x028 0x068 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x028 0x068 0x0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x028 0x068 0x0DC 0x7 0x1 +#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x028 0x068 0x0B0 0x8 0x2 + +#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x02C 0x06C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x02C 0x06C 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x02C 0x06C 0x08C 0x2 0x1 +#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x02C 0x06C 0x0BC 0x3 0x0 +#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x02C 0x06C 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x02C 0x06C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x02C 0x06C 0x0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x02C 0x06C 0x0 0x7 0x0 +#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x02C 0x06C 0x0AC 0x8 0x2 +#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x02C 0x06C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x030 0x070 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x030 0x070 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x030 0x070 0x0 0x1 0x0 +#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x030 0x070 0x0C0 0x3 0x0 +#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x030 0x070 0x0 0x4 0x0 +#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x030 0x070 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x030 0x070 0x0 0x6 0x0 +#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x030 0x070 0x0D8 0x7 0x1 +#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x030 0x070 0x098 0x8 0x1 + +#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x034 0x074 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x034 0x074 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x034 0x074 0x0B8 0x1 0x1 +#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x034 0x074 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x034 0x074 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x034 0x074 0x0D0 0x7 0x1 +#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x034 0x074 0x094 0x8 0x1 + +#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x038 0x078 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x038 0x078 0x0BC 0x1 0x1 +#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x038 0x078 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x038 0x078 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x038 0x078 0x0CC 0x7 0x1 +#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x038 0x078 0x0A0 0x8 0x1 +#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x038 0x078 0x0 0xA 0x0 + +#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x03C 0x07C 0x0 0xA 0x0 +#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x03C 0x07C 0x0 0x0 0x0 +#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x03C 0x07C 0x0C0 0x1 0x1 +#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x03C 0x07C 0x0 0x2 0x0 +#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x03C 0x07C 0x0 0x5 0x0 +#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x03C 0x07C 0x0D4 0x7 0x1 +#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x03C 0x07C 0x09C 0x8 0x1 + +#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000 0x40C94040 0x0 0x5 0x0 +#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000 0x40C94040 0x0C4 0x7 0x1 + +#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004 0x40C94044 0x0 0x0 0x0 +#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004 0x40C94044 0x0 0x5 0x0 + +#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008 0x40C94048 0x0 0x0 0x0 +#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008 0x40C94048 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400C 0x40C9404C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400C 0x40C9404C 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010 0x40C94050 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010 0x40C94050 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014 0x40C94054 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014 0x40C94054 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018 0x40C94058 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018 0x40C94058 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401C 0x40C9405C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401C 0x40C9405C 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020 0x40C94060 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020 0x40C94060 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024 0x40C94064 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024 0x40C94064 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028 0x40C94068 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028 0x40C94068 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402C 0x40C9406C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402C 0x40C9406C 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030 0x40C94070 0x0 0x0 0x0 +#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030 0x40C94070 0x0 0x5 0x0 + +#define IOMUXC_TEST_MODE_DIG 0x0 0x40C94034 0x0 0x0 0x0 + +#define IOMUXC_POR_B_DIG 0x0 0x40C94038 0x0 0x0 0x0 + +#define IOMUXC_ONOFF_DIG 0x0 0x40C9403C 0x0 0x0 0x0 + +#define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x010 0x254 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x010 0x254 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x010 0x254 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_00_FLEXIO1_D00 0x010 0x254 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 0x010 0x254 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 0x014 0x258 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 0x014 0x258 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B 0x014 0x258 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 0x014 0x258 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_01_FLEXIO1_D01 0x014 0x258 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 0x018 0x25C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A 0x018 0x25C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 0x018 0x25C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_02_FLEXIO1_D02 0x018 0x25C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 0x018 0x25C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 0x01C 0x260 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B 0x01C 0x260 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 0x01C 0x260 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_03_FLEXIO1_D03 0x01C 0x260 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 0x01C 0x260 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 0x020 0x264 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 0x020 0x264 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A 0x020 0x264 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 0x020 0x264 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_04_FLEXIO1_D04 0x020 0x264 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 0x024 0x268 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B 0x024 0x268 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 0x024 0x268 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_05_FLEXIO1_D05 0x024 0x268 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 0x024 0x268 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 0x028 0x26C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A 0x028 0x26C 0x518 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 0x028 0x26C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_06_FLEXIO1_D06 0x028 0x26C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 0x028 0x26C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 0x02C 0x270 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 0x02C 0x270 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B 0x02C 0x270 0x524 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 0x02C 0x270 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_07_FLEXIO1_D07 0x02C 0x270 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 0x030 0x274 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A 0x030 0x274 0x51C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 0x030 0x274 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_08_FLEXIO1_D08 0x030 0x274 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 0x030 0x274 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 0x034 0x278 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B 0x034 0x278 0x528 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 0x034 0x278 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 0x034 0x278 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_09_FLEXIO1_D09 0x034 0x278 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 0x034 0x278 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 0x038 0x27C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A 0x038 0x27C 0x520 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 0x038 0x27C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 0x038 0x27C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_10_FLEXIO1_D10 0x038 0x27C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 0x038 0x27C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 0x03C 0x280 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 0x03C 0x280 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B 0x03C 0x280 0x52C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 0x03C 0x280 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 0x03C 0x280 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_11_FLEXIO1_D11 0x03C 0x280 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 0x040 0x284 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_12_XBAR1_INOUT04 0x040 0x284 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 0x040 0x284 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 0x040 0x284 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_12_FLEXIO1_D12 0x040 0x284 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 0x040 0x284 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 0x044 0x288 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_13_XBAR1_INOUT05 0x044 0x288 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 0x044 0x288 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 0x044 0x288 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_13_FLEXIO1_D13 0x044 0x288 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 0x044 0x288 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 0x048 0x28C 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 0x048 0x28C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_14_XBAR1_INOUT06 0x048 0x28C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_14_GPT5_CLK 0x048 0x28C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 0x048 0x28C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_14_FLEXIO1_D14 0x048 0x28C 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 0x04C 0x290 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_15_XBAR1_INOUT07 0x04C 0x290 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 0x04C 0x290 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_15_FLEXIO1_D15 0x04C 0x290 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 0x04C 0x290 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 0x050 0x294 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_16_XBAR1_INOUT08 0x050 0x294 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 0x050 0x294 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_16_FLEXIO1_D16 0x050 0x294 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 0x050 0x294 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 0x054 0x298 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 0x054 0x298 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A 0x054 0x298 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_17_TMR1_TIMER0 0x054 0x298 0x63C 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 0x054 0x298 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_17_FLEXIO1_D17 0x054 0x298 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 0x058 0x29C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B 0x058 0x29C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_18_TMR2_TIMER0 0x058 0x29C 0x648 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 0x058 0x29C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_18_FLEXIO1_D18 0x058 0x29C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 0x058 0x29C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 0x05C 0x2A0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A 0x05C 0x2A0 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_19_TMR3_TIMER0 0x05C 0x2A0 0x654 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 0x05C 0x2A0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_19_FLEXIO1_D19 0x05C 0x2A0 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 0x05C 0x2A0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 0x060 0x2A4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B 0x060 0x2A4 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_20_TMR4_TIMER0 0x060 0x2A4 0x660 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 0x060 0x2A4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_20_FLEXIO1_D20 0x060 0x2A4 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 0x060 0x2A4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 0x064 0x2A8 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 0x064 0x2A8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A 0x064 0x2A8 0x53C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 0x064 0x2A8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_21_FLEXIO1_D21 0x064 0x2A8 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 0x068 0x2AC 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 0x068 0x2AC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B 0x068 0x2AC 0x54C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 0x068 0x2AC 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_22_FLEXIO1_D22 0x068 0x2AC 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 0x06C 0x2B0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A 0x06C 0x2B0 0x500 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 0x06C 0x2B0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_23_FLEXIO1_D23 0x06C 0x2B0 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 0x06C 0x2B0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 0x070 0x2B4 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_24_SEMC_CAS 0x070 0x2B4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B 0x070 0x2B4 0x50C 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 0x070 0x2B4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_24_FLEXIO1_D24 0x070 0x2B4 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 0x074 0x2B8 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_25_SEMC_RAS 0x074 0x2B8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A 0x074 0x2B8 0x504 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 0x074 0x2B8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_25_FLEXIO1_D25 0x074 0x2B8 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_26_SEMC_CLK 0x078 0x2BC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B 0x078 0x2BC 0x510 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 0x078 0x2BC 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_26_FLEXIO1_D26 0x078 0x2BC 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 0x078 0x2BC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 0x07C 0x2C0 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_27_SEMC_CKE 0x07C 0x2C0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A 0x07C 0x2C0 0x508 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 0x07C 0x2C0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_27_FLEXIO1_D27 0x07C 0x2C0 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 0x080 0x2C4 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_28_SEMC_WE 0x080 0x2C4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B 0x080 0x2C4 0x514 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 0x080 0x2C4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_28_FLEXIO1_D28 0x080 0x2C4 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 0x084 0x2C8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A 0x084 0x2C8 0x530 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 0x084 0x2C8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_29_FLEXIO1_D29 0x084 0x2C8 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 0x084 0x2C8 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 0x088 0x2CC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B 0x088 0x2CC 0x540 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 0x088 0x2CC 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_30_FLEXIO1_D30 0x088 0x2CC 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 0x088 0x2CC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 0x08C 0x2D0 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 0x08C 0x2D0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A 0x08C 0x2D0 0x534 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 0x08C 0x2D0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_31_FLEXIO1_D31 0x08C 0x2D0 0x0 0x8 0x0 + +#define IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 0x090 0x2D4 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 0x090 0x2D4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B 0x090 0x2D4 0x544 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 0x090 0x2D4 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 0x094 0x2D8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A 0x094 0x2D8 0x538 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 0x094 0x2D8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 0x094 0x2D8 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 0x098 0x2DC 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 0x098 0x2DC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B 0x098 0x2DC 0x548 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 0x098 0x2DC 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 0x09C 0x2E0 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 0x09C 0x2E0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_35_XBAR1_INOUT09 0x09C 0x2E0 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 0x09C 0x2E0 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 0x0A0 0x2E4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_36_XBAR1_INOUT10 0x0A0 0x2E4 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 0x0A0 0x2E4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 0x0A0 0x2E4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 0x0A4 0x2E8 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 0x0A4 0x2E8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_37_XBAR1_INOUT11 0x0A4 0x2E8 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 0x0A4 0x2E8 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 0x0A8 0x2EC 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 0x0A8 0x2EC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A 0x0A8 0x2EC 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_38_TMR1_TIMER1 0x0A8 0x2EC 0x640 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 0x0A8 0x2EC 0x0 0x5 0x0 + +#define IOMUXC_GPIO_EMC_B1_39_SEMC_DQS 0x0AC 0x2F0 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B 0x0AC 0x2F0 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_39_TMR2_TIMER1 0x0AC 0x2F0 0x64C 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 0x0AC 0x2F0 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 0x0AC 0x2F0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_40_SEMC_RDY 0x0B0 0x2F4 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_40_XBAR1_INOUT12 0x0B0 0x2F4 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT 0x0B0 0x2F4 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD 0x0B0 0x2F4 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 0x0B0 0x2F4 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC 0x0B0 0x2F4 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 0x0B0 0x2F4 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 0x0B0 0x2F4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 0x0B4 0x2F8 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 0x0B4 0x2F8 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B1_41_XBAR1_INOUT13 0x0B4 0x2F8 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B1_41_MQS_LEFT 0x0B4 0x2F8 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD 0x0B4 0x2F8 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 0x0B4 0x2F8 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 0x0B4 0x2F8 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO 0x0B4 0x2F8 0x4C8 0x7 0x0 +#define IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 0x0B4 0x2F8 0x0 0x9 0x0 + +#define IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 0x0B8 0x2FC 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M 0x0B8 0x2FC 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_00_TMR3_TIMER1 0x0B8 0x2FC 0x658 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B 0x0B8 0x2FC 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 0x0B8 0x2FC 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 0x0B8 0x2FC 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_00_XBAR1_INOUT20 0x0B8 0x2FC 0x6D8 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_00_ENET_QOS_1588_EVENT1_OUT 0x0B8 0x2FC 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK 0x0B8 0x2FC 0x5D0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL 0x0B8 0x2FC 0x5B4 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 0x0B8 0x2FC 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A 0x0B8 0x2FC 0x530 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 0x0BC 0x300 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B 0x0BC 0x300 0x6D0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_01_TMR4_TIMER1 0x0BC 0x300 0x664 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B 0x0BC 0x300 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 0x0BC 0x300 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 0x0BC 0x300 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_01_XBAR1_INOUT21 0x0BC 0x300 0x6DC 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_01_ENET_QOS_1588_EVENT1_IN 0x0BC 0x300 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 0x0BC 0x300 0x5CC 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA 0x0BC 0x300 0x5B8 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 0x0BC 0x300 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B 0x0BC 0x300 0x540 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 0x0C0 0x304 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_02_USDHC2_WP 0x0C0 0x304 0x6D4 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 0x0C0 0x304 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 0x0C0 0x304 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 0x0C0 0x304 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_02_XBAR1_INOUT22 0x0C0 0x304 0x6E0 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_02_ENET_QOS_1588_EVENT1_AUX_IN 0x0C0 0x304 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_02_LPSPI1_SOUT 0x0C0 0x304 0x5D8 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 0x0C0 0x304 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A 0x0C0 0x304 0x534 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 0x0C4 0x308 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT 0x0C4 0x308 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 0x0C4 0x308 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 0x0C4 0x308 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 0x0C4 0x308 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_03_XBAR1_INOUT23 0x0C4 0x308 0x6E4 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_03_ENET_1G_TX_DATA03 0x0C4 0x308 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_03_LPSPI1_SIN 0x0C4 0x308 0x5D4 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 0x0C4 0x308 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B 0x0C4 0x308 0x544 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 0x0C8 0x30C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B 0x0C8 0x30C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK 0x0C8 0x30C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 0x0C8 0x30C 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 0x0C8 0x30C 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 0x0C8 0x30C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_04_XBAR1_INOUT24 0x0C8 0x30C 0x6E8 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_04_ENET_1G_TX_DATA02 0x0C8 0x30C 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK 0x0C8 0x30C 0x600 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 0x0C8 0x30C 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A 0x0C8 0x30C 0x538 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 0x0CC 0x310 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_05_GPT3_CLK 0x0CC 0x310 0x598 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC 0x0CC 0x310 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 0x0CC 0x310 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 0x0CC 0x310 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 0x0CC 0x310 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_05_XBAR1_INOUT25 0x0CC 0x310 0x6EC 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK 0x0CC 0x310 0x4CC 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 0x0CC 0x310 0x5F0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER0 0x0CC 0x310 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 0x0CC 0x310 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B 0x0CC 0x310 0x548 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 0x0D0 0x314 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 0x0D0 0x314 0x590 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 0x0D0 0x314 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK 0x0D0 0x314 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A 0x0D0 0x314 0x53C 0xB 0x1 +#define IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 0x0D0 0x314 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 0x0D0 0x314 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 0x0D0 0x314 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_06_XBAR1_INOUT26 0x0D0 0x314 0x6F0 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER 0x0D0 0x314 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_06_LPSPI3_SOUT 0x0D0 0x314 0x608 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER1 0x0D0 0x314 0x0 0x9 0x0 + +#define IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 0x0D4 0x318 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 0x0D4 0x318 0x594 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA 0x0D4 0x318 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 0x0D4 0x318 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS 0x0D4 0x318 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 0x0D4 0x318 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_07_XBAR1_INOUT27 0x0D4 0x318 0x6F4 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_07_ENET_1G_RX_DATA03 0x0D4 0x318 0x4DC 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_07_LPSPI3_SIN 0x0D4 0x318 0x604 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER2 0x0D4 0x318 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 0x0D4 0x318 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B 0x0D4 0x318 0x54C 0xB 0x1 + +#define IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 0x0D8 0x31C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 0x0D8 0x31C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA 0x0D8 0x31C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 0x0D8 0x31C 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B 0x0D8 0x31C 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 0x0D8 0x31C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_08_XBAR1_INOUT28 0x0D8 0x31C 0x6F8 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_08_ENET_1G_RX_DATA02 0x0D8 0x31C 0x4D8 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 0x0D8 0x31C 0x5F4 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER3 0x0D8 0x31C 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 0x0D8 0x31C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 0x0DC 0x320 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 0x0DC 0x320 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 0x0DC 0x320 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK 0x0DC 0x320 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 0x0DC 0x320 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK 0x0DC 0x320 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 0x0DC 0x320 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_09_XBAR1_INOUT29 0x0DC 0x320 0x6FC 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS 0x0DC 0x320 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 0x0DC 0x320 0x5F8 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_09_TMR1_TIMER0 0x0DC 0x320 0x63C 0x9 0x1 + +#define IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 0x0E0 0x324 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 0x0E0 0x324 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 0x0E0 0x324 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC 0x0E0 0x324 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD 0x0E0 0x324 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK 0x0E0 0x324 0x58C 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 0x0E0 0x324 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_10_XBAR1_INOUT30 0x0E0 0x324 0x700 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL 0x0E0 0x324 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 0x0E0 0x324 0x5FC 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_10_TMR1_TIMER1 0x0E0 0x324 0x640 0x9 0x1 + +#define IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 0x0E4 0x328 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_11_SPDIF_IN 0x0E4 0x328 0x6B4 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_11_ENET_1G_TX_DATA00 0x0E4 0x328 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC 0x0E4 0x328 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B 0x0E4 0x328 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 0x0E4 0x328 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_11_XBAR1_INOUT31 0x0E4 0x328 0x704 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_11_EMVSIM1_IO 0x0E4 0x328 0x69C 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_11_TMR1_TIMER2 0x0E4 0x328 0x644 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 0x0E4 0x328 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 0x0E8 0x32C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT 0x0E8 0x32C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_12_ENET_1G_TX_DATA01 0x0E8 0x32C 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK 0x0E8 0x32C 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS 0x0E8 0x32C 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 0x0E8 0x32C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_12_XBAR1_INOUT32 0x0E8 0x32C 0x708 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_12_EMVSIM1_CLK 0x0E8 0x32C 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_12_TMR1_TIMER3 0x0E8 0x32C 0x0 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 0x0E8 0x32C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 0x0EC 0x330 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 0x0EC 0x330 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN 0x0EC 0x330 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA 0x0EC 0x330 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 0x0EC 0x330 0x57C 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 0x0EC 0x330 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_13_XBAR1_INOUT33 0x0EC 0x330 0x70C 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_13_EMVSIM1_RST 0x0EC 0x330 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_13_TMR2_TIMER0 0x0EC 0x330 0x648 0x9 0x1 + +#define IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 0x0F0 0x334 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO 0x0F0 0x334 0x4E8 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA 0x0F0 0x334 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 0x0F0 0x334 0x580 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 0x0F0 0x334 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_14_XBAR1_INOUT34 0x0F0 0x334 0x710 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_14_SFA_ipp_do_atx_clk_under_test 0x0F0 0x334 0x0 0x7 0x0 +#define IOMUXC_GPIO_EMC_B2_14_EMVSIM1_SVEN 0x0F0 0x334 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_14_TMR2_TIMER1 0x0F0 0x334 0x64C 0x9 0x1 +#define IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 0x0F0 0x334 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 0x0F4 0x338 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_15_ENET_1G_RX_DATA00 0x0F4 0x338 0x4D0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK 0x0F4 0x338 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 0x0F4 0x338 0x584 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 0x0F4 0x338 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_15_XBAR1_INOUT35 0x0F4 0x338 0x714 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_15_EMVSIM1_PD 0x0F4 0x338 0x6A0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_15_TMR2_TIMER2 0x0F4 0x338 0x650 0x9 0x0 +#define IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 0x0F4 0x338 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 0x0F8 0x33C 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 0x0F8 0x33C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_16_XBAR1_INOUT14 0x0F8 0x33C 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_16_ENET_1G_RX_DATA01 0x0F8 0x33C 0x4D4 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC 0x0F8 0x33C 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 0x0F8 0x33C 0x588 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 0x0F8 0x33C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_16_EMVSIM1_POWER_FAIL 0x0F8 0x33C 0x6A4 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_16_TMR2_TIMER3 0x0F8 0x33C 0x0 0x9 0x0 + +#define IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 0x0FC 0x340 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_17_XBAR1_INOUT15 0x0FC 0x340 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN 0x0FC 0x340 0x4E0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK 0x0FC 0x340 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 0x0FC 0x340 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 0x0FC 0x340 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_17_WDOG1_ANY 0x0FC 0x340 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_17_TMR3_TIMER0 0x0FC 0x340 0x654 0x9 0x1 +#define IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 0x0FC 0x340 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 0x100 0x344 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_18_XBAR1_INOUT16 0x100 0x344 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER 0x100 0x344 0x4E4 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_18_EWM_OUT_B 0x100 0x344 0x0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 0x100 0x344 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 0x100 0x344 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS 0x100 0x344 0x550 0x6 0x0 +#define IOMUXC_GPIO_EMC_B2_18_WDOG1_B 0x100 0x344 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_18_TMR3_TIMER1 0x100 0x344 0x658 0x9 0x1 +#define IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 0x100 0x344 0x0 0xA 0x0 + +#define IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 0x104 0x348 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 0x104 0x348 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_19_ENET_MDC 0x104 0x348 0x0 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC 0x104 0x348 0x0 0x2 0x0 +#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x104 0x348 0x4C4 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x104 0x348 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x104 0x348 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC 0x104 0x348 0x0 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_19_TMR3_TIMER2 0x104 0x348 0x65C 0x9 0x0 + +#define IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 0x108 0x34C 0x0 0xA 0x0 +#define IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 0x108 0x34C 0x0 0x0 0x0 +#define IOMUXC_GPIO_EMC_B2_20_ENET_MDIO 0x108 0x34C 0x4AC 0x1 0x0 +#define IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO 0x108 0x34C 0x4C8 0x2 0x1 +#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x108 0x34C 0x4A0 0x3 0x0 +#define IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x108 0x34C 0x0 0x4 0x0 +#define IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x108 0x34C 0x0 0x5 0x0 +#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x108 0x34C 0x4EC 0x8 0x0 +#define IOMUXC_GPIO_EMC_B2_20_TMR3_TIMER3 0x108 0x34C 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_00_GPIO8_IO31 0x10C 0x350 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_00_EMVSIM1_IO 0x10C 0x350 0x69C 0x0 0x1 +#define IOMUXC_GPIO_AD_00_FLEXCAN2_TX 0x10C 0x350 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN 0x10C 0x350 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 0x10C 0x350 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A 0x10C 0x350 0x500 0x4 0x1 +#define IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 0x10C 0x350 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_00_LPUART7_TXD 0x10C 0x350 0x630 0x6 0x0 +#define IOMUXC_GPIO_AD_00_FLEXIO2_D00 0x10C 0x350 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B 0x10C 0x350 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_01_GPIO9_IO00 0x110 0x354 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_01_EMVSIM1_CLK 0x110 0x354 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_01_FLEXCAN2_RX 0x110 0x354 0x49C 0x1 0x0 +#define IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT 0x110 0x354 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 0x110 0x354 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B 0x110 0x354 0x50C 0x4 0x1 +#define IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 0x110 0x354 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_01_LPUART7_RXD 0x110 0x354 0x62C 0x6 0x0 +#define IOMUXC_GPIO_AD_01_FLEXIO2_D01 0x110 0x354 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B 0x110 0x354 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_02_GPIO9_IO01 0x114 0x358 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_02_EMVSIM1_RST 0x114 0x358 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_02_LPUART7_CTS_B 0x114 0x358 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN 0x114 0x358 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_02_GPT2_COMPARE1 0x114 0x358 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A 0x114 0x358 0x504 0x4 0x1 +#define IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 0x114 0x358 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_02_LPUART8_TXD 0x114 0x358 0x638 0x6 0x0 +#define IOMUXC_GPIO_AD_02_FLEXIO2_D02 0x114 0x358 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 0x114 0x358 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_03_GPIO9_IO02 0x118 0x35C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_03_EMVSIM1_SVEN 0x118 0x35C 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_03_LPUART7_RTS_B 0x118 0x35C 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT 0x118 0x35C 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_03_GPT2_COMPARE2 0x118 0x35C 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B 0x118 0x35C 0x510 0x4 0x1 +#define IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 0x118 0x35C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_03_LPUART8_RXD 0x118 0x35C 0x634 0x6 0x0 +#define IOMUXC_GPIO_AD_03_FLEXIO2_D03 0x118 0x35C 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 0x118 0x35C 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_04_EMVSIM1_PD 0x11C 0x360 0x6A0 0x0 0x1 +#define IOMUXC_GPIO_AD_04_LPUART8_CTS_B 0x11C 0x360 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN 0x11C 0x360 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_04_GPT2_COMPARE3 0x11C 0x360 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A 0x11C 0x360 0x508 0x4 0x1 +#define IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 0x11C 0x360 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_04_WDOG1_B 0x11C 0x360 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_04_FLEXIO2_D04 0x11C 0x360 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_04_TMR4_TIMER0 0x11C 0x360 0x660 0x9 0x1 +#define IOMUXC_GPIO_AD_04_GPIO9_IO03 0x11C 0x360 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_05_EMVSIM1_POWER_FAIL 0x120 0x364 0x6A4 0x0 0x1 +#define IOMUXC_GPIO_AD_05_LPUART8_RTS_B 0x120 0x364 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT 0x120 0x364 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_05_GPT2_CLK 0x120 0x364 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B 0x120 0x364 0x514 0x4 0x1 +#define IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 0x120 0x364 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_05_WDOG2_B 0x120 0x364 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_05_FLEXIO2_D05 0x120 0x364 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_05_TMR4_TIMER1 0x120 0x364 0x664 0x9 0x1 +#define IOMUXC_GPIO_AD_05_GPIO9_IO04 0x120 0x364 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_06_USB_OTG2_OC 0x124 0x368 0x6B8 0x0 0x0 +#define IOMUXC_GPIO_AD_06_FLEXCAN1_TX 0x124 0x368 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_06_EMVSIM2_IO 0x124 0x368 0x6A8 0x2 0x0 +#define IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 0x124 0x368 0x590 0x3 0x1 +#define IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 0x124 0x368 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 0x124 0x368 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN 0x124 0x368 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_06_FLEXIO2_D06 0x124 0x368 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_06_TMR4_TIMER2 0x124 0x368 0x668 0x9 0x0 +#define IOMUXC_GPIO_AD_06_GPIO9_IO05 0x124 0x368 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X 0x124 0x368 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_07_USB_OTG2_PWR 0x128 0x36C 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_07_FLEXCAN1_RX 0x128 0x36C 0x498 0x1 0x0 +#define IOMUXC_GPIO_AD_07_EMVSIM2_CLK 0x128 0x36C 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 0x128 0x36C 0x594 0x3 0x1 +#define IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 0x128 0x36C 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 0x128 0x36C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT 0x128 0x36C 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_07_FLEXIO2_D07 0x128 0x36C 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_07_TMR4_TIMER3 0x128 0x36C 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_07_GPIO9_IO06 0x128 0x36C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X 0x128 0x36C 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID 0x12C 0x370 0x6C4 0x0 0x0 +#define IOMUXC_GPIO_AD_08_LPI2C1_SCL 0x12C 0x370 0x5AC 0x1 0x0 +#define IOMUXC_GPIO_AD_08_EMVSIM2_RST 0x12C 0x370 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_08_GPT3_COMPARE1 0x12C 0x370 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 0x12C 0x370 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 0x12C 0x370 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN 0x12C 0x370 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_08_FLEXIO2_D08 0x12C 0x370 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_08_GPIO9_IO07 0x12C 0x370 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X 0x12C 0x370 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0x130 0x374 0x6C0 0x0 0x0 +#define IOMUXC_GPIO_AD_09_LPI2C1_SDA 0x130 0x374 0x5B0 0x1 0x0 +#define IOMUXC_GPIO_AD_09_EMVSIM2_SVEN 0x130 0x374 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_09_GPT3_COMPARE2 0x130 0x374 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 0x130 0x374 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 0x130 0x374 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT 0x130 0x374 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_09_FLEXIO2_D09 0x130 0x374 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_09_GPIO9_IO08 0x130 0x374 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X 0x130 0x374 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_10_USB_OTG1_PWR 0x134 0x378 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_10_LPI2C1_SCLS 0x134 0x378 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_10_EMVSIM2_PD 0x134 0x378 0x6AC 0x2 0x0 +#define IOMUXC_GPIO_AD_10_GPT3_COMPARE3 0x134 0x378 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 0x134 0x378 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 0x134 0x378 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN 0x134 0x378 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_10_FLEXIO2_D10 0x134 0x378 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_10_GPIO9_IO09 0x134 0x378 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X 0x134 0x378 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_11_USB_OTG1_OC 0x138 0x37C 0x6BC 0x0 0x0 +#define IOMUXC_GPIO_AD_11_LPI2C1_SDAS 0x138 0x37C 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_11_EMVSIM2_POWER_FAIL 0x138 0x37C 0x6B0 0x2 0x0 +#define IOMUXC_GPIO_AD_11_GPT3_CLK 0x138 0x37C 0x598 0x3 0x1 +#define IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 0x138 0x37C 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 0x138 0x37C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT 0x138 0x37C 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_11_FLEXIO2_D11 0x138 0x37C 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_11_GPIO9_IO10 0x138 0x37C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X 0x138 0x37C 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_12_SPDIF_LOCK 0x13C 0x380 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_12_LPI2C1_HREQ 0x13C 0x380 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 0x13C 0x380 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 0x13C 0x380 0x570 0x3 0x0 +#define IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK 0x13C 0x380 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 0x13C 0x380 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_12_ENET_TX_DATA03 0x13C 0x380 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_12_FLEXIO2_D12 0x13C 0x380 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_12_EWM_OUT_B 0x13C 0x380 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_12_GPIO9_IO11 0x13C 0x380 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X 0x13C 0x380 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_13_SPDIF_SR_CLK 0x140 0x384 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_13_PIT1_TRIGGER0 0x140 0x384 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 0x140 0x384 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 0x140 0x384 0x56C 0x3 0x0 +#define IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK 0x140 0x384 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 0x140 0x384 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_13_ENET_TX_DATA02 0x140 0x384 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_13_FLEXIO2_D13 0x140 0x384 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_13_REF_CLK_32K 0x140 0x384 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_13_GPIO9_IO12 0x140 0x384 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X 0x140 0x384 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK 0x144 0x388 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_14_REF_CLK_24M 0x144 0x388 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_14_GPT1_COMPARE1 0x144 0x388 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 0x144 0x388 0x568 0x3 0x0 +#define IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC 0x144 0x388 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 0x144 0x388 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_14_ENET_RX_CLK 0x144 0x388 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_14_FLEXIO2_D14 0x144 0x388 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M 0x144 0x388 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_14_GPIO9_IO13 0x144 0x388 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X 0x144 0x388 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_15_GPIO9_IO14 0x148 0x38C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X 0x148 0x38C 0x0 0xB 0x0 +#define IOMUXC_GPIO_AD_15_SPDIF_IN 0x148 0x38C 0x6B4 0x0 0x1 +#define IOMUXC_GPIO_AD_15_LPUART10_TXD 0x148 0x38C 0x628 0x1 0x0 +#define IOMUXC_GPIO_AD_15_GPT1_COMPARE2 0x148 0x38C 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 0x148 0x38C 0x564 0x3 0x0 +#define IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC 0x148 0x38C 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 0x148 0x38C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_15_ENET_TX_ER 0x148 0x38C 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_15_FLEXIO2_D15 0x148 0x38C 0x0 0x8 0x0 + +#define IOMUXC_GPIO_AD_16_SPDIF_OUT 0x14C 0x390 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_16_LPUART10_RXD 0x14C 0x390 0x624 0x1 0x0 +#define IOMUXC_GPIO_AD_16_GPT1_COMPARE3 0x14C 0x390 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK 0x14C 0x390 0x578 0x3 0x0 +#define IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 0x14C 0x390 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 0x14C 0x390 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_16_ENET_RX_DATA03 0x14C 0x390 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_16_FLEXIO2_D16 0x14C 0x390 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_16_ENET_1G_MDC 0x14C 0x390 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_16_GPIO9_IO15 0x14C 0x390 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X 0x14C 0x390 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_17_SAI1_MCLK 0x150 0x394 0x66C 0x0 0x0 +#define IOMUXC_GPIO_AD_17_ACMP1_OUT 0x150 0x394 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_17_GPT1_CLK 0x150 0x394 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS 0x150 0x394 0x550 0x3 0x1 +#define IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 0x150 0x394 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 0x150 0x394 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_17_ENET_RX_DATA02 0x150 0x394 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_17_FLEXIO2_D17 0x150 0x394 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_17_ENET_1G_MDIO 0x150 0x394 0x4C8 0x9 0x2 +#define IOMUXC_GPIO_AD_17_GPIO9_IO16 0x150 0x394 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X 0x150 0x394 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_18_GPIO9_IO17 0x154 0x398 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X 0x154 0x398 0x0 0xB 0x0 +#define IOMUXC_GPIO_AD_18_SAI1_RX_SYNC 0x154 0x398 0x678 0x0 0x0 +#define IOMUXC_GPIO_AD_18_ACMP2_OUT 0x154 0x398 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_18_LPSPI1_PCS1 0x154 0x398 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B 0x154 0x398 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 0x154 0x398 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 0x154 0x398 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_18_ENET_CRS 0x154 0x398 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_18_FLEXIO2_D18 0x154 0x398 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_18_LPI2C2_SCL 0x154 0x398 0x5B4 0x9 0x1 + +#define IOMUXC_GPIO_AD_19_SAI1_RX_BCLK 0x158 0x39C 0x670 0x0 0x0 +#define IOMUXC_GPIO_AD_19_ACMP3_OUT 0x158 0x39C 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_19_LPSPI1_PCS2 0x158 0x39C 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK 0x158 0x39C 0x574 0x3 0x0 +#define IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 0x158 0x39C 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 0x158 0x39C 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_19_ENET_COL 0x158 0x39C 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_19_FLEXIO2_D19 0x158 0x39C 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_19_LPI2C2_SDA 0x158 0x39C 0x5B8 0x9 0x1 +#define IOMUXC_GPIO_AD_19_GPIO9_IO18 0x158 0x39C 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X 0x158 0x39C 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 0x15C 0x3A0 0x674 0x0 0x0 +#define IOMUXC_GPIO_AD_20_ACMP4_OUT 0x15C 0x3A0 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_20_LPSPI1_PCS3 0x15C 0x3A0 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 0x15C 0x3A0 0x554 0x3 0x0 +#define IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 0x15C 0x3A0 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 0x15C 0x3A0 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_20_KPP_ROW07 0x15C 0x3A0 0x5A8 0x6 0x0 +#define IOMUXC_GPIO_AD_20_FLEXIO2_D20 0x15C 0x3A0 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_20_ENET_QOS_1588_EVENT2_OUT 0x15C 0x3A0 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_20_GPIO9_IO19 0x15C 0x3A0 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X 0x15C 0x3A0 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 0x160 0x3A4 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_21_LPSPI2_PCS1 0x160 0x3A4 0x5E0 0x2 0x0 +#define IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 0x160 0x3A4 0x558 0x3 0x0 +#define IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 0x160 0x3A4 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 0x160 0x3A4 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_21_KPP_COL07 0x160 0x3A4 0x5A0 0x6 0x0 +#define IOMUXC_GPIO_AD_21_FLEXIO2_D21 0x160 0x3A4 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_21_ENET_QOS_1588_EVENT2_IN 0x160 0x3A4 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_21_GPIO9_IO20 0x160 0x3A4 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X 0x160 0x3A4 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_22_GPIO9_IO21 0x164 0x3A8 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_22_SAI1_TX_BCLK 0x164 0x3A8 0x67C 0x0 0x0 +#define IOMUXC_GPIO_AD_22_LPSPI2_PCS2 0x164 0x3A8 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 0x164 0x3A8 0x55C 0x3 0x0 +#define IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 0x164 0x3A8 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 0x164 0x3A8 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_22_KPP_ROW06 0x164 0x3A8 0x5A4 0x6 0x0 +#define IOMUXC_GPIO_AD_22_FLEXIO2_D22 0x164 0x3A8 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_22_ENET_QOS_1588_EVENT3_OUT 0x164 0x3A8 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_23_SAI1_TX_SYNC 0x168 0x3AC 0x680 0x0 0x0 +#define IOMUXC_GPIO_AD_23_LPSPI2_PCS3 0x168 0x3AC 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 0x168 0x3AC 0x560 0x3 0x0 +#define IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 0x168 0x3AC 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 0x168 0x3AC 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_23_KPP_COL06 0x168 0x3AC 0x59C 0x6 0x0 +#define IOMUXC_GPIO_AD_23_FLEXIO2_D23 0x168 0x3AC 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_23_ENET_QOS_1588_EVENT3_IN 0x168 0x3AC 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_23_GPIO9_IO22 0x168 0x3AC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_24_LPUART1_TXD 0x16C 0x3B0 0x620 0x0 0x0 +#define IOMUXC_GPIO_AD_24_LPSPI2_SCK 0x16C 0x3B0 0x5E4 0x1 0x0 +#define IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 0x16C 0x3B0 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_24_ENET_RX_EN 0x16C 0x3B0 0x4B8 0x3 0x0 +#define IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A 0x16C 0x3B0 0x518 0x4 0x1 +#define IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 0x16C 0x3B0 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_24_KPP_ROW05 0x16C 0x3B0 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_24_FLEXIO2_D24 0x16C 0x3B0 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_24_LPI2C4_SCL 0x16C 0x3B0 0x5C4 0x9 0x0 +#define IOMUXC_GPIO_AD_24_GPIO9_IO23 0x16C 0x3B0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_25_GPIO9_IO24 0x170 0x3B4 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_25_LPUART1_RXD 0x170 0x3B4 0x61C 0x0 0x0 +#define IOMUXC_GPIO_AD_25_LPSPI2_PCS0 0x170 0x3B4 0x5DC 0x1 0x0 +#define IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 0x170 0x3B4 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_25_ENET_RX_ER 0x170 0x3B4 0x4BC 0x3 0x0 +#define IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B 0x170 0x3B4 0x524 0x4 0x1 +#define IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 0x170 0x3B4 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_25_KPP_COL05 0x170 0x3B4 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_25_FLEXIO2_D25 0x170 0x3B4 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_25_LPI2C4_SDA 0x170 0x3B4 0x5C8 0x9 0x0 + +#define IOMUXC_GPIO_AD_26_LPUART1_CTS_B 0x174 0x3B8 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_26_LPSPI2_SOUT 0x174 0x3B8 0x5EC 0x1 0x0 +#define IOMUXC_GPIO_AD_26_SEMC_CSX01 0x174 0x3B8 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_26_ENET_RX_DATA00 0x174 0x3B8 0x4B0 0x3 0x0 +#define IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A 0x174 0x3B8 0x51C 0x4 0x1 +#define IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 0x174 0x3B8 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_26_KPP_ROW04 0x174 0x3B8 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_26_FLEXIO2_D26 0x174 0x3B8 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_26_ENET_QOS_MDC 0x174 0x3B8 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_26_GPIO9_IO25 0x174 0x3B8 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_26_USDHC2_CD_B 0x174 0x3B8 0x6D0 0xB 0x1 + +#define IOMUXC_GPIO_AD_27_LPUART1_RTS_B 0x178 0x3BC 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_27_LPSPI2_SIN 0x178 0x3BC 0x5E8 0x1 0x0 +#define IOMUXC_GPIO_AD_27_SEMC_CSX02 0x178 0x3BC 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_27_ENET_RX_DATA01 0x178 0x3BC 0x4B4 0x3 0x0 +#define IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B 0x178 0x3BC 0x528 0x4 0x1 +#define IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 0x178 0x3BC 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_27_KPP_COL04 0x178 0x3BC 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_27_FLEXIO2_D27 0x178 0x3BC 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_27_ENET_QOS_MDIO 0x178 0x3BC 0x4EC 0x9 0x1 +#define IOMUXC_GPIO_AD_27_GPIO9_IO26 0x178 0x3BC 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_27_USDHC2_WP 0x178 0x3BC 0x6D4 0xB 0x1 + +#define IOMUXC_GPIO_AD_28_GPIO9_IO27 0x17C 0x3C0 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_28_USDHC2_VSELECT 0x17C 0x3C0 0x0 0xB 0x0 +#define IOMUXC_GPIO_AD_28_LPSPI1_SCK 0x17C 0x3C0 0x5D0 0x0 0x1 +#define IOMUXC_GPIO_AD_28_LPUART5_TXD 0x17C 0x3C0 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_28_SEMC_CSX03 0x17C 0x3C0 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_28_ENET_TX_EN 0x17C 0x3C0 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A 0x17C 0x3C0 0x520 0x4 0x1 +#define IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 0x17C 0x3C0 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_28_KPP_ROW03 0x17C 0x3C0 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_28_FLEXIO2_D28 0x17C 0x3C0 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 0x17C 0x3C0 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_29_LPSPI1_PCS0 0x180 0x3C4 0x5CC 0x0 0x1 +#define IOMUXC_GPIO_AD_29_LPUART5_RXD 0x180 0x3C4 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_29_ENET_REF_CLK 0x180 0x3C4 0x4A8 0x2 0x0 +#define IOMUXC_GPIO_AD_29_ENET_TX_CLK 0x180 0x3C4 0x4C0 0x3 0x0 +#define IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B 0x180 0x3C4 0x52C 0x4 0x1 +#define IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 0x180 0x3C4 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_29_KPP_COL03 0x180 0x3C4 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_29_FLEXIO2_D29 0x180 0x3C4 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 0x180 0x3C4 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_29_GPIO9_IO28 0x180 0x3C4 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_29_USDHC2_RESET_B 0x180 0x3C4 0x0 0xB 0x0 + +#define IOMUXC_GPIO_AD_30_LPSPI1_SOUT 0x184 0x3C8 0x5D8 0x0 0x1 +#define IOMUXC_GPIO_AD_30_USB_OTG2_OC 0x184 0x3C8 0x6B8 0x1 0x1 +#define IOMUXC_GPIO_AD_30_FLEXCAN2_TX 0x184 0x3C8 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_30_ENET_TX_DATA00 0x184 0x3C8 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_30_LPUART3_TXD 0x184 0x3C8 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 0x184 0x3C8 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_30_KPP_ROW02 0x184 0x3C8 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_30_FLEXIO2_D30 0x184 0x3C8 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB 0x184 0x3C8 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_30_GPIO9_IO29 0x184 0x3C8 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_31_LPSPI1_SIN 0x188 0x3CC 0x5D4 0x0 0x1 +#define IOMUXC_GPIO_AD_31_USB_OTG2_PWR 0x188 0x3CC 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_31_FLEXCAN2_RX 0x188 0x3CC 0x49C 0x2 0x1 +#define IOMUXC_GPIO_AD_31_ENET_TX_DATA01 0x188 0x3CC 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_31_LPUART3_RXD 0x188 0x3CC 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 0x188 0x3CC 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_31_KPP_COL02 0x188 0x3CC 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_31_FLEXIO2_D31 0x188 0x3CC 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB 0x188 0x3CC 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_31_GPIO9_IO30 0x188 0x3CC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_32_GPIO9_IO31 0x18C 0x3D0 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_32_LPI2C1_SCL 0x18C 0x3D0 0x5AC 0x0 0x1 +#define IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID 0x18C 0x3D0 0x6C4 0x1 0x1 +#define IOMUXC_GPIO_AD_32_PGMC_PMIC_RDY 0x18C 0x3D0 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_32_ENET_MDC 0x18C 0x3D0 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_32_USDHC1_CD_B 0x18C 0x3D0 0x6C8 0x4 0x0 +#define IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 0x18C 0x3D0 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_32_KPP_ROW01 0x18C 0x3D0 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_32_LPUART10_TXD 0x18C 0x3D0 0x628 0x8 0x1 +#define IOMUXC_GPIO_AD_32_ENET_1G_MDC 0x18C 0x3D0 0x0 0x9 0x0 + +#define IOMUXC_GPIO_AD_33_LPI2C1_SDA 0x190 0x3D4 0x5B0 0x0 0x1 +#define IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID 0x190 0x3D4 0x6C0 0x1 0x1 +#define IOMUXC_GPIO_AD_33_XBAR1_INOUT17 0x190 0x3D4 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_33_ENET_MDIO 0x190 0x3D4 0x4AC 0x3 0x1 +#define IOMUXC_GPIO_AD_33_USDHC1_WP 0x190 0x3D4 0x6CC 0x4 0x0 +#define IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 0x190 0x3D4 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_33_KPP_COL01 0x190 0x3D4 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_33_LPUART10_RXD 0x190 0x3D4 0x624 0x8 0x1 +#define IOMUXC_GPIO_AD_33_ENET_1G_MDIO 0x190 0x3D4 0x4C8 0x9 0x3 +#define IOMUXC_GPIO_AD_33_GPIO10_IO00 0x190 0x3D4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN 0x194 0x3D8 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_34_USB_OTG1_PWR 0x194 0x3D8 0x0 0x1 0x0 +#define IOMUXC_GPIO_AD_34_XBAR1_INOUT18 0x194 0x3D8 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN 0x194 0x3D8 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_34_USDHC1_VSELECT 0x194 0x3D8 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 0x194 0x3D8 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_34_KPP_ROW00 0x194 0x3D8 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_34_LPUART10_CTS_B 0x194 0x3D8 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_34_WDOG1_ANY 0x194 0x3D8 0x0 0x9 0x0 +#define IOMUXC_GPIO_AD_34_GPIO10_IO01 0x194 0x3D8 0x0 0xA 0x0 + +#define IOMUXC_GPIO_AD_35_GPIO10_IO02 0x198 0x3DC 0x0 0xA 0x0 +#define IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x0 0x0 +#define IOMUXC_GPIO_AD_35_USB_OTG1_OC 0x198 0x3DC 0x6BC 0x1 0x1 +#define IOMUXC_GPIO_AD_35_XBAR1_INOUT19 0x198 0x3DC 0x0 0x2 0x0 +#define IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x3 0x0 +#define IOMUXC_GPIO_AD_35_USDHC1_RESET_B 0x198 0x3DC 0x0 0x4 0x0 +#define IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 0x198 0x3DC 0x0 0x5 0x0 +#define IOMUXC_GPIO_AD_35_KPP_COL00 0x198 0x3DC 0x0 0x6 0x0 +#define IOMUXC_GPIO_AD_35_LPUART10_RTS_B 0x198 0x3DC 0x0 0x8 0x0 +#define IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B 0x198 0x3DC 0x0 0x9 0x0 + +#define IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x19C 0x3E0 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20 0x19C 0x3E0 0x6D8 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 0x19C 0x3E0 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x19C 0x3E0 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x19C 0x3E0 0x0 0x6 0x0 +#define IOMUXC_GPIO_SD_B1_00_KPP_ROW07 0x19C 0x3E0 0x5A8 0x8 0x1 +#define IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 0x19C 0x3E0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x1A0 0x3E4 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21 0x1A0 0x3E4 0x6DC 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 0x1A0 0x3E4 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x1A0 0x3E4 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x1A0 0x3E4 0x58C 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_01_KPP_COL07 0x1A0 0x3E4 0x5A0 0x8 0x1 +#define IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 0x1A0 0x3E4 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 0x1A4 0x3E8 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x1A4 0x3E8 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22 0x1A4 0x3E8 0x6E0 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 0x1A4 0x3E8 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x1A4 0x3E8 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x1A4 0x3E8 0x57C 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_02_KPP_ROW06 0x1A4 0x3E8 0x5A4 0x8 0x1 +#define IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B 0x1A4 0x3E8 0x0 0x9 0x0 + +#define IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x1A8 0x3EC 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23 0x1A8 0x3EC 0x6E4 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 0x1A8 0x3EC 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x1A8 0x3EC 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x1A8 0x3EC 0x580 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_03_KPP_COL06 0x1A8 0x3EC 0x59C 0x8 0x1 +#define IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B 0x1A8 0x3EC 0x0 0x9 0x0 +#define IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 0x1A8 0x3EC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x1AC 0x3F0 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24 0x1AC 0x3F0 0x6E8 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 0x1AC 0x3F0 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x1AC 0x3F0 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x1AC 0x3F0 0x584 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x1AC 0x3F0 0x0 0x8 0x0 +#define IOMUXC_GPIO_SD_B1_04_ENET_QOS_1588_EVENT2_AUX_IN 0x1AC 0x3F0 0x0 0x9 0x0 +#define IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 0x1AC 0x3F0 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 0x1B0 0x3F4 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x1B0 0x3F4 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25 0x1B0 0x3F4 0x6EC 0x2 0x1 +#define IOMUXC_GPIO_SD_B1_05_GPT4_CLK 0x1B0 0x3F4 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x1B0 0x3F4 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x1B0 0x3F4 0x588 0x6 0x1 +#define IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x1B0 0x3F4 0x0 0x8 0x0 +#define IOMUXC_GPIO_SD_B1_05_ENET_QOS_1588_EVENT3_AUX_IN 0x1B0 0x3F4 0x0 0x9 0x0 + +#define IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 0x1B4 0x3F8 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 0x1B4 0x3F8 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 0x1B4 0x3F8 0x570 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN 0x1B4 0x3F8 0x4E0 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_00_LPUART9_TXD 0x1B4 0x3F8 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK 0x1B4 0x3F8 0x610 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 0x1B4 0x3F8 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 0x1B8 0x3FC 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 0x1B8 0x3FC 0x56C 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK 0x1B8 0x3FC 0x4CC 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_01_LPUART9_RXD 0x1B8 0x3FC 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 0x1B8 0x3FC 0x60C 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 0x1B8 0x3FC 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 0x1B8 0x3FC 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 0x1BC 0x400 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 0x1BC 0x400 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 0x1BC 0x400 0x568 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_02_ENET_1G_RX_DATA00 0x1BC 0x400 0x4D0 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B 0x1BC 0x400 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_02_LPSPI4_SOUT 0x1BC 0x400 0x618 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 0x1BC 0x400 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 0x1C0 0x404 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 0x1C0 0x404 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 0x1C0 0x404 0x564 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_03_ENET_1G_RX_DATA01 0x1C0 0x404 0x4D4 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B 0x1C0 0x404 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_03_LPSPI4_SIN 0x1C0 0x404 0x614 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 0x1C0 0x404 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_04_USDHC2_CLK 0x1C4 0x408 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK 0x1C4 0x408 0x578 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_04_ENET_1G_RX_DATA02 0x1C4 0x408 0x4D8 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B 0x1C4 0x408 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 0x1C4 0x408 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 0x1C4 0x408 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 0x1C4 0x408 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 0x1C8 0x40C 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_05_USDHC2_CMD 0x1C8 0x40C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0x1C8 0x40C 0x550 0x1 0x2 +#define IOMUXC_GPIO_SD_B2_05_ENET_1G_RX_DATA03 0x1C8 0x40C 0x4DC 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B 0x1C8 0x40C 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 0x1C8 0x40C 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 0x1C8 0x40C 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 0x1CC 0x410 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B 0x1CC 0x410 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0x1CC 0x410 0x0 0x1 0x0 +#define IOMUXC_GPIO_SD_B2_06_ENET_1G_TX_DATA03 0x1CC 0x410 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 0x1CC 0x410 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 0x1CC 0x410 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 0x1CC 0x410 0x0 0x5 0x0 + +#define IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE 0x1D0 0x414 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0x1D0 0x414 0x574 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_07_ENET_1G_TX_DATA02 0x1D0 0x414 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B 0x1D0 0x414 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 0x1D0 0x414 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x1D0 0x414 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK 0x1D0 0x414 0x5E4 0x6 0x1 +#define IOMUXC_GPIO_SD_B2_07_ENET_TX_ER 0x1D0 0x414 0x0 0x8 0x0 +#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x1D0 0x414 0x4A0 0x9 0x1 +#define IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 0x1D0 0x414 0x0 0xA 0x0 + +#define IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 0x1D4 0x418 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 0x1D4 0x418 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0x1D4 0x418 0x554 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_08_ENET_1G_TX_DATA01 0x1D4 0x418 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B 0x1D4 0x418 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 0x1D4 0x418 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 0x1D4 0x418 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 0x1D4 0x418 0x5DC 0x6 0x1 + +#define IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 0x1D8 0x41C 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 0x1D8 0x41C 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0x1D8 0x41C 0x558 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_09_ENET_1G_TX_DATA00 0x1D8 0x41C 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B 0x1D8 0x41C 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 0x1D8 0x41C 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 0x1D8 0x41C 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_09_LPSPI2_SOUT 0x1D8 0x41C 0x5EC 0x6 0x1 + +#define IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 0x1DC 0x420 0x0 0xA 0x0 +#define IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 0x1DC 0x420 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0x1DC 0x420 0x55C 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN 0x1DC 0x420 0x0 0x2 0x0 +#define IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B 0x1DC 0x420 0x0 0x3 0x0 +#define IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 0x1DC 0x420 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 0x1DC 0x420 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_10_LPSPI2_SIN 0x1DC 0x420 0x5E8 0x6 0x1 + +#define IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 0x1E0 0x424 0x0 0x0 0x0 +#define IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x1E0 0x424 0x560 0x1 0x1 +#define IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x1E0 0x424 0x4E8 0x2 0x1 +#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x1E0 0x424 0x4C4 0x3 0x1 +#define IOMUXC_GPIO_SD_B2_11_GPT6_CLK 0x1E0 0x424 0x0 0x4 0x0 +#define IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x1E0 0x424 0x0 0x5 0x0 +#define IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 0x1E0 0x424 0x5E0 0x6 0x1 +#define IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 0x1E0 0x424 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x1E4 0x428 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN 0x1E4 0x428 0x4E0 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0 0x1E4 0x428 0x63C 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26 0x1E4 0x428 0x6F0 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x1E4 0x428 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x1E4 0x428 0x4F8 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 0x1E4 0x428 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x1E8 0x42C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK 0x1E8 0x42C 0x4CC 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER 0x1E8 0x42C 0x4E4 0x2 0x1 +#define IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1 0x1E8 0x42C 0x640 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27 0x1E8 0x42C 0x6F4 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x1E8 0x42C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x1E8 0x42C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x1E8 0x42C 0x4FC 0x9 0x0 +#define IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 0x1E8 0x42C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 0x1EC 0x430 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x1EC 0x430 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00 0x1EC 0x430 0x4D0 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL 0x1EC 0x430 0x5BC 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2 0x1EC 0x430 0x644 0x3 0x1 +#define IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28 0x1EC 0x430 0x6F8 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x1EC 0x430 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x1EC 0x430 0x4F0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD 0x1EC 0x430 0x620 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x1F0 0x434 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01 0x1F0 0x434 0x4D4 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA 0x1F0 0x434 0x5C0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0 0x1F0 0x434 0x648 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29 0x1F0 0x434 0x6FC 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x1F0 0x434 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x1F0 0x434 0x4F4 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD 0x1F0 0x434 0x61C 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 0x1F0 0x434 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x1F4 0x438 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02 0x1F4 0x438 0x4D8 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_04_LPUART4_RXD 0x1F4 0x438 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1 0x1F4 0x438 0x64C 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30 0x1F4 0x438 0x700 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x1F4 0x438 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x1F4 0x438 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK 0x1F4 0x438 0x600 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 0x1F4 0x438 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 0x1F8 0x43C 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x1F8 0x43C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03 0x1F8 0x43C 0x4DC 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B 0x1F8 0x43C 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2 0x1F8 0x43C 0x650 0x3 0x1 +#define IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31 0x1F8 0x43C 0x704 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x1F8 0x43C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x1F8 0x43C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN 0x1F8 0x43C 0x604 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x1FC 0x440 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03 0x1FC 0x440 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_06_LPUART4_TXD 0x1FC 0x440 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_06_TMR3_TIMER0 0x1FC 0x440 0x654 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_06_XBAR1_INOUT32 0x1FC 0x440 0x708 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 0x1FC 0x440 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 0x1FC 0x440 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_06_ENET_QOS_TX_DATA03 0x1FC 0x440 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_06_LPSPI3_SOUT 0x1FC 0x440 0x608 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 0x1FC 0x440 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x200 0x444 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02 0x200 0x444 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B 0x200 0x444 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_07_TMR3_TIMER1 0x200 0x444 0x658 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_07_XBAR1_INOUT33 0x200 0x444 0x70C 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 0x200 0x444 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 0x200 0x444 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_07_ENET_QOS_TX_DATA02 0x200 0x444 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 0x200 0x444 0x5F0 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 0x200 0x444 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 0x204 0x448 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x204 0x448 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01 0x204 0x448 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B 0x204 0x448 0x6C8 0x2 0x1 +#define IOMUXC_GPIO_DISP_B1_08_TMR3_TIMER2 0x204 0x448 0x65C 0x3 0x1 +#define IOMUXC_GPIO_DISP_B1_08_XBAR1_INOUT34 0x204 0x448 0x710 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 0x204 0x448 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 0x204 0x448 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_08_ENET_QOS_TX_DATA01 0x204 0x448 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 0x204 0x448 0x5F4 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x208 0x44C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00 0x208 0x44C 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_09_USDHC1_WP 0x208 0x44C 0x6CC 0x2 0x1 +#define IOMUXC_GPIO_DISP_B1_09_TMR4_TIMER0 0x208 0x44C 0x660 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_09_XBAR1_INOUT35 0x208 0x44C 0x714 0x4 0x1 +#define IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 0x208 0x44C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 0x208 0x44C 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_09_ENET_QOS_TX_DATA00 0x208 0x44C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 0x208 0x44C 0x5F8 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 0x208 0x44C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x20C 0x450 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN 0x20C 0x450 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B 0x20C 0x450 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B1_10_TMR4_TIMER1 0x20C 0x450 0x664 0x3 0x2 +#define IOMUXC_GPIO_DISP_B1_10_XBAR1_INOUT36 0x20C 0x450 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 0x20C 0x450 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 0x20C 0x450 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_10_ENET_QOS_TX_EN 0x20C 0x450 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 0x20C 0x450 0x5FC 0x9 0x1 +#define IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 0x20C 0x450 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x210 0x454 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x210 0x454 0x4E8 0x1 0x2 +#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x210 0x454 0x4C4 0x2 0x2 +#define IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2 0x210 0x454 0x668 0x3 0x1 +#define IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37 0x210 0x454 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x210 0x454 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 0x210 0x454 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x210 0x454 0x4A4 0x8 0x0 +#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x210 0x454 0x4A0 0x9 0x2 +#define IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 0x210 0x454 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 0x214 0x458 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x214 0x458 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_00_WDOG1_B 0x214 0x458 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT 0x214 0x458 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER 0x214 0x458 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 0x214 0x458 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 0x214 0x458 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 0x214 0x458 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_00_ENET_QOS_TX_ER 0x214 0x458 0x0 0x8 0x0 + +#define IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x218 0x45C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT 0x218 0x45C 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_01_MQS_LEFT 0x218 0x45C 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_01_WDOG2_B 0x218 0x45C 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 0x218 0x45C 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 0x218 0x45C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 0x218 0x45C 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_01_EWM_OUT_B 0x218 0x45C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M 0x218 0x45C 0x0 0x9 0x0 +#define IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 0x218 0x45C 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 0x21C 0x460 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x21C 0x460 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00 0x21C 0x460 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x21C 0x460 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 0x21C 0x460 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x21C 0x460 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x21C 0x460 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 0x21C 0x460 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_02_ENET_QOS_TX_DATA00 0x21C 0x460 0x0 0x8 0x0 + +#define IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 0x220 0x464 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x220 0x464 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01 0x220 0x464 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x220 0x464 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 0x220 0x464 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK 0x220 0x464 0x66C 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x220 0x464 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 0x220 0x464 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_03_ENET_QOS_TX_DATA01 0x220 0x464 0x0 0x8 0x0 + +#define IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x224 0x468 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN 0x224 0x468 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x224 0x468 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 0x224 0x468 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x224 0x468 0x678 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x224 0x468 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 0x224 0x468 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_04_ENET_QOS_TX_EN 0x224 0x468 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 0x224 0x468 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 0x228 0x46C 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x228 0x46C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK 0x228 0x46C 0x4C0 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK 0x228 0x46C 0x4A8 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 0x228 0x46C 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x228 0x46C 0x670 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x228 0x46C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 0x228 0x46C 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_05_ENET_QOS_TX_CLK 0x228 0x46C 0x4A4 0x8 0x1 + +#define IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 0x22C 0x470 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x22C 0x470 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00 0x22C 0x470 0x4B0 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD 0x22C 0x470 0x630 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x22C 0x470 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x22C 0x470 0x674 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x22C 0x470 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x22C 0x470 0x4F0 0x8 0x1 + +#define IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x230 0x474 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01 0x230 0x474 0x4B4 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD 0x230 0x474 0x62C 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x230 0x474 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x230 0x474 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x230 0x474 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x230 0x474 0x4F4 0x8 0x1 +#define IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 0x230 0x474 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 0x234 0x478 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x234 0x478 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN 0x234 0x478 0x4B8 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD 0x234 0x478 0x638 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_08_ARM_CM7_EVENTO 0x234 0x478 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK 0x234 0x478 0x67C 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 0x234 0x478 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_08_ENET_QOS_RX_EN 0x234 0x478 0x4F8 0x8 0x1 +#define IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD 0x234 0x478 0x620 0x9 0x2 + +#define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x238 0x47C 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x238 0x47C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x238 0x47C 0x4BC 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x238 0x47C 0x634 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_09_ARM_CM7_EVENTI 0x238 0x47C 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC 0x238 0x47C 0x680 0x4 0x1 +#define IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 0x238 0x47C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_09_ENET_QOS_RX_ER 0x238 0x47C 0x4FC 0x8 0x1 +#define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x238 0x47C 0x61C 0x9 0x2 + +#define IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 0x23C 0x480 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x23C 0x480 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO 0x23C 0x480 0x6A8 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD 0x23C 0x480 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x23C 0x480 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38 0x23C 0x480 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x23C 0x480 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL 0x23C 0x480 0x5BC 0x6 0x1 +#define IOMUXC_GPIO_DISP_B2_10_ENET_QOS_RX_ER 0x23C 0x480 0x4FC 0x8 0x2 +#define IOMUXC_GPIO_DISP_B2_10_SPDIF_IN 0x23C 0x480 0x6B4 0x9 0x2 + +#define IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x240 0x484 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK 0x240 0x484 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD 0x240 0x484 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x240 0x484 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39 0x240 0x484 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x240 0x484 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA 0x240 0x484 0x5C0 0x6 0x1 +#define IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS 0x240 0x484 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT 0x240 0x484 0x0 0x9 0x0 +#define IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 0x240 0x484 0x0 0xA 0x0 + +#define IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 0x244 0x488 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x244 0x488 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST 0x244 0x488 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX 0x244 0x488 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B 0x244 0x488 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_12_XBAR1_INOUT40 0x244 0x488 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 0x244 0x488 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL 0x244 0x488 0x5C4 0x6 0x1 +#define IOMUXC_GPIO_DISP_B2_12_ENET_QOS_COL 0x244 0x488 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK 0x244 0x488 0x610 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 0x248 0x48C 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x248 0x48C 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x248 0x48C 0x0 0x1 0x0 +#define IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX 0x248 0x48C 0x498 0x2 0x1 +#define IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B 0x248 0x48C 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK 0x248 0x48C 0x4A8 0x4 0x2 +#define IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x248 0x48C 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA 0x248 0x48C 0x5C8 0x6 0x1 +#define IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x248 0x48C 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_13_LPSPI4_SIN 0x248 0x48C 0x614 0x9 0x1 + +#define IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 0x24C 0x490 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_14_FLEXCAN1_TX 0x24C 0x490 0x0 0x6 0x0 +#define IOMUXC_GPIO_DISP_B2_14_ENET_QOS_1588_EVENT0_IN 0x24C 0x490 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_14_LPSPI4_SOUT 0x24C 0x490 0x618 0x9 0x1 +#define IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 0x24C 0x490 0x0 0xA 0x0 +#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x24C 0x490 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD 0x24C 0x490 0x6AC 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_14_WDOG2_B 0x24C 0x490 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x24C 0x490 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x24C 0x490 0x4C4 0x4 0x3 + +#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x250 0x494 0x0 0x0 0x0 +#define IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x250 0x494 0x6B0 0x1 0x1 +#define IOMUXC_GPIO_DISP_B2_15_WDOG1_B 0x250 0x494 0x0 0x2 0x0 +#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 0x250 0x494 0x0 0x3 0x0 +#define IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER0 0x250 0x494 0x0 0x4 0x0 +#define IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 0x250 0x494 0x0 0x5 0x0 +#define IOMUXC_GPIO_DISP_B2_15_FLEXCAN1_RX 0x250 0x494 0x498 0x6 0x2 +#define IOMUXC_GPIO_DISP_B2_15_ENET_QOS_1588_EVENT0_AUX_IN 0x250 0x494 0x0 0x8 0x0 +#define IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 0x250 0x494 0x60C 0x9 0x1 +#define IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 0x250 0x494 0x0 0xA 0x0 + +#endif /* _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H */ diff --git a/arch/arm/boot/dts/integratorap-im-pd1.dts b/arch/arm/boot/dts/integratorap-im-pd1.dts index d47bfb66d069..cc514cf07bff 100644 --- a/arch/arm/boot/dts/integratorap-im-pd1.dts +++ b/arch/arm/boot/dts/integratorap-im-pd1.dts @@ -178,12 +178,12 @@ clock-names = "uartclk", "apb_pclk"; }; - ssp@300000 { + spi@300000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x00300000 0x1000>; interrupts-extended = <&impd1_vic 3>; clocks = <&impd1_sspclk>, <&sysclk>; - clock-names = "spiclk", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; }; impd1_gpio0: gpio@400000 { @@ -249,6 +249,7 @@ /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ max-memory-bandwidth = <40000000>; memory-region = <&impd1_ram>; + dma-ranges; port@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index 9b652cc27b14..9148287fa0a9 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -160,6 +160,7 @@ pci: pciv3@62000000 { compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; + device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; @@ -261,7 +262,7 @@ lm0: bus@c0000000 { compatible = "simple-bus"; ranges = <0x00000000 0xc0000000 0x10000000>; - dma-ranges = <0x00000000 0x80000000 0x10000000>; + dma-ranges = <0x00000000 0xc0000000 0x10000000>; reg = <0xc0000000 0x10000000>; #address-cells = <1>; #size-cells = <1>; @@ -269,7 +270,7 @@ lm1: bus@d0000000 { compatible = "simple-bus"; ranges = <0x00000000 0xd0000000 0x10000000>; - dma-ranges = <0x00000000 0x80000000 0x10000000>; + dma-ranges = <0x00000000 0xd0000000 0x10000000>; reg = <0xd0000000 0x10000000>; #address-cells = <1>; #size-cells = <1>; @@ -277,7 +278,7 @@ lm2: bus@e0000000 { compatible = "simple-bus"; ranges = <0x00000000 0xe0000000 0x10000000>; - dma-ranges = <0x00000000 0x80000000 0x10000000>; + dma-ranges = <0x00000000 0xe0000000 0x10000000>; reg = <0xe0000000 0x10000000>; #address-cells = <1>; #size-cells = <1>; @@ -285,7 +286,7 @@ lm3: bus@f0000000 { compatible = "simple-bus"; ranges = <0x00000000 0xf0000000 0x10000000>; - dma-ranges = <0x00000000 0x80000000 0x10000000>; + dma-ranges = <0x00000000 0xf0000000 0x10000000>; reg = <0xf0000000 0x10000000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts index a1c03c965f17..b7cbc90e1c18 100644 --- a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts +++ b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: ISC /* - * Device Tree file for Gateway 7001 AP + * Device Tree file for Gateway 7001 AP based on IXP422 * Derived from boardfiles written by Imre Kaloz */ @@ -29,7 +29,6 @@ aliases { /* second UART is the primary console */ serial0 = &uart1; - serial1 = &uart0; }; soc { diff --git a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts index a57009436ed8..df2ca6d95ee5 100644 --- a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts +++ b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts @@ -10,26 +10,26 @@ #include <dt-bindings/input/input.h> / { - model = "Netgear WG302 v2"; - compatible = "netgear,wg302v2", "intel,ixp42x"; + model = "Netgear WG302 v1"; + compatible = "netgear,wg302v1", "intel,ixp42x"; #address-cells = <1>; #size-cells = <1>; memory@0 { - /* 16 MB SDRAM according to OpenWrt database */ + /* 32 MB SDRAM according to boot arguments */ device_type = "memory"; - reg = <0x00000000 0x01000000>; + reg = <0x00000000 0x02000000>; }; chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; - stdout-path = "uart1:115200n8"; + /* The RedBoot comes up in 9600 baud so let's keep this */ + bootargs = "console=ttyS0,9600n8"; + stdout-path = "uart1:9600n8"; }; aliases { /* These are switched around */ serial0 = &uart1; - serial1 = &uart0; }; soc { @@ -38,18 +38,17 @@ compatible = "intel,ixp4xx-flash", "cfi-flash"; bank-width = <2>; /* - * 32 MB of Flash in 128 0x20000 sized blocks - * mapped in at CS0 and CS1 + * 8 MB of Flash in 64 0x20000 sized blocks + * mapped in at CS0. */ - reg = <0 0x00000000 0x2000000>; + reg = <0 0x00000000 0x800000>; /* Configure expansion bus to allow writes */ intel,ixp4xx-eb-write-enable = <1>; partitions { compatible = "redboot-fis"; - /* CHECKME: guess this is Redboot FIS */ - fis-index-block = <0xff>; + fis-index-block = <0x3f>; }; }; }; @@ -82,14 +81,14 @@ queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; - phy-handle = <&phy8>; + phy-handle = <&phy30>; mdio { #address-cells = <1>; #size-cells = <0>; - phy8: ethernet-phy@8 { - reg = <8>; + phy30: ethernet-phy@30 { + reg = <30>; }; }; }; diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel-ixp42x.dtsi index d0e0f8afb7c9..84cee8ec3ab8 100644 --- a/arch/arm/boot/dts/intel-ixp42x.dtsi +++ b/arch/arm/boot/dts/intel-ixp42x.dtsi @@ -9,7 +9,7 @@ soc { bus@c4000000 { compatible = "intel,ixp42x-expansion-bus-controller", "syscon"; - reg = <0xc4000000 0x28>; + reg = <0xc4000000 0x30>; }; pci@c0000000 { diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi index 849034a49a3f..03caea6fc6ff 100644 --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -181,7 +181,7 @@ }; &gpio2 { - touch-interrupt { + touch-interrupt-hog { gpio-hog; gpios = <12 GPIO_ACTIVE_LOW>; input; diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts index 66fec5f5d081..5d6d074011df 100644 --- a/arch/arm/boot/dts/keystone-k2e-evm.dts +++ b/arch/arm/boot/dts/keystone-k2e-evm.dts @@ -137,10 +137,10 @@ }; &spi0 { - nor_flash: n25q128a11@0 { + nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "Micron,n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <54000000>; m25p,fast-read; reg = <0>; diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi index 71064483d34f..42cf74db673c 100644 --- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi @@ -12,9 +12,9 @@ qmss: qmss@2a40000 { #size-cells = <1>; clocks = <&chipclk13>; ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0 0x10000>; + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0 0x10000>; qmgrs { #address-cells = <1>; @@ -176,40 +176,40 @@ netcp: netcp@24000000 { interfaces { gbe0: interface-0 { slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; + link-interface = <1>; + phy-handle = <ðphy0>; }; gbe1: interface-1 { slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; + link-interface = <1>; + phy-handle = <ðphy1>; }; }; secondary-slave-ports { port-2 { slave-port = <2>; - link-interface = <2>; + link-interface = <2>; }; port-3 { slave-port = <3>; - link-interface = <2>; + link-interface = <2>; }; port-4 { slave-port = <4>; - link-interface = <2>; + link-interface = <2>; }; port-5 { slave-port = <5>; - link-interface = <2>; + link-interface = <2>; }; port-6 { slave-port = <6>; - link-interface = <2>; + link-interface = <2>; }; port-7 { slave-port = <7>; - link-interface = <2>; + link-interface = <2>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index b8f152e7af7f..65c32946c522 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -141,7 +141,7 @@ clock-names = "pcie"; #address-cells = <3>; #size-cells = <2>; - reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; + reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; ranges = <0x82000000 0 0x60000000 0x60000000 0 0x10000000>; @@ -185,14 +185,14 @@ }; mdio: mdio@24200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x24200f00 0x100>; status = "disabled"; clocks = <&clkcpgmac>; clock-names = "fck"; - bus_freq = <2500000>; + bus_freq = <2500000>; }; /include/ "keystone-k2e-netcp.dtsi" }; diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index d800f26b6275..88be868cf71e 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -392,7 +392,7 @@ pinctrl-0 = <&qspi_pins>; cdns,rclk-en; - flash0: m25p80@0 { + flash0: flash@0 { compatible = "s25fl512s", "jedec,spi-nor"; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts index 2a2d38cf0fff..bd84d7f0f2fe 100644 --- a/arch/arm/boot/dts/keystone-k2g-ice.dts +++ b/arch/arm/boot/dts/keystone-k2g-ice.dts @@ -325,7 +325,7 @@ cdns,rclk-en; status = "okay"; - flash0: m25p80@0 { + flash0: flash@0 { compatible = "s25fl256s1", "jedec,spi-nor"; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi index d0e6a9a43402..f6306933ff42 100644 --- a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi @@ -125,7 +125,7 @@ netcp: netcp@4000000 { interfaces { gbe0: interface-0 { slave-port = <0>; - link-interface = <5>; + link-interface = <5>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 37198294f4b2..380dd9d637ee 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -262,7 +262,7 @@ */ ti,system-reboot-controller; mbox-names = "rx", "tx"; - mboxes= <&msgmgr 5 2>, + mboxes = <&msgmgr 5 2>, <&msgmgr 0 0>; reg-names = "debug_messages"; reg = <0x02921c00 0x400>; @@ -326,13 +326,13 @@ dss: dss@02540000 { compatible = "ti,k2g-dss"; - reg = <0x02540000 0x400>, + reg = <0x02540000 0x400>, <0x02550000 0x1000>, <0x02557000 0x1000>, <0x0255a800 0x100>, <0x0255ac00 0x100>; reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; - clocks = <&k2g_clks 0x2 0>, + clocks = <&k2g_clks 0x2 0>, <&k2g_clks 0x2 1>; clock-names = "fck", "vp1"; interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>; @@ -348,7 +348,7 @@ edma0: edma@2700000 { compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; - reg = <0x02700000 0x8000>; + reg = <0x02700000 0x8000>; reg-names = "edma3_cc"; interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>, @@ -367,19 +367,19 @@ edma0_tptc0: tptc@2760000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x02760000 0x400>; + reg = <0x02760000 0x400>; power-domains = <&k2g_pds 0x3f>; }; edma0_tptc1: tptc@2768000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x02768000 0x400>; + reg = <0x02768000 0x400>; power-domains = <&k2g_pds 0x3f>; }; edma1: edma@2728000 { compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; - reg = <0x02728000 0x8000>; + reg = <0x02728000 0x8000>; reg-names = "edma3_cc"; interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>, @@ -402,13 +402,13 @@ edma1_tptc0: tptc@27b0000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x027b0000 0x400>; + reg = <0x027b0000 0x400>; power-domains = <&k2g_pds 0x4f>; }; edma1_tptc1: tptc@27b8000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x027b8000 0x400>; + reg = <0x027b8000 0x400>; power-domains = <&k2g_pds 0x4f>; }; diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts index ad4e22afe133..4a91f5ded402 100644 --- a/arch/arm/boot/dts/keystone-k2hk-evm.dts +++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts @@ -161,10 +161,10 @@ }; &spi0 { - nor_flash: n25q128a11@0 { + nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "Micron,n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <54000000>; m25p,fast-read; reg = <0>; diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi index 022d93c366c7..8a421c65f920 100644 --- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi @@ -12,9 +12,9 @@ qmss: qmss@2a40000 { #size-cells = <1>; clocks = <&chipclk13>; ranges; - queue-range = <0 0x4000>; - linkram0 = <0x100000 0x8000>; - linkram1 = <0x0 0x10000>; + queue-range = <0 0x4000>; + linkram0 = <0x100000 0x8000>; + linkram1 = <0x0 0x10000>; qmgrs { #address-cells = <1>; @@ -150,7 +150,7 @@ netcp: netcp@2000000 { #size-cells = <1>; /* NetCP address range */ - ranges = <0 0x2000000 0x100000>; + ranges = <0 0x2000000 0x100000>; clocks = <&clkpa>, <&clkcpgmac>; clock-names = "pa_clk", "ethss_clk"; @@ -207,11 +207,11 @@ netcp: netcp@2000000 { secondary-slave-ports { port-2 { slave-port = <2>; - link-interface = <2>; + link-interface = <2>; }; port-3 { slave-port = <3>; - link-interface = <2>; + link-interface = <2>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi index 8a9447703310..da6d3934c2e8 100644 --- a/arch/arm/boot/dts/keystone-k2hk.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk.dtsi @@ -282,14 +282,14 @@ }; mdio: mdio@2090300 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x02090300 0x100>; status = "disabled"; clocks = <&clkcpgmac>; clock-names = "fck"; - bus_freq = <2500000>; + bus_freq = <2500000>; }; /include/ "keystone-k2hk-netcp.dtsi" }; diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts index e200533d26a4..1c880cf8fa91 100644 --- a/arch/arm/boot/dts/keystone-k2l-evm.dts +++ b/arch/arm/boot/dts/keystone-k2l-evm.dts @@ -110,10 +110,10 @@ }; &spi0 { - nor_flash: n25q128a11@0 { + nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "Micron,n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <54000000>; m25p,fast-read; reg = <0>; diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi index e96ca664abc2..5ec6680a533d 100644 --- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi @@ -12,9 +12,9 @@ qmss: qmss@2a40000 { #size-cells = <1>; clocks = <&chipclk13>; ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ qmgrs { #address-cells = <1>; @@ -174,24 +174,24 @@ netcp: netcp@26000000 { interfaces { gbe0: interface-0 { slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; + link-interface = <1>; + phy-handle = <ðphy0>; }; gbe1: interface-1 { slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; + link-interface = <1>; + phy-handle = <ðphy1>; }; }; secondary-slave-ports { port-2 { slave-port = <2>; - link-interface = <2>; + link-interface = <2>; }; port-3 { slave-port = <3>; - link-interface = <2>; + link-interface = <2>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index dff5fea72b2f..421a02bbc9d3 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -47,7 +47,7 @@ reg-shift = <2>; reg-io-width = <4>; reg = <0x02348400 0x100>; - clocks = <&clkuart2>; + clocks = <&clkuart2>; interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>; }; @@ -57,7 +57,7 @@ reg-shift = <2>; reg-io-width = <4>; reg = <0x02348800 0x100>; - clocks = <&clkuart3>; + clocks = <&clkuart3>; interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; }; @@ -388,14 +388,14 @@ }; mdio: mdio@26200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x26200f00 0x100>; status = "disabled"; clocks = <&clkcpgmac>; clock-names = "fck"; - bus_freq = <2500000>; + bus_freq = <2500000>; }; /include/ "keystone-k2l-netcp.dtsi" }; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index fc9fdc857ae8..50789f9e2215 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -14,7 +14,7 @@ interrupt-parent = <&gic>; aliases { - serial0 = &uart0; + serial0 = &uart0; spi0 = &spi0; spi1 = &spi1; spi2 = &spi2; @@ -61,11 +61,11 @@ }; psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; }; soc0: soc@0 { @@ -119,7 +119,7 @@ reg-shift = <2>; reg-io-width = <4>; reg = <0x02530c00 0x100>; - clocks = <&clkuart0>; + clocks = <&clkuart0>; interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; }; @@ -129,7 +129,7 @@ reg-shift = <2>; reg-io-width = <4>; reg = <0x02531000 0x100>; - clocks = <&clkuart1>; + clocks = <&clkuart1>; interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; }; @@ -301,7 +301,7 @@ clock-names = "pcie"; #address-cells = <3>; #size-cells = <2>; - reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; + reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; ranges = <0x82000000 0 0x50000000 0x50000000 0 0x10000000>; diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi index 396bcba08adb..705c0d7effed 100644 --- a/arch/arm/boot/dts/kirkwood-6192.dtsi +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi @@ -26,12 +26,22 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gate_clk 2>; status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index faa05849a40d..8e311165fd13 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -26,12 +26,22 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gate_clk 2>; status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index e84c54b77dea..e33723160ce7 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -30,12 +30,22 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gate_clk 2>; status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie1: pcie@2,0 { @@ -48,12 +58,22 @@ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 10>; + interrupt-names = "intx", "error"; + interrupts = <10>, <45>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gate_clk 18>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi index 299c147298c3..c3469a2fc58a 100644 --- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi @@ -26,12 +26,22 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gate_clk 2>; status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-c200-v1.dts b/arch/arm/boot/dts/kirkwood-c200-v1.dts new file mode 100644 index 000000000000..f59ff7578dfc --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-c200-v1.dts @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Ctera C200 V1 Board Description + * Copyright 2021-2022 Pawel Dembicki <paweldembicki@gmail.com> + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "Ctera C200 V1"; + compatible = "ctera,c200-v1", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + + power { + label = "Power Button"; + linux,code = <KEY_POWER>; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + + reset { + label = "Reset Button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + + usb1 { + label = "USB1 Button"; + linux,code = <BTN_0>; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + + usb2 { + label = "USB2 Button"; + linux,code = <BTN_1>; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_poweroff>; + pinctrl-names = "default"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds>; + pinctrl-names = "default"; + + led-0 { + function = LED_FUNCTION_DISK; + function-enumerator = <2>; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + + led-1 { + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + led-2 { + function = LED_FUNCTION_DISK; + function-enumerator = <2>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + }; + + led-3 { + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + + led-4 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + led-5 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + led-6 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + led-7 { + function = LED_FUNCTION_DISK_ERR; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + led-8 { + function = LED_FUNCTION_DISK_ERR; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + led-9 { + function = LED_FUNCTION_USB; + function-enumerator = <1>; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + }; + + led-10 { + function = LED_FUNCTION_USB; + function-enumerator = <1>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port2>; + }; + + led-11 { + function = LED_FUNCTION_USB; + function-enumerator = <2>; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + + led-12 { + function = LED_FUNCTION_USB; + function-enumerator = <2>; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port1>; + }; + }; +}; + +ð0 { + status = "okay"; +}; + +ð0port { + phy-handle = <ðphy9>; +}; + +&i2c0 { + status = "okay"; + + rtc@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + + lm63@4c { + compatible = "national,lm63"; + reg = <0x4c>; + }; +}; + +&mdio { + status = "okay"; + + ethphy9: ethernet-phy@9 { + reg = <9>; + }; +}; + +&nand { + status = "okay"; + chip-delay = <40>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x200000>; + }; + + partition@200000 { + label = "certificate"; + reg = <0x0200000 0x100000>; + }; + + partition@300000 { + label = "preset_cfg"; + reg = <0x0300000 0x100000>; + }; + + partition@400000 { + label = "dev_params"; + reg = <0x0400000 0x100000>; + }; + + partition@500000 { + label = "active_bank"; + reg = <0x0500000 0x0100000>; + }; + + partition@600000 { + label = "magic"; + reg = <0x0600000 0x0100000>; + }; + + partition@700000 { + label = "bank1"; + reg = <0x0700000 0x2800000>; + }; + + partition@2f00000 { + label = "bank2"; + reg = <0x2f00000 0x2800000>; + }; + + /* 0x5700000-0x5a00000 undefined in vendor firmware */ + + partition@5a00000 { + label = "reserved"; + reg = <0x5a00000 0x2000000>; + }; + + partition@7a00000 { + label = "rootfs"; + reg = <0x7a00000 0x8600000>; + }; +}; + +&pinctrl { + /* Buzzer gpios are connected to two pins of buzzer. + * This buzzer require a modulated signal from gpio. + * Leave it as is due lack of proper driver. + */ + pmx_buzzer: pmx-buzzer { + marvell,pins = "mpp12", "mpp13"; + marvell,function = "gpio"; + }; + + pmx_leds: pmx-leds { + marvell,pins = "mpp14", "mpp15", "mpp16", "mpp17", "mpp38", + "mpp39", "mpp40", "mpp42", "mpp43", "mpp44", + "mpp45", "mpp46", "mpp47"; + marvell,function = "gpio"; + }; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp28", "mpp29", "mpp48", "mpp49"; + marvell,function = "gpio"; + }; + + pmx_poweroff: pmx-poweroff { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; +}; + +&rtc { + status = "disabled"; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + #trigger-source-cells = <0>; + + hub_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + hub_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts index b3ad3f607d31..c32300611d2c 100644 --- a/arch/arm/boot/dts/kirkwood-dir665.dts +++ b/arch/arm/boot/dts/kirkwood-dir665.dts @@ -78,7 +78,7 @@ spi@10600 { status = "okay"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 7b151acb9984..88b70ba1c8fe 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -10,6 +10,11 @@ ocp@f1000000 { pinctrl: pin-controller@10000 { + /* Non-default UART pins */ + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp4", "mpp5"; + }; + pmx_power_hdd: pmx-power-hdd { marvell,pins = "mpp10"; marvell,function = "gpo"; @@ -213,22 +218,11 @@ &mdio { status = "okay"; - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - ethphy1: ethernet-phy@8 { reg = <8>; }; }; -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - ð1 { status = "okay"; ethernet1-port@0 { diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index 217bd374e52b..8f6c387d3a8b 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -198,7 +198,7 @@ spi@10600 { status = "okay"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts new file mode 100644 index 000000000000..0f555eb45bda --- /dev/null +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS + */ + +/dts-v1/; +#include "lan966x-kontron-kswitch-d10-mmt.dtsi" + +/ { + model = "Kontron KSwitch D10 MMT 6G-2GS"; + compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921", + "microchip,lan9668", "microchip,lan966"; + + aliases { + i2c0 = &i2c4; + i2c1 = &i2c1; + }; + + sfp0: sfp0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c4>; + los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <2500>; + tx-disable-gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 0 2 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&sgpio_out 2 0 GPIO_ACTIVE_HIGH>; + rate-select1-gpios = <&sgpio_out 2 1 GPIO_ACTIVE_HIGH>; + }; + + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + los-gpios = <&sgpio_in 1 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 1 3 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <2500>; + tx-disable-gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 0 3 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&sgpio_out 2 2 GPIO_ACTIVE_HIGH>; + rate-select1-gpios = <&sgpio_out 2 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&flx1 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; + + i2c1: i2c@600 { + pinctrl-0 = <&fc1_c_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; + + i2c4: i2c@600 { + pinctrl-0 = <&fc4_b_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&gpio { + fc1_c_pins: fc1-c-i2c-pins { + /* SCL, SDA */ + pins = "GPIO_47", "GPIO_48"; + function = "fc1_c"; + }; + + fc4_b_pins: fc4-b-i2c-pins { + /* SCL, SDA */ + pins = "GPIO_57", "GPIO_58"; + function = "fc4_b"; + }; +}; + +&port2 { + phys = <&serdes 2 SERDES6G(0)>; + sfp = <&sfp0>; + managed = "in-band-status"; + phy-mode = "sgmii"; + status = "okay"; +}; + +&port3 { + phys = <&serdes 3 SERDES6G(1)>; + sfp = <&sfp1>; + managed = "in-band-status"; + phy-mode = "sgmii"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts new file mode 100644 index 000000000000..5feef9a59a79 --- /dev/null +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for the Kontron KSwitch D10 MMT 8G + */ + +/dts-v1/; +#include "lan966x-kontron-kswitch-d10-mmt.dtsi" + +/ { + model = "Kontron KSwitch D10 MMT 8G"; + compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921", + "microchip,lan9668", "microchip,lan966"; +}; + +&mdio0 { + phy2: ethernet-phy@3 { + reg = <3>; + }; + + phy3: ethernet-phy@4 { + reg = <4>; + }; +}; + +&port2 { + phys = <&serdes 2 SERDES6G(0)>; + phy-handle = <&phy2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&port3 { + phys = <&serdes 3 SERDES6G(1)>; + phy-handle = <&phy3>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi new file mode 100644 index 000000000000..0097e72e3fb2 --- /dev/null +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common part of the device tree for the Kontron KSwitch D10 MMT + */ + +/dts-v1/; +#include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" + +/ { + aliases { + serial0 = &usart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +&flx0 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; + + usart0: serial@200 { + pinctrl-0 = <&usart0_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&flx3 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>; + status = "okay"; + + spi3: spi@400 { + pinctrl-0 = <&fc3_b_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + }; +}; + +&gpio { + fc3_b_pins: fc3-b-pins { + /* SCK, MISO, MOSI */ + pins = "GPIO_51", "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + miim_c_pins: miim-c-pins { + /* MDC, MDIO */ + pins = "GPIO_59", "GPIO_60"; + function = "miim_c"; + }; + + sgpio_a_pins: sgpio-a-pins { + /* SCK, D0, D1 */ + pins = "GPIO_32", "GPIO_33", "GPIO_34"; + function = "sgpio_a"; + }; + + sgpio_b_pins: sgpio-b-pins { + /* LD */ + pins = "GPIO_64"; + function = "sgpio_b"; + }; + + usart0_pins: usart0-pins { + /* RXD, TXD */ + pins = "GPIO_25", "GPIO_26"; + function = "fc0_b"; + }; + + usbs_a_pins: usbs-a-pins { + /* VBUS_DET */ + pins = "GPIO_66"; + function = "gpio"; + }; +}; + +&mdio0 { + pinctrl-0 = <&miim_c_pins>; + pinctrl-names = "default"; + reset-gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + clock-frequency = <2500000>; + status = "okay"; + + phy4: ethernet-phy@5 { + reg = <5>; + coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; + }; + + phy5: ethernet-phy@6 { + reg = <6>; + coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; + }; + + phy6: ethernet-phy@7 { + reg = <7>; + coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; + }; + + phy7: ethernet-phy@8 { + reg = <8>; + coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; + }; +}; + +&mdio1 { + status = "okay"; +}; + +&phy0 { + status = "okay"; +}; + +&phy1 { + status = "okay"; +}; + +&port0 { + phys = <&serdes 0 CU(0)>; + phy-handle = <&phy0>; + phy-mode = "gmii"; + status = "okay"; +}; + +&port1 { + phys = <&serdes 1 CU(1)>; + phy-handle = <&phy1>; + phy-mode = "gmii"; + status = "okay"; +}; + +&port4 { + phys = <&serdes 4 SERDES6G(2)>; + phy-handle = <&phy4>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&port5 { + phys = <&serdes 5 SERDES6G(2)>; + phy-handle = <&phy5>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&port6 { + phys = <&serdes 6 SERDES6G(2)>; + phy-handle = <&phy6>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&port7 { + phys = <&serdes 7 SERDES6G(2)>; + phy-handle = <&phy7>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + +&sgpio { + pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>; + pinctrl-names = "default"; + bus-frequency = <8000000>; + /* arbitrary range because all GPIOs are in software mode */ + microchip,sgpio-port-ranges = <0 11>; + status = "okay"; + + sgpio_in: gpio@0 { + ngpios = <128>; + }; + + sgpio_out: gpio@1 { + ngpios = <128>; + }; +}; + +&switch { + status = "okay"; +}; + +&udc { + pinctrl-0 = <&usbs_a_pins>; + pinctrl-names = "default"; + atmel,vbus-gpio = <&gpio 66 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lan966x-pcb8290.dts b/arch/arm/boot/dts/lan966x-pcb8290.dts new file mode 100644 index 000000000000..77187f59f04d --- /dev/null +++ b/arch/arm/boot/dts/lan966x-pcb8290.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Horatiu Vultur <horatiu.vultur@microchip.com> + */ +/dts-v1/; +#include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" + +/ { + model = "Microchip EVB LAN9668"; + compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966"; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +&aes { + status = "disabled"; /* Reserved by secure OS */ +}; + +&gpio { + miim_a_pins: mdio-pins { + /* MDC, MDIO */ + pins = "GPIO_28", "GPIO_29"; + function = "miim_a"; + }; + + pps_out_pins: pps-out-pins { + /* 1pps output */ + pins = "GPIO_38"; + function = "ptpsync_3"; + }; + + ptp_ext_pins: ptp-ext-pins { + /* 1pps input */ + pins = "GPIO_35"; + function = "ptpsync_0"; + }; + + udc_pins: ucd-pins { + /* VBUS_DET B */ + pins = "GPIO_8"; + function = "usb_slave_b"; + }; +}; + +&mdio0 { + pinctrl-0 = <&miim_a_pins>; + pinctrl-names = "default"; + status = "okay"; + + ext_phy0: ethernet-phy@7 { + reg = <7>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy1: ethernet-phy@8 { + reg = <8>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy2: ethernet-phy@9 { + reg = <9>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy3: ethernet-phy@10 { + reg = <10>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy4: ethernet-phy@15 { + reg = <15>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy5: ethernet-phy@16 { + reg = <16>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy6: ethernet-phy@17 { + reg = <17>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy7: ethernet-phy@18 { + reg = <18>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; +}; + +&port0 { + reg = <2>; + phy-handle = <&ext_phy2>; + phy-mode = "qsgmii"; + phys = <&serdes 0 SERDES6G(1)>; + status = "okay"; +}; + +&port1 { + reg = <3>; + phy-handle = <&ext_phy3>; + phy-mode = "qsgmii"; + phys = <&serdes 1 SERDES6G(1)>; + status = "okay"; +}; + +&port2 { + reg = <0>; + phy-handle = <&ext_phy0>; + phy-mode = "qsgmii"; + phys = <&serdes 2 SERDES6G(1)>; + status = "okay"; +}; + +&port3 { + reg = <1>; + phy-handle = <&ext_phy1>; + phy-mode = "qsgmii"; + phys = <&serdes 3 SERDES6G(1)>; + status = "okay"; +}; + +&port4 { + reg = <6>; + phy-handle = <&ext_phy6>; + phy-mode = "qsgmii"; + phys = <&serdes 4 SERDES6G(2)>; + status = "okay"; +}; + +&port5 { + reg = <7>; + phy-handle = <&ext_phy7>; + phy-mode = "qsgmii"; + phys = <&serdes 5 SERDES6G(2)>; + status = "okay"; +}; + +&port6 { + reg = <4>; + phy-handle = <&ext_phy4>; + phy-mode = "qsgmii"; + phys = <&serdes 6 SERDES6G(2)>; + status = "okay"; +}; + +&port7 { + reg = <5>; + phy-handle = <&ext_phy5>; + phy-mode = "qsgmii"; + phys = <&serdes 7 SERDES6G(2)>; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + +&switch { + pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&udc { + pinctrl-0 = <&udc_pins>; + pinctrl-names = "default"; + atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts new file mode 100644 index 000000000000..f4f054cdf2a8 --- /dev/null +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x_pcb8291.dts - Device Tree file for PCB8291 + */ +/dts-v1/; +#include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" + +/ { + model = "Microchip EVB - LAN9662"; + compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &usart3; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; + }; + + leds { + compatible = "gpio-leds"; + + led-s0-blue { + label = "s0:blue"; + gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s0-green { + label = "s0:green"; + gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s1-blue { + label = "s1:blue"; + gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s1-green { + label = "s1:green"; + gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&aes { + status = "disabled"; /* Reserved by secure OS */ +}; + +&gpio { + fc3_b_pins: fc3-b-pins { + /* RX, TX */ + pins = "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + can0_b_pins: can0-b-pins { + /* RX, TX */ + pins = "GPIO_35", "GPIO_36"; + function = "can0_b"; + }; +}; + +&can0 { + pinctrl-0 = <&can0_b_pins>; + pinctrl-names = "default"; + status = "disabled"; /* Conflict with switch */ +}; + +&flx3 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; + + usart3: serial@200 { + pinctrl-0 = <&fc3_b_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&mdio1 { + status = "okay"; +}; + +&phy0 { + status = "okay"; +}; + +&phy1 { + status = "okay"; +}; + +&port0 { + phy-handle = <&phy0>; + phy-mode = "gmii"; + phys = <&serdes 0 CU(0)>; + status = "okay"; +}; + +&port1 { + phy-handle = <&phy1>; + phy-mode = "gmii"; + phys = <&serdes 1 CU(1)>; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + +&switch { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lan966x-pcb8309.dts b/arch/arm/boot/dts/lan966x-pcb8309.dts new file mode 100644 index 000000000000..c436cd20d4b4 --- /dev/null +++ b/arch/arm/boot/dts/lan966x-pcb8309.dts @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x_pcb8309.dts - Device Tree file for PCB8309 + */ +/dts-v1/; +#include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" + +/ { + model = "Microchip EVB - LAN9662"; + compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966"; + + aliases { + serial0 = &usart3; + i2c102 = &i2c102; + i2c103 = &i2c103; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; + }; + + i2c-mux { + compatible = "i2c-mux"; + #address-cells = <1>; + #size-cells = <0>; + mux-controls = <&mux>; + i2c-parent = <&i2c4>; + + i2c102: i2c-sfp@1 { + reg = <1>; + }; + + i2c103: i2c-sfp@2 { + reg = <2>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-s0-green { + label = "s0:green"; + gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s0-red { + label = "s0:red"; + gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s1-green { + label = "s1:green"; + gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s1-red { + label = "s1:red"; + gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&sgpio_out 11 0 GPIO_ACTIVE_HIGH>, /* p11b0 */ + <&sgpio_out 11 1 GPIO_ACTIVE_HIGH>; /* p11b1 */ + }; + + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c102>; + tx-disable-gpios = <&sgpio_out 10 0 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in 2 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 2 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>; + }; + + sfp3: sfp3 { + compatible = "sff,sfp"; + i2c-bus = <&i2c103>; + tx-disable-gpios = <&sgpio_out 10 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in 3 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 3 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&aes { + status = "disabled"; /* Reserved by secure OS */ +}; + +&flx3 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; + + usart3: serial@200 { + pinctrl-0 = <&fc3_b_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; + + i2c4: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&nic_clk>; + pinctrl-0 = <&fc4_b_pins>; + pinctrl-names = "default"; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + i2c-sda-hold-time-ns = <1500>; + status = "okay"; + }; +}; + +&gpio { + fc3_b_pins: fc3-b-pins { + /* RXD, TXD */ + pins = "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + fc4_b_pins: fc4-b-pins { + /* SCL, SDA */ + pins = "GPIO_57", "GPIO_58"; + function = "fc4_b"; + }; + + sgpio_a_pins: sgpio-a-pins { + /* SCK, D0, D1, LD */ + pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35"; + function = "sgpio_a"; + }; +}; + +&mdio1 { + status = "okay"; +}; + +&phy0 { + status = "okay"; +}; + +&phy1 { + status = "okay"; +}; + +&port0 { + phy-handle = <&phy0>; + phy-mode = "gmii"; + phys = <&serdes 0 CU(0)>; + status = "okay"; +}; + +&port1 { + phy-handle = <&phy1>; + phy-mode = "gmii"; + phys = <&serdes 1 CU(1)>; + status = "okay"; +}; + +&port2 { + sfp = <&sfp2>; + managed = "in-band-status"; + phy-mode = "sgmii"; + phys = <&serdes 2 SERDES6G(0)>; + status = "okay"; +}; + +&port3 { + sfp = <&sfp3>; + managed = "in-band-status"; + phy-mode = "sgmii"; + phys = <&serdes 3 SERDES6G(1)>; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + +&sgpio { + pinctrl-0 = <&sgpio_a_pins>; + pinctrl-names = "default"; + microchip,sgpio-port-ranges = <0 3>, <8 11>; + status = "okay"; + + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + +&switch { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi new file mode 100644 index 000000000000..0bf818713422 --- /dev/null +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC + * + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries + * + * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> + * + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mfd/atmel-flexcom.h> +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/microchip,lan966x.h> + +/ { + model = "Microchip LAN966 family SoC"; + compatible = "microchip,lan966"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + clock-frequency = <600000000>; + reg = <0x0>; + }; + }; + + clocks { + sys_clk: sys_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <165625000>; + }; + + cpu_clk: cpu_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + ddr_clk: ddr_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + + nic_clk: nic_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + clks: clock-controller@e00c00a8 { + compatible = "microchip,lan966x-gck"; + #clock-cells = <1>; + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; + clock-names = "cpu", "ddr", "sys"; + reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <37500000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + udc: usb@200000 { + compatible = "microchip,lan9662-udc", + "atmel,sama5d3-udc"; + reg = <0x00200000 0x80000>, + <0xe0808000 0x400>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + switch: switch@e0000000 { + compatible = "microchip,lan966x-switch"; + reg = <0xe0000000 0x0100000>, + <0xe2000000 0x0800000>; + reg-names = "cpu", "gcb"; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "xtr", "fdma", "ana", "ptp", + "ptp-ext"; + resets = <&reset 0>; + reset-names = "switch"; + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + port4: port@4 { + reg = <4>; + status = "disabled"; + }; + + port5: port@5 { + reg = <5>; + status = "disabled"; + }; + + port6: port@6 { + reg = <6>; + status = "disabled"; + }; + + port7: port@7 { + reg = <7>; + status = "disabled"; + }; + }; + }; + + flx0: flexcom@e0040000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0040000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0040000 0x800>; + status = "disabled"; + + usart0: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi0: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flx1: flexcom@e0044000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0044000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0044000 0x800>; + status = "disabled"; + + usart1: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi1: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + trng: rng@e0048000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xe0048000 0x100>; + clocks = <&nic_clk>; + }; + + aes: crypto@e004c000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xe004c000 0x100>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, + <&dma0 AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "aes_clk"; + }; + + flx2: flexcom@e0060000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0060000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0060000 0x800>; + status = "disabled"; + + usart2: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flx3: flexcom@e0064000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0064000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0064000 0x800>; + status = "disabled"; + + usart3: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + dma0: dma-controller@e0068000 { + compatible = "microchip,sama7g5-dma"; + reg = <0xe0068000 0x1000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&nic_clk>; + clock-names = "dma_clk"; + }; + + sha: crypto@e006c000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xe006c000 0xec>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>; + dma-names = "tx"; + clocks = <&nic_clk>; + clock-names = "sha_clk"; + }; + + flx4: flexcom@e0070000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0070000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0070000 0x800>; + status = "disabled"; + + usart4: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi4: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + timer0: timer@e008c000 { + compatible = "snps,dw-apb-timer"; + reg = <0xe008c000 0x400>; + clocks = <&nic_clk>; + clock-names = "timer"; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + }; + + watchdog: watchdog@e0090000 { + compatible = "snps,dw-wdt"; + reg = <0xe0090000 0x1000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&nic_clk>; + status = "disabled"; + }; + + cpu_ctrl: syscon@e00c0000 { + compatible = "microchip,lan966x-cpu-syscon", "syscon"; + reg = <0xe00c0000 0x350>; + }; + + can0: can@e081c000 { + compatible = "bosch,m_can"; + reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&clks GCK_ID_MCAN0>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can1: can@e0820000 { + compatible = "bosch,m_can"; + reg = <0xe0820000 0xfc>, <0x00100000 0x8000>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&clks GCK_ID_MCAN1>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + reset: reset-controller@e200400c { + compatible = "microchip,lan966x-switch-reset"; + reg = <0xe200400c 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + }; + + gpio: pinctrl@e2004064 { + compatible = "microchip,lan966x-pinctrl"; + reg = <0xe2004064 0xb4>, + <0xe2010024 0x138>; + resets = <&reset 0>; + reset-names = "switch"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 78>; + interrupt-controller; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + }; + + mdio0: mdio@e2004118 { + compatible = "microchip,lan966x-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe2004118 0x24>; + clocks = <&sys_clk>; + status = "disabled"; + }; + + mdio1: mdio@e200413c { + compatible = "microchip,lan966x-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe200413c 0x24>, + <0xe2010020 0x4>; + clocks = <&sys_clk>; + status = "disabled"; + + phy0: ethernet-phy@1 { + reg = <1>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + phy1: ethernet-phy@2 { + reg = <2>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + sgpio: gpio@e2004190 { + compatible = "microchip,sparx5-sgpio"; + reg = <0xe2004190 0x118>; + clocks = <&sys_clk>; + resets = <&reset 0>; + reset-names = "switch"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgpio_in: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + sgpio_out: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + }; + }; + + hwmon: hwmon@e2010180 { + compatible = "microchip,lan9668-hwmon"; + reg = <0xe2010180 0xc>, + <0xe20042a8 0xc>; + reg-names = "pvt", "fan"; + clocks = <&sys_clk>; + }; + + serdes: serdes@e202c000 { + compatible = "microchip,lan966x-serdes"; + reg = <0xe202c000 0x9c>, + <0xe2004010 0x4>; + #phy-cells = <2>; + status = "disabled"; + }; + + gic: interrupt-controller@e8c11000 { + compatible = "arm,gic-400", "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + reg = <0xe8c11000 0x1000>, + <0xe8c12000 0x2000>, + <0xe8c14000 0x2000>, + <0xe8c16000 0x2000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts index 2a0a98fe67f0..3240c67e0c39 100644 --- a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts @@ -11,3 +11,18 @@ model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit"; compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3"; }; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts index a604d92221a4..c757f0d7781c 100644 --- a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts @@ -11,3 +11,18 @@ model = "LogicPD Zoom DM3730 SOM-LV Development Kit"; compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"; }; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi index b56524cc7fe2..9ba0ea4eb48a 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -27,6 +27,8 @@ /* HS USB Host PHY on PORT 1 */ hsusb2_phy: hsusb2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_reset_pin>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ #phy-cells = <0>; @@ -144,6 +146,8 @@ }; &usbhshost { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_pins>; port2-mode = "ehci-phy"; }; @@ -151,10 +155,7 @@ phys = <0 &hsusb2_phy>; }; - &omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_pins>; mmc3_pins: pinmux_mm3_pins { pinctrl-single,pins = < @@ -250,8 +251,7 @@ }; &omap3_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_reset_pin>; + hsusb2_reset_pin: pinmux_hsusb1_reset_pin { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ @@ -265,21 +265,6 @@ }; }; -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; - &uart2 { interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts index 57bae2aa910e..cb08aa62d967 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts @@ -11,3 +11,11 @@ model = "LogicPD Zoom OMAP35xx Torpedo Development Kit"; compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3430", "ti,omap3"; }; + +&omap3_pmx_core { + isp1763_pins: pinmux_isp1763_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat6.gpio_128 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts index 5532db04046c..07ea822fe405 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts @@ -85,3 +85,12 @@ >; }; }; + +/* The gpio muxing between omap3530 and dm3730 is different for GPIO_128 */ +&omap3_pmx_wkup { + isp1763_pins: pinmux_isp1763_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a58, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_128 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi index 533a47bc4a53..d3da8b1b473b 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi @@ -93,7 +93,8 @@ &gpmc { ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */ + 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */ + 6 0 0x28000000 0x1000000>; /* CS6: 16MB for ISP1763 */ ethernet@gpmc { pinctrl-names = "default"; @@ -102,6 +103,44 @@ interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* gpio129 */ reg = <1 0 0xff>; }; + + usb@6,0 { + pinctrl-names = "default"; + pinctrl-0 = <&isp1763_pins>; + compatible = "nxp,usb-isp1763"; + reg = <0x6 0x0 0xff>; + interrupt-parent = <&gpio5>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host"; + bus-width = <16>; + dr_mode = "host"; + gpmc,mux-add-data = <0>; + gpmc,device-width = <2>; + gpmc,wait-pin = <0>; + gpmc,burst-length = <4>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <45>; + gpmc,cs-wr-off-ns = <45>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <0>; + gpmc,adv-wr-off-ns = <0>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <45>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <25>; + gpmc,rd-cycle-ns = <60>; + gpmc,wr-cycle-ns = <45>; + gpmc,access-ns = <35>; + gpmc,page-burst-access-ns = <0>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <60>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <5>; + gpmc,wr-access-ns = <20>; + }; }; &hdqw1w { diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 10b8249b8ab6..1bb686a7b3ec 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -121,7 +121,7 @@ status = "disabled"; }; - usb0: ehci@40006100 { + usb0: usb@40006100 { compatible = "nxp,lpc1850-ehci", "generic-ehci"; reg = <0x40006100 0x100>; interrupts = <8>; @@ -133,7 +133,7 @@ status = "disabled"; }; - usb1: ehci@40007100 { + usb1: usb@40007100 { compatible = "nxp,lpc1850-ehci", "generic-ehci"; reg = <0x40007100 0x100>; interrupts = <9>; @@ -183,7 +183,7 @@ compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; reg = <0x40010000 0x2000>; interrupts = <5>; - interrupt-names = "macirq"; + interrupt-names = "macirq"; clocks = <&ccu1 CLK_CPU_ETHERNET>; clock-names = "stmmaceth"; resets = <&rgu 22>; diff --git a/arch/arm/boot/dts/ls1021a-iot.dts b/arch/arm/boot/dts/ls1021a-iot.dts new file mode 100644 index 000000000000..ce8e26d7791f --- /dev/null +++ b/arch/arm/boot/dts/ls1021a-iot.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021-2022 NXP + * + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A-IOT Board"; + compatible = "fsl,ls1021a-iot", "fsl,ls1021a"; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_3p3v: regulator-3V3 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_2p5v: regulator-2V5 { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + frame-master; + bitclock-master; + }; + }; +}; + +&can0{ + status = "disabled"; +}; + +&can1{ + status = "disabled"; +}; + +&can2{ + status = "disabled"; +}; + +&can3{ + status = "okay"; +}; + +&dcu { + display = <&display>; + status = "okay"; + + display: display@0 { + bits-per-pixel = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: mode0 { + clock-frequency = <25000000>; + hactive = <640>; + vactive = <480>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <12>; + vsync-len = <2>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; +}; + +&enet0 { + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi1>; + phy-handle = <&phy3>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet2 { + fixed-link = <0 1 1000 0 0>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&esdhc{ + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + pca9555: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sgtl5000: audio-codec@2a { + #sound-dai-cells = <0x0>; + compatible = "fsl,sgtl5000"; + reg = <0x2a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_2p5v>; + clocks = <&sys_mclk>; + }; + + max1239: adc@35 { + compatible = "maxim,max1239"; + reg = <0x35>; + #io-channel-cells = <1>; + }; + + ina2201: core-monitor@44 { + compatible = "ti,ina220"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + ina2202: current-monitor@45 { + compatible = "ti,ina220"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + lm75b: thermal-monitor@48 { + compatible = "national,lm75b"; + reg = <0x48>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + phy3: ethernet-phy@3 { + reg = <0x3>; + }; + + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&qspi { + num-cs = <2>; + status = "okay"; + + s25fl128s: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&sai2 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 2e69d6eab4d1..7c5510e34494 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -122,13 +122,20 @@ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; }; - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; + ifc: memory-controller@1530000 { + compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen 4 3>; + clock-names = "sfp"; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1021a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x1000>; @@ -192,7 +199,7 @@ <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0x7 0x0>; }; }; @@ -640,7 +647,7 @@ status = "disabled"; }; - edma0: edma@2c00000 { + edma0: dma-controller@2c00000 { #dma-cells = <2>; compatible = "fsl,vf610-edma"; reg = <0x0 0x2c00000 0x0 0x10000>, diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi new file mode 100644 index 000000000000..aac42df9ecf6 --- /dev/null +++ b/arch/arm/boot/dts/mba6ulx.dtsi @@ -0,0 +1,569 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel <Markus.Niebel@tq-group.com> + */ + +/ { + model = "TQ-Systems MBA6ULx Baseboard"; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc1; + rtc0 = &rtc0; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <®_mba6ul_3v3>; + enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + beeper: beeper { + compatible = "gpio-beeper"; + gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>; + }; + + gpio_buttons: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_buttons>; + + button1 { + label = "s14"; + linux,code = <KEY_1>; + gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>; + }; + + button2 { + label = "s6"; + linux,code = <KEY_2>; + gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>; + }; + + button3 { + label = "s7"; + linux,code = <KEY_3>; + gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>; + }; + + power-button { + label = "POWER"; + linux,code = <KEY_POWER>; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + status = "okay"; + + led1 { + label = "led1"; + gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_lcd_pwr: regulator-lcd-pwr { + compatible = "regulator-fixed"; + regulator-name = "lcd-pwr"; + gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_mba6ul_3v3: regulator-mba6ul-3v3 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6ul-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_mba6ul_5v0: regulator-mba6ul-5v0 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6ul-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_mpcie: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "mpcie-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + startup-delay-us = <500000>; + vin-supply = <®_mba6ul_3v3>; + }; + + reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 { + compatible = "regulator-fixed"; + gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "otg2-vbus-supply-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_mpcie>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x6000000>; + linux,cma-default; + }; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic32x4>; + audio-asrc = <&asrc>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_mba6ul_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_mba6ul_3v3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <768000000>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-cs = <1>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_mba6ul_3v3>; + phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-reset-post-delay = <1>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_mba6ul_3v3>; + phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-reset-post-delay = <1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + reg = <0>; + max-speed = <100>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + reg = <1>; + max-speed = <100>; + }; + }; +}; + +&i2c4 { + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX6UL_CLK_SAI1>; + clock-names = "mclk"; + ldoin-supply = <®_mba6ul_3v3>; + iov-supply = <®_mba6ul_3v3>; + }; + + jc42: temperature-sensor@19 { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x19>; + }; + + expander_out0: gpio-expander@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + expander_in0: gpio-expander@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander_in0>; + interrupt-parent = <&gpio4>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + enet1_int-hog { + gpio-hog; + gpios = <6 0>; + input; + }; + + enet2_int-hog { + gpio-hog; + gpios = <7 0>; + input; + }; + }; + + expander_out1: gpio-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + analog_touch: touchscreen@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio4>; + interrupt-controller; + status = "disabled"; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ + st,ave-ctrl = <3>; /* 8 sample average control */ + st,fraction-z = <7>; /* 7 length fractional part in z */ + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + st,mod-12b = <1>; /* 12-bit ADC */ + st,ref-sel = <0>; /* internal ADC reference */ + st,sample-time = <4>; /* ADC converstion time: 80 clocks */ + st,settling = <3>; /* 1 ms panel driver settling time */ + st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */ + }; + }; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97b: eeprom@51 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, + <&clks IMX6UL_CLK_SAI1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24000000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart6dte>; */ + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +/* otg-port */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + power-active-high; + over-current-active-low; + /* we implement only dual role but not a fully featured OTG */ + hnp-disable; + srp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +/* 7-port usb hub */ +/* id, pwr, oc pins not connected */ +&usbotg2 { + disable-over-current; + vbus-supply = <®_otg2vbus_5v0>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + vmmc-supply = <®_mba6ul_3v3>; + vqmmc-supply = <®_vccsd>; + no-1-8-v; + no-mmc; + no-sdio; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_buttons: buttonsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020 + MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020 + MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020 + MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 + >; + }; + + pinctrl_enet2_mdc: enet2mdcgrp { + fsl,pins = < + /* mdio */ + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_expander_in0: expanderin0grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1 + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart6dte: uart6dte { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1 + MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059 + MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0 + MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099 + >; + }; +}; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 3be7cba603d5..8e3860d5d916 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -59,7 +59,7 @@ }; uart_A: serial@84c0 { - compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson6-uart"; reg = <0x84c0 0x18>; interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; fifo-size = <128>; @@ -67,7 +67,7 @@ }; uart_B: serial@84dc { - compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson6-uart"; reg = <0x84dc 0x18>; interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; status = "disabled"; @@ -105,7 +105,7 @@ }; uart_C: serial@8700 { - compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson6-uart"; reg = <0x8700 0x18>; interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; status = "disabled"; @@ -214,21 +214,21 @@ ranges = <0x0 0xc8100000 0x100000>; ao_arc_rproc: remoteproc@1c { - compatible= "amlogic,meson-mx-ao-arc"; + compatible = "amlogic,meson-mx-ao-arc"; reg = <0x1c 0x8>, <0x38 0x8>; reg-names = "remap", "cpu"; status = "disabled"; }; ir_receiver: ir-receiver@480 { - compatible= "amlogic,meson6-ir"; + compatible = "amlogic,meson6-ir"; reg = <0x480 0x20>; interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; uart_AO: serial@4c0 { - compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart"; reg = <0x4c0 0x18>; interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; status = "disabled"; diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts index 61ec929ab86e..56ea875c418c 100644 --- a/arch/arm/boot/dts/meson8-minix-neo-x8.dts +++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts @@ -65,7 +65,7 @@ pinctrl-0 = <&spi_nor_pins>; pinctrl-names = "default"; - spi-flash@0 { + flash@0 { compatible = "mxicy,mx25l1606e"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index f80ddc98d3a2..0f8bac8bac8b 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -430,7 +430,7 @@ }; &ao_arc_rproc { - compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; + compatible = "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; amlogic,secbus2 = <&secbus2>; sram = <&ao_arc_sram>; resets = <&reset RESET_MEDIA_CPU>; @@ -736,27 +736,27 @@ }; &uart_AO { - compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart"; + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &uart_A { - compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &uart_B { - compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &uart_C { - compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &usb0 { diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index b49b7cbaed4e..cf9c04a61ba3 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -384,7 +384,7 @@ }; &ao_arc_rproc { - compatible= "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc"; + compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc"; amlogic,secbus2 = <&secbus2>; sram = <&ao_arc_sram>; resets = <&reset RESET_MEDIA_CPU>; @@ -724,27 +724,27 @@ }; &uart_AO { - compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart"; + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &uart_A { - compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8b-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &uart_B { - compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8b-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &uart_C { - compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; - clock-names = "baud", "xtal", "pclk"; + compatible = "amlogic,meson8b-uart"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk", "baud"; }; &usb0 { diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 46984d4c5224..987d792f67ea 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -275,7 +275,9 @@ compatible = "marvell,pdma-1.0"; reg = <0xd4000000 0x10000>; interrupts = <48>; + /* For backwards compatibility: */ #dma-channels = <16>; + dma-channels = <16>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxart-uc7112lx.dts index eb5291b0ee3a..e07b807b4cec 100644 --- a/arch/arm/boot/dts/moxart-uc7112lx.dts +++ b/arch/arm/boot/dts/moxart-uc7112lx.dts @@ -79,7 +79,7 @@ clocks = <&ref12>; }; -&sdhci { +&mmc { status = "okay"; }; diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi index f5f070a87482..764832ddfa78 100644 --- a/arch/arm/boot/dts/moxart.dtsi +++ b/arch/arm/boot/dts/moxart.dtsi @@ -93,8 +93,8 @@ clock-names = "PCLK"; }; - sdhci: sdhci@98e00000 { - compatible = "moxa,moxart-sdhci"; + mmc: mmc@98e00000 { + compatible = "moxa,moxart-mmc"; reg = <0x98e00000 0x5C>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_apb>; diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/mstar-infinity.dtsi index 0bee517797f4..441a917b88ba 100644 --- a/arch/arm/boot/dts/mstar-infinity.dtsi +++ b/arch/arm/boot/dts/mstar-infinity.dtsi @@ -8,6 +8,40 @@ #include <dt-bindings/gpio/msc313-gpio.h> +/ { + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; +}; + &imi { reg = <0xa0000000 0x16000>; }; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi new file mode 100644 index 000000000000..34df472fed71 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + * Author: Romain Perier <romain.perier@gmail.com> + */ + +/ { + reg_vcc_dram: regulator-vcc-dram { + compatible = "regulator-fixed"; + regulator-name = "vcc_dram"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts new file mode 100644 index 000000000000..f25a04c98ccb --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" + +/ { + model = "DongShanPi One"; + compatible = "100ask,dongshanpione", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts new file mode 100644 index 000000000000..1bbbf47132dc --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" + +/ { + model = "Miyoo Mini"; + compatible = "miyoo,miyoo-mini", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts new file mode 100644 index 000000000000..b15c40762bc0 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + * Author: Romain Perier <romain.perier@gmail.com> + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Wireless Tag IDO-SBC2D06-1VB-22W"; + compatible = "wirelesstag,ido-sbc2d06-v1b-22w", "mstar,infinity2m"; + + leds { + compatible = "gpio-leds"; + sys_led { + gpios = <&gpio SSD20XD_GPIO_GPIO85 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi new file mode 100644 index 000000000000..d877aff85033 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + * Author: Romain Perier <romain.perier@gmail.com> + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" +#include "mstar-infinity2m-ssd201-som2d01.dtsi" + +/ { + model = "Wireless Tag IDO-SOM2D01 (SSD202D)"; + compatible = "wirelesstag,ido-som2d01", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +®_vcc_dram { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; +}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi index 7a5e28b33f96..6f067da61ba3 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi @@ -6,6 +6,11 @@ #include "mstar-infinity2m.dtsi" +&gpio { + compatible = "sstar,ssd20xd-gpio"; + status = "okay"; +}; + &smpctrl { compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; status = "okay"; diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi index 6d4d1d224e96..1b485efd7156 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -6,11 +6,28 @@ #include "mstar-infinity.dtsi" +&cpu0_opp_table { + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; +}; + &cpus { cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; + operating-points-v2 = <&cpu0_opp_table>; reg = <0x1>; + clocks = <&cpupll>; + clock-names = "cpuclk"; }; }; diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/mstar-infinity3.dtsi index 9857e2a9934d..a56cf29e5d82 100644 --- a/arch/arm/boot/dts/mstar-infinity3.dtsi +++ b/arch/arm/boot/dts/mstar-infinity3.dtsi @@ -6,6 +6,64 @@ #include "mstar-infinity.dtsi" +&cpu0_opp_table { + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + // overclock frequencies below, shown to work fine up to 1.3 GHz + opp-108000000 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1188000000 { + opp-hz = /bits/ 64 <1188000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1404000000 { + opp-hz = /bits/ 64 <1404000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1458000000 { + opp-hz = /bits/ 64 <1458000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; +}; + &imi { reg = <0xa0000000 0x20000>; }; diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 89ebfe4f29da..c26ba9b7b6dd 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -21,6 +21,8 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; + clocks = <&cpupll>; + clock-names = "cpuclk"; }; }; @@ -155,6 +157,13 @@ clocks = <&xtal>; }; + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <0>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; + gpio: gpio@207800 { #gpio-cells = <2>; reg = <0x207800 0x200>; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 4776f85d6d5b..b8eba3ba153c 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -427,9 +427,9 @@ afe: audio-controller { compatible = "mediatek,mt2701-audio"; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "afe", "asys"; + interrupt-names = "afe", "asys"; power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; clocks = <&infracfg CLK_INFRA_AUDIO>, @@ -559,12 +559,11 @@ compatible = "mediatek,mt2701-jpgdec"; reg = <0 0x15004000 0 0x1000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; - clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, <&imgsys CLK_IMG_JPGDEC>; clock-names = "jpgdec-smi", "jpgdec"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; }; @@ -574,10 +573,9 @@ "mediatek,mtk-jpgenc"; reg = <0 0x1500a000 0 0x1000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>; - clocks = <&imgsys CLK_IMG_VENC>; + clocks = <&imgsys CLK_IMG_VENC>; clock-names = "jpgenc"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; }; diff --git a/arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts b/arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts new file mode 100644 index 000000000000..b057e037f940 --- /dev/null +++ b/arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Maxim Kutnij <gtk3@inbox.ru> + */ + +/dts-v1/; +#include "mt6582.dtsi" + +/ { + model = "Prestigio PMT5008 3G"; + compatible = "prestigio,pmt5008-3g", "mediatek,mt6582"; + + aliases { + bootargs = "console=ttyS0,921600n8 earlyprintk"; + serial0 = &uart0; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mt6582.dtsi b/arch/arm/boot/dts/mt6582.dtsi new file mode 100644 index 000000000000..4263371784cd --- /dev/null +++ b/arch/arm/boot/dts/mt6582.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Maxim Kutnij <gtk3@inbox.ru> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt6582"; + interrupt-parent = <&sysirq>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer: timer@11008000 { + compatible = "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt6582-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200100 0x1c>; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, + <0x10212000 0x2000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6582-uart", + "mediatek,mt6577-uart"; + reg = <0x11002000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6582-uart", + "mediatek,mt6577-uart"; + reg = <0x11003000 0x400>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6582-uart", + "mediatek,mt6577-uart"; + reg = <0x11004000 0x400>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt6582-uart", + "mediatek,mt6577-uart"; + reg = <0x11005000 0x400>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt6582-wdt", + "mediatek,mt6589-wdt"; + reg = <0x10007000 0x100>; + }; +}; diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index f4848362b3be..25d31e40a553 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -241,7 +241,7 @@ }; pericfg: syscon@10003000 { - compatible = "mediatek,mt7623-pericfg", + compatible = "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"; reg = <0 0x10003000 0 0x1000>; @@ -628,9 +628,9 @@ afe: audio-controller { compatible = "mediatek,mt7623-audio", "mediatek,mt2701-audio"; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "afe", "asys"; + interrupt-names = "afe", "asys"; power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; clocks = <&infracfg CLK_INFRA_AUDIO>, diff --git a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts index 13c86936d1c8..e8b4b6d30d19 100644 --- a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts @@ -45,13 +45,13 @@ pinctrl-names = "default"; pinctrl-0 = <&key_pins_a>; - factory { + button-factory { label = "factory"; linux,code = <BTN_0>; gpios = <&pio 256 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&pio 257 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/mt7623a-rfb-nand.dts b/arch/arm/boot/dts/mt7623a-rfb-nand.dts index 88d8f0b2f4c2..61f5da68d4b0 100644 --- a/arch/arm/boot/dts/mt7623a-rfb-nand.dts +++ b/arch/arm/boot/dts/mt7623a-rfb-nand.dts @@ -45,13 +45,13 @@ pinctrl-names = "default"; pinctrl-0 = <&key_pins_a>; - factory { + button-factory { label = "factory"; linux,code = <BTN_0>; gpios = <&pio 256 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&pio 257 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 027c1b0c6a98..5008115d2494 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -91,13 +91,13 @@ pinctrl-names = "default"; pinctrl-0 = <&key_pins_a>; - factory { + button-factory { label = "factory"; linux,code = <BTN_0>; gpios = <&pio 256 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&pio 257 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index 1b9b9a8145a7..bf67a8e9be59 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -60,13 +60,13 @@ pinctrl-names = "default"; pinctrl-0 = <&key_pins_a>; - factory { + button-factory { label = "factory"; linux,code = <BTN_0>; gpios = <&pio 256 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&pio 257 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi index bcb0846e29fd..3adab5cd1fef 100644 --- a/arch/arm/boot/dts/mt7623n.dtsi +++ b/arch/arm/boot/dts/mt7623n.dtsi @@ -121,7 +121,6 @@ clock-names = "jpgdec-smi", "jpgdec"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; }; @@ -144,7 +143,6 @@ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>; clocks = <&mmsys CLK_MM_DISP_OVL>; iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; - mediatek,larb = <&larb0>; }; rdma0: rdma@14008000 { @@ -154,7 +152,6 @@ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; clocks = <&mmsys CLK_MM_DISP_RDMA>; iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; - mediatek,larb = <&larb0>; }; wdma@14009000 { @@ -164,7 +161,6 @@ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; clocks = <&mmsys CLK_MM_DISP_WDMA>; iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; - mediatek,larb = <&larb0>; }; bls: pwm@1400a000 { @@ -215,7 +211,6 @@ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; - mediatek,larb = <&larb0>; }; dpi0: dpi@14014000 { diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts index eb536cbebd9b..84e14bee7235 100644 --- a/arch/arm/boot/dts/mt7629-rfb.dts +++ b/arch/arm/boot/dts/mt7629-rfb.dts @@ -23,13 +23,13 @@ gpio-keys { compatible = "gpio-keys"; - reset { + button-reset { label = "factory"; linux,code = <KEY_RESTART>; gpios = <&pio 60 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&pio 58 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/mxs-pinfunc.h b/arch/arm/boot/dts/mxs-pinfunc.h index c6da987b20cb..31297abcbc71 100644 --- a/arch/arm/boot/dts/mxs-pinfunc.h +++ b/arch/arm/boot/dts/mxs-pinfunc.h @@ -1,14 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Header providing constants for i.MX28 pinctrl bindings. * * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #ifndef __DT_BINDINGS_MXS_PINCTRL_H__ diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi index 41744cc2bc72..01e1bb7c3c6c 100644 --- a/arch/arm/boot/dts/nspire-classic.dtsi +++ b/arch/arm/boot/dts/nspire-classic.dtsi @@ -17,7 +17,7 @@ &fast_timer { /* compatible = "lsi,zevio-timer"; */ - reg = <0x90010000 0x1000>, <0x900A0010 0x8>; + reg = <0x90010000 0x1000>, <0x900a0010 0x8>; }; &uart { @@ -30,12 +30,12 @@ &timer0 { /* compatible = "lsi,zevio-timer"; */ - reg = <0x900C0000 0x1000>, <0x900A0018 0x8>; + reg = <0x900c0000 0x1000>, <0x900a0018 0x8>; }; &timer1 { compatible = "lsi,zevio-timer"; - reg = <0x900D0000 0x1000>, <0x900A0020 0x8>; + reg = <0x900d0000 0x1000>, <0x900a0020 0x8>; }; &keypad { @@ -66,10 +66,10 @@ #address-cells = <1>; #size-cells = <1>; - intc: interrupt-controller@DC000000 { + intc: interrupt-controller@dc000000 { compatible = "lsi,zevio-intc"; interrupt-controller; - reg = <0xDC000000 0x1000>; + reg = <0xdc000000 0x1000>; #interrupt-cells = <1>; }; }; diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts index 0c16b04e2744..590b7dff6ae5 100644 --- a/arch/arm/boot/dts/nspire-cx.dts +++ b/arch/arm/boot/dts/nspire-cx.dts @@ -92,10 +92,10 @@ #address-cells = <1>; #size-cells = <1>; - intc: interrupt-controller@DC000000 { + intc: interrupt-controller@dc000000 { compatible = "arm,pl190-vic"; interrupt-controller; - reg = <0xDC000000 0x1000>; + reg = <0xdc000000 0x1000>; #interrupt-cells = <1>; }; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index 90e033d9141f..bb240e6a3a6f 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -20,9 +20,9 @@ reg = <0x00000000 0x80000>; }; - sram: sram@A4000000 { + sram: sram@a4000000 { device = "memory"; - reg = <0xA4000000 0x20000>; + reg = <0xa4000000 0x20000>; }; timer_clk: timer_clk { @@ -33,12 +33,12 @@ base_clk: base_clk { #clock-cells = <0>; - reg = <0x900B0024 0x4>; + reg = <0x900b0024 0x4>; }; ahb_clk: ahb_clk { #clock-cells = <0>; - reg = <0x900B0024 0x4>; + reg = <0x900b0024 0x4>; clocks = <&base_clk>; }; @@ -71,28 +71,28 @@ #size-cells = <1>; ranges; - spi: spi@A9000000 { - reg = <0xA9000000 0x1000>; + spi: spi@a9000000 { + reg = <0xa9000000 0x1000>; }; - usb0: usb@B0000000 { + usb0: usb@b0000000 { compatible = "lsi,zevio-usb"; - reg = <0xB0000000 0x1000>; + reg = <0xb0000000 0x1000>; interrupts = <8>; usb-phy = <&usb_phy>; vbus-supply = <&vbus_reg>; }; - usb1: usb@B4000000 { - reg = <0xB4000000 0x1000>; + usb1: usb@b4000000 { + reg = <0xb4000000 0x1000>; interrupts = <9>; status = "disabled"; }; - lcd: lcd@C0000000 { + lcd: lcd@c0000000 { compatible = "arm,pl111", "arm,primecell"; - reg = <0xC0000000 0x1000>; + reg = <0xc0000000 0x1000>; interrupts = <21>; /* @@ -105,17 +105,17 @@ clock-names = "clcdclk", "apb_pclk"; }; - adc: adc@C4000000 { - reg = <0xC4000000 0x1000>; + adc: adc@c4000000 { + reg = <0xc4000000 0x1000>; interrupts = <11>; }; - tdes: crypto@C8010000 { - reg = <0xC8010000 0x1000>; + tdes: crypto@c8010000 { + reg = <0xc8010000 0x1000>; }; - sha256: crypto@CC000000 { - reg = <0xCC000000 0x1000>; + sha256: crypto@cc000000 { + reg = <0xcc000000 0x1000>; }; apb@90000000 { @@ -143,16 +143,16 @@ interrupts = <1>; }; - timer0: timer@900C0000 { - reg = <0x900C0000 0x1000>; + timer0: timer@900c0000 { + reg = <0x900c0000 0x1000>; clocks = <&timer_clk>, <&timer_clk>, <&timer_clk>; clock-names = "timer0clk", "timer1clk", "apb_pclk"; }; - timer1: timer@900D0000 { - reg = <0x900D0000 0x1000>; + timer1: timer@900d0000 { + reg = <0x900d0000 0x1000>; interrupts = <19>; clocks = <&timer_clk>, <&timer_clk>, <&timer_clk>; @@ -171,18 +171,18 @@ interrupts = <4>; }; - misc: misc@900A0000 { - reg = <0x900A0000 0x1000>; + misc: misc@900a0000 { + reg = <0x900a0000 0x1000>; }; - pwr: pwr@900B0000 { - reg = <0x900B0000 0x1000>; + pwr: pwr@900b0000 { + reg = <0x900b0000 0x1000>; interrupts = <15>; }; - keypad: input@900E0000 { + keypad: input@900e0000 { compatible = "ti,nspire-keypad"; - reg = <0x900E0000 0x1000>; + reg = <0x900e0000 0x1000>; interrupts = <16>; scan-interval = <1000>; @@ -191,8 +191,8 @@ clocks = <&apb_pclk>; }; - contrast: contrast@900F0000 { - reg = <0x900F0000 0x1000>; + contrast: contrast@900f0000 { + reg = <0x900f0000 0x1000>; }; led: led@90110000 { diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index 3696980a3da1..c7b5ef15b716 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -110,6 +110,7 @@ compatible = "nuvoton,npcm750-reset"; reg = <0xf0801000 0x70>; #reset-cells = <2>; + nuvoton,sysgcr = <&gcr>; }; clk: clock-controller@f0801000 { @@ -128,7 +129,7 @@ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; ethernet = <0>; - clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; clock-names = "stmmaceth", "clk_gmac"; pinctrl-names = "default"; pinctrl-0 = <&rg1_pins diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts b/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts index eb6eb21cb2a4..d10669fcd527 100644 --- a/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts +++ b/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts @@ -358,7 +358,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0cs1_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -406,7 +406,7 @@ pinctrl-0 = <&spi3_pins>, <&spi3cs1_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -416,7 +416,7 @@ m25p,fast-read; label = "pnor"; }; - spi-nor@1 { + flash@1 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts index d4ff49939a3d..491606c4f044 100644 --- a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts +++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts @@ -135,7 +135,7 @@ pinctrl-0 = <&spi0cs1_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts index 82a104b2a65f..a0c2d7652625 100644 --- a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts +++ b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts @@ -380,7 +380,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0cs1_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -415,7 +415,7 @@ }; }; }; - spi-nor@1 { + flash@1 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -440,7 +440,7 @@ &fiu3 { pinctrl-0 = <&spi3_pins>; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts index 0334641f8829..3dad32834e5e 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts @@ -67,7 +67,7 @@ &fiu0 { status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -128,7 +128,7 @@ &fiu3 { pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -324,7 +324,7 @@ &spi0 { cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; status = "okay"; - Flash@0 { + flash@0 { compatible = "winbond,w25q128", "jedec,spi-nor"; reg = <0x0>; @@ -345,7 +345,7 @@ &spi1 { cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; status = "okay"; - Flash@0 { + flash@0 { compatible = "winbond,w25q128fw", "jedec,spi-nor"; reg = <0x0>; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts index 767e0ac0df7c..132e702281fc 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts +++ b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts @@ -100,7 +100,7 @@ pinctrl-0 = <&spi0cs1_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -139,7 +139,7 @@ }; }; - spi-nor@1 { + flash@1 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -166,7 +166,7 @@ pinctrl-0 = <&spi3_pins>; status = "okay"; - spi-nor@0 { + flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi index 13eee0fe5642..30eed40b89b5 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -51,7 +51,7 @@ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; ethernet = <1>; - clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; + clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; clock-names = "stmmaceth", "clk_gmac"; pinctrl-names = "default"; pinctrl-0 = <&rg2_pins diff --git a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts index 83f27fbf4e93..3ee61251a16d 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts +++ b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts @@ -8,6 +8,9 @@ #include "nuvoton-wpcm450.dtsi" +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/gpio/gpio.h> + / { model = "Supermicro X9SCi-LN4F BMC"; compatible = "supermicro,x9sci-ln4f-bmc", "nuvoton,wpcm450"; @@ -20,6 +23,46 @@ device_type = "memory"; reg = <0 0x08000000>; /* 128 MiB */ }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins>; + + uid { + label = "UID button"; + linux,code = <KEY_HOME>; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + uid { + label = "UID"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + heartbeat { + label = "heartbeat"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pinctrl { + key_pins: mux-keys { + groups = "gspi", "sspi"; + function = "gpio"; + }; + + led_pins: mux-leds { + groups = "hg3", "hg0", "pwm4"; + function = "gpio"; + }; }; &serial0 { diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index d7cbeb187484..93595850a4c3 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -8,6 +8,17 @@ #address-cells = <1>; #size-cells = <1>; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -33,12 +44,19 @@ interrupt-parent = <&aic>; ranges; + gcr: syscon@b0000000 { + compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd"; + reg = <0xb0000000 0x200>; + }; + serial0: serial@b8000000 { compatible = "nuvoton,wpcm450-uart"; reg = <0xb8000000 0x20>; reg-shift = <2>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk24m>; + pinctrl-names = "default"; + pinctrl-0 = <&bsp_pins>; status = "disabled"; }; @@ -72,5 +90,371 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0: gpio@0 { + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>, + <4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + + gpio1: gpio@1 { + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + + gpio2: gpio@2 { + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@3 { + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio4: gpio@4 { + reg = <4>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio5: gpio@5 { + reg = <5>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio6: gpio@6 { + reg = <6>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio7: gpio@7 { + reg = <7>; + gpio-controller; + #gpio-cells = <2>; + }; + + smb3_pins: mux-smb3 { + groups = "smb3"; + function = "smb3"; + }; + + smb4_pins: mux-smb4 { + groups = "smb4"; + function = "smb4"; + }; + + smb5_pins: mux-smb5 { + groups = "smb5"; + function = "smb5"; + }; + + scs1_pins: mux-scs1 { + groups = "scs1"; + function = "scs1"; + }; + + scs2_pins: mux-scs2 { + groups = "scs2"; + function = "scs2"; + }; + + scs3_pins: mux-scs3 { + groups = "scs3"; + function = "scs3"; + }; + + smb0_pins: mux-smb0 { + groups = "smb0"; + function = "smb0"; + }; + + smb1_pins: mux-smb1 { + groups = "smb1"; + function = "smb1"; + }; + + smb2_pins: mux-smb2 { + groups = "smb2"; + function = "smb2"; + }; + + bsp_pins: mux-bsp { + groups = "bsp"; + function = "bsp"; + }; + + hsp1_pins: mux-hsp1 { + groups = "hsp1"; + function = "hsp1"; + }; + + hsp2_pins: mux-hsp2 { + groups = "hsp2"; + function = "hsp2"; + }; + + r1err_pins: mux-r1err { + groups = "r1err"; + function = "r1err"; + }; + + r1md_pins: mux-r1md { + groups = "r1md"; + function = "r1md"; + }; + + rmii2_pins: mux-rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + r2err_pins: mux-r2err { + groups = "r2err"; + function = "r2err"; + }; + + r2md_pins: mux-r2md { + groups = "r2md"; + function = "r2md"; + }; + + kbcc_pins: mux-kbcc { + groups = "kbcc"; + function = "kbcc"; + }; + + dvo0_pins: mux-dvo0 { + groups = "dvo"; + function = "dvo0"; + }; + + dvo3_pins: mux-dvo3 { + groups = "dvo"; + function = "dvo3"; + }; + + clko_pins: mux-clko { + groups = "clko"; + function = "clko"; + }; + + smi_pins: mux-smi { + groups = "smi"; + function = "smi"; + }; + + uinc_pins: mux-uinc { + groups = "uinc"; + function = "uinc"; + }; + + gspi_pins: mux-gspi { + groups = "gspi"; + function = "gspi"; + }; + + mben_pins: mux-mben { + groups = "mben"; + function = "mben"; + }; + + xcs2_pins: mux-xcs2 { + groups = "xcs2"; + function = "xcs2"; + }; + + xcs1_pins: mux-xcs1 { + groups = "xcs1"; + function = "xcs1"; + }; + + sdio_pins: mux-sdio { + groups = "sdio"; + function = "sdio"; + }; + + sspi_pins: mux-sspi { + groups = "sspi"; + function = "sspi"; + }; + + fi0_pins: mux-fi0 { + groups = "fi0"; + function = "fi0"; + }; + + fi1_pins: mux-fi1 { + groups = "fi1"; + function = "fi1"; + }; + + fi2_pins: mux-fi2 { + groups = "fi2"; + function = "fi2"; + }; + + fi3_pins: mux-fi3 { + groups = "fi3"; + function = "fi3"; + }; + + fi4_pins: mux-fi4 { + groups = "fi4"; + function = "fi4"; + }; + + fi5_pins: mux-fi5 { + groups = "fi5"; + function = "fi5"; + }; + + fi6_pins: mux-fi6 { + groups = "fi6"; + function = "fi6"; + }; + + fi7_pins: mux-fi7 { + groups = "fi7"; + function = "fi7"; + }; + + fi8_pins: mux-fi8 { + groups = "fi8"; + function = "fi8"; + }; + + fi9_pins: mux-fi9 { + groups = "fi9"; + function = "fi9"; + }; + + fi10_pins: mux-fi10 { + groups = "fi10"; + function = "fi10"; + }; + + fi11_pins: mux-fi11 { + groups = "fi11"; + function = "fi11"; + }; + + fi12_pins: mux-fi12 { + groups = "fi12"; + function = "fi12"; + }; + + fi13_pins: mux-fi13 { + groups = "fi13"; + function = "fi13"; + }; + + fi14_pins: mux-fi14 { + groups = "fi14"; + function = "fi14"; + }; + + fi15_pins: mux-fi15 { + groups = "fi15"; + function = "fi15"; + }; + + pwm0_pins: mux-pwm0 { + groups = "pwm0"; + function = "pwm0"; + }; + + pwm1_pins: mux-pwm1 { + groups = "pwm1"; + function = "pwm1"; + }; + + pwm2_pins: mux-pwm2 { + groups = "pwm2"; + function = "pwm2"; + }; + + pwm3_pins: mux-pwm3 { + groups = "pwm3"; + function = "pwm3"; + }; + + pwm4_pins: mux-pwm4 { + groups = "pwm4"; + function = "pwm4"; + }; + + pwm5_pins: mux-pwm5 { + groups = "pwm5"; + function = "pwm5"; + }; + + pwm6_pins: mux-pwm6 { + groups = "pwm6"; + function = "pwm6"; + }; + + pwm7_pins: mux-pwm7 { + groups = "pwm7"; + function = "pwm7"; + }; + + hg0_pins: mux-hg0 { + groups = "hg0"; + function = "hg0"; + }; + + hg1_pins: mux-hg1 { + groups = "hg1"; + function = "hg1"; + }; + + hg2_pins: mux-hg2 { + groups = "hg2"; + function = "hg2"; + }; + + hg3_pins: mux-hg3 { + groups = "hg3"; + function = "hg3"; + }; + + hg4_pins: mux-hg4 { + groups = "hg4"; + function = "hg4"; + }; + + hg5_pins: mux-hg5 { + groups = "hg5"; + function = "hg5"; + }; + + hg6_pins: mux-hg6 { + groups = "hg6"; + function = "hg6"; + }; + + hg7_pins: mux-hg7 { + groups = "hg7"; + function = "hg7"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index 5750ca1233cc..afabb36a8ac1 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP2 SoC * * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h> diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts index af964f139abf..5acf5dd87c59 100644 --- a/arch/arm/boot/dts/omap2420-h4.dts +++ b/arch/arm/boot/dts/omap2420-h4.dts @@ -21,7 +21,7 @@ nor@0,0 { compatible = "cfi-flash"; - linux,mtd-name= "intel,ge28f256l18b85"; + linux,mtd-name = "intel,ge28f256l18b85"; #address-cells = <1>; #size-cells = <1>; reg = <0 0 0x04000000>; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index bb529a2a295d..821da51cb870 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP2420 SoC * * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "omap2.dtsi" diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 23115ba61bc0..b9a9e6e45266 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP243x SoC * * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "omap2.dtsi" diff --git a/arch/arm/boot/dts/omap3-beagle-ab4.dts b/arch/arm/boot/dts/omap3-beagle-ab4.dts new file mode 100644 index 000000000000..990ff2d84686 --- /dev/null +++ b/arch/arm/boot/dts/omap3-beagle-ab4.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include "omap3-beagle.dts" + +/ { + model = "TI OMAP3 BeagleBoard A to B4"; + compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3"; +}; + +/* + * Workaround for capacitor C70 issue, see "Boards revision A and < B5" + * section at https://elinux.org/BeagleBoard_Community + */ + +/* Unusable as clocksource because of unreliable oscillator */ +&counter32k { + status = "disabled"; +}; + +/* Unusable as clockevent because of unreliable oscillator, allow to idle */ +&timer1_target { + /delete-property/ti,no-reset-on-init; + /delete-property/ti,no-idle; + timer@0 { + /delete-property/ti,timer-alwon; + }; +}; + +/* Preferred always-on timer for clocksource */ +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + /* Always clocked by secure_32k_fck */ + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index a858ebfa1500..35eced6521ef 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -370,7 +370,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index f9f34b8458e9..0548b391334f 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -304,39 +304,6 @@ phys = <0 &hsusb2_phy>; }; -/* Unusable as clocksource because of unreliable oscillator */ -&counter32k { - status = "disabled"; -}; - -/* Unusable as clockevent because if unreliable oscillator, allow to idle */ -&timer1_target { - /delete-property/ti,no-reset-on-init; - /delete-property/ti,no-idle; - timer@0 { - /delete-property/ti,timer-alwon; - }; -}; - -/* Preferred always-on timer for clocksource */ -&timer12_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - /* Always clocked by secure_32k_fck */ - }; -}; - -/* Preferred timer for clockevent */ -&timer2_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&gpt2_fck>; - assigned-clock-parents = <&sys_ck>; - }; -}; - &twl_gpio { ti,use-leds; /* pullups: BIT(1) */ diff --git a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi index a9069cca5888..0da759f8e2c2 100644 --- a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi +++ b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP3 SoC CPU thermal * * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi index 5e55198e4576..54cd37336be7 100644 --- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi @@ -158,6 +158,24 @@ status = "disabled"; }; +/* Unusable as clockevent because if unreliable oscillator, allow to idle */ +&timer1_target { + /delete-property/ti,no-reset-on-init; + /delete-property/ti,no-idle; + timer@0 { + /delete-property/ti,timer-alwon; + }; +}; + +/* Preferred timer for clockevent */ +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + /* Always clocked by secure_32k_fck */ + }; +}; + &twl_gpio { ti,use-leds; /* diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index c2995a280729..162d0726b008 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts @@ -14,36 +14,3 @@ display2 = &tv0; }; }; - -/* Unusable as clocksource because of unreliable oscillator */ -&counter32k { - status = "disabled"; -}; - -/* Unusable as clockevent because if unreliable oscillator, allow to idle */ -&timer1_target { - /delete-property/ti,no-reset-on-init; - /delete-property/ti,no-idle; - timer@0 { - /delete-property/ti,timer-alwon; - }; -}; - -/* Preferred always-on timer for clocksource */ -&timer12_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - /* Always clocked by secure_32k_fck */ - }; -}; - -/* Preferred timer for clockevent */ -&timer2_target { - ti,no-reset-on-init; - ti,no-idle; - timer@0 { - assigned-clocks = <&gpt2_fck>; - assigned-clock-parents = <&sys_ck>; - }; -}; diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index c9332195d096..abd403c228c7 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -60,7 +60,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "hynix,h8kds0un0mer-4em"; + linux,mtd-name = "hynix,h8kds0un0mer-4em"; nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index 5cc0cf7cd16c..f95eea63b355 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -60,7 +60,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f2g16abdhc"; + linux,mtd-name = "micron,mt29f2g16abdhc"; nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 7e3d8147e2c1..28a6a9345be5 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -31,6 +31,8 @@ aliases { display0 = &lcd; display1 = &tv0; + /delete-property/ mmc2; + /delete-property/ mmc3; }; ldo_3v3: fixedregulator { @@ -125,7 +127,7 @@ spi-cpol; spi-cpha; - backlight= <&backlight>; + backlight = <&backlight>; label = "lcd"; port { lcd_in: endpoint { diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index 99f5585097a1..219202610463 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -111,7 +111,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29c4g96maz"; + linux,mtd-name = "micron,mt29c4g96maz"; nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts index 9c6a92724590..36fc8805e0c1 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/omap3-ldp.dts @@ -103,7 +103,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,nand"; + linux,mtd-name = "micron,nand"; nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; @@ -215,11 +215,11 @@ }; &mmc2 { - status="disabled"; + status = "disabled"; }; &mmc3 { - status="disabled"; + status = "disabled"; }; &omap3_pmx_core { diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index 73d477898ec2..c595afe4181d 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -372,7 +372,7 @@ gpmc,device-width = <2>; gpmc,wait-pin = <0>; gpmc,wait-monitoring-ns = <0>; - gpmc,burst-length= <4>; + gpmc,burst-length = <4>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <100>; gpmc,cs-wr-off-ns = <100>; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 32335d4ce478..dd7971556449 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -8,6 +8,7 @@ #include "omap34xx.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> /* * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall @@ -567,8 +568,8 @@ }; &twl_gpio { - ti,pullups = <0x0>; - ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ + ti,pullups = <0x0>; + ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ }; &i2c2 { @@ -630,63 +631,92 @@ }; lp5523: lp5523@32 { + #address-cells = <1>; + #size-cells = <0>; compatible = "national,lp5523"; reg = <0x32>; clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ + enable-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */ - chan0 { + led@0 { + reg = <0>; chan-name = "lp5523:kb1"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_KBD_BACKLIGHT; }; - chan1 { + led@1 { + reg = <1>; chan-name = "lp5523:kb2"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_KBD_BACKLIGHT; }; - chan2 { + led@2 { + reg = <2>; chan-name = "lp5523:kb3"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_KBD_BACKLIGHT; }; - chan3 { + led@3 { + reg = <3>; chan-name = "lp5523:kb4"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_KBD_BACKLIGHT; }; - chan4 { + led@4 { + reg = <4>; chan-name = "lp5523:b"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; }; - chan5 { + led@5 { + reg = <5>; chan-name = "lp5523:g"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; }; - chan6 { + led@6 { + reg = <6>; chan-name = "lp5523:r"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_STATUS; }; - chan7 { + led@7 { + reg = <7>; chan-name = "lp5523:kb5"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_KBD_BACKLIGHT; }; - chan8 { + led@8 { + reg = <8>; chan-name = "lp5523:kb6"; led-cur = /bits/ 8 <50>; max-cur = /bits/ 8 <100>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_KBD_BACKLIGHT; }; }; diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 7dde9fbb06d3..f68da828b050 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -162,8 +162,8 @@ }; &twl_gpio { - ti,pullups = <0x000001>; /* BIT(0) */ - ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ + ti,pullups = <0x000001>; /* BIT(0) */ + ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ }; &vdac { diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index 006a6d97231c..adc714c39825 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -222,7 +222,7 @@ nand@0,0 { compatible = "ti,omap2-nand"; - linux,mtd-name= "micron,mt29c4g96maz"; + linux,mtd-name = "micron,mt29c4g96maz"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi index 37608af6c07f..559853764487 100644 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -666,7 +666,7 @@ lcd: lcd@1 { reg = <1>; /* CS1 */ - compatible = "tpo,td043mtea1"; + compatible = "tpo,td043mtea1"; spi-max-frequency = <100000>; spi-cpol; spi-cpha; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 64b7e6fddd1b..825075ff0e34 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP3 SoC * * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h> diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index 7d530ae3483b..258ecd9e4519 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts @@ -53,7 +53,7 @@ nor@0,0 { compatible = "cfi-flash"; - linux,mtd-name= "intel,pf48f6000m0y1be"; + linux,mtd-name = "intel,pf48f6000m0y1be"; #address-cells = <1>; #size-cells = <1>; reg = <0 0 0x08000000>; @@ -105,7 +105,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f1g08abb"; + linux,mtd-name = "micron,mt29f1g08abb"; #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "sw"; @@ -148,7 +148,7 @@ }; onenand@2,0 { - linux,mtd-name= "samsung,kfm2g16q2m-deb8"; + linux,mtd-name = "samsung,kfm2g16q2m-deb8"; #address-cells = <1>; #size-cells = <1>; compatible = "ti,omap2-onenand"; diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 2ec3628d3315..24adfac26be0 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -46,37 +46,61 @@ ti,bit-shift = <2>; }; - d2d_26m_fck: d2d_26m_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0a00>; - ti,bit-shift = <3>; - }; - - fshostusb_fck: fshostusb_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <5>; - }; - - ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - reg = <0x0a00>; - }; - - ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + d2d_26m_fck: clock-d2d-26m-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "d2d_26m_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + }; + + fshostusb_fck: clock-fshostusb-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "fshostusb_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <5>; + }; + + ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "ssi_ssr_gate_fck_3430es1"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + }; + }; + + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "ssi_ssr_div_fck_3430es1"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; + + usb_l4_div_ick: clock-usb-l4-div-ick { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "usb_l4_div_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <4>; + ti,max-div = <1>; + ti,index-starts-at-one; + }; }; ssi_ssr_fck: ssi_ssr_fck_3430es1 { @@ -93,20 +117,43 @@ clock-div = <2>; }; - hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; - }; - - fac_ick: fac_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <8>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clock-output-names = "hsotgusb_ick_3430es1"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + fac_ick: clock-fac-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "fac_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <8>; + }; + + ssi_ick: clock-ssi-ick-3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clock-output-names = "ssi_ick_3430es1"; + clocks = <&ssi_l4_ick>; + ti,bit-shift = <0>; + }; + + usb_l4_gate_ick: clock-usb-l4-gate-ick { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clock-output-names = "usb_l4_gate_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <5>; + }; }; ssi_l4_ick: ssi_l4_ick { @@ -117,45 +164,26 @@ clock-div = <1>; }; - ssi_ick: ssi_ick_3430es1@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <0>; - }; - - usb_l4_gate_ick: usb_l4_gate_ick@a10 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <5>; - reg = <0x0a10>; - }; - - usb_l4_div_ick: usb_l4_div_ick@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <4>; - ti,max-div = <1>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - usb_l4_ick: usb_l4_ick { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; }; - dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - reg = <0x0e00>; - ti,set-rate-parent; + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss1_alwon_fck_3430es1"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; }; dss_ick: dss_ick_3430es1@e10 { diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index 21079cdf2663..8374532f20e2 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -13,45 +13,76 @@ clock-div = <1>; }; - aes1_ick: aes1_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - ti,bit-shift = <3>; - reg = <0x0a14>; - }; + clock@a14 { + compatible = "ti,clksel"; + reg = <0xa14>; + #clock-cells = <2>; + #address-cells = <0>; - rng_ick: rng_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <2>; - }; + aes1_ick: clock-aes1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "aes1_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <3>; + }; - sha11_ick: sha11_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <1>; - }; + rng_ick: clock-rng-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "rng_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <2>; + }; - des1_ick: des1_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <0>; + sha11_ick: clock-sha11-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sha11_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <1>; + }; + + des1_ick: clock-des1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "des1_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <0>; + }; + + pka_ick: clock-pka-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "pka_ick"; + clocks = <&security_l3_ick>; + ti,bit-shift = <4>; + }; }; - cam_mclk: cam_mclk@f00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m5x2_ck>; - ti,bit-shift = <0>; - reg = <0x0f00>; - ti,set-rate-parent; + /* CM_FCLKEN_CAM */ + clock@f00 { + compatible = "ti,clksel"; + reg = <0xf00>; + #clock-cells = <2>; + #address-cells = <0>; + + cam_mclk: clock-cam-mclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "cam_mclk"; + clocks = <&dpll4_m5x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; + + csi2_96m_fck: clock-csi2-96m-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "csi2_96m_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <1>; + }; }; cam_ick: cam_ick@f10 { @@ -62,14 +93,6 @@ ti,bit-shift = <0>; }; - csi2_96m_fck: csi2_96m_fck@f00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0f00>; - ti,bit-shift = <1>; - }; - security_l3_ick: security_l3_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -78,44 +101,51 @@ clock-div = <1>; }; - pka_ick: pka_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l3_ick>; - reg = <0x0a14>; - ti,bit-shift = <4>; - }; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; - icr_ick: icr_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <29>; - }; + icr_ick: clock-icr-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "icr_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <29>; + }; - des2_ick: des2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <26>; - }; + des2_ick: clock-des2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "des2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <26>; + }; - mspro_ick: mspro_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; + mspro_ick: clock-mspro-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mspro_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <23>; + }; - mailboxes_ick: mailboxes_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <7>; + mailboxes_ick: clock-mailboxes-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mailboxes_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <7>; + }; + + sad2d_ick: clock-sad2d-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sad2d_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <3>; + }; }; ssi_l4_ick: ssi_l4_ick { @@ -126,20 +156,27 @@ clock-div = <1>; }; - sr1_fck: sr1_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0c00>; - ti,bit-shift = <6>; - }; + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; - sr2_fck: sr2_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0c00>; - ti,bit-shift = <7>; + sr1_fck: clock-sr1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sr1_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + }; + + sr2_fck: clock-sr2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sr2_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <7>; + }; }; sr_l4_ick: sr_l4_ick { @@ -187,37 +224,45 @@ ti,bit-shift = <0>; }; - modem_fck: modem_fck@a00 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - reg = <0x0a00>; - ti,bit-shift = <31>; - }; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; - sad2d_ick: sad2d_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <3>; - }; + modem_fck: clock-modem-fck { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "modem_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <31>; + }; - mad2d_ick: mad2d_ick@a18 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l3_ick>; - reg = <0x0a18>; - ti,bit-shift = <3>; + mspro_fck: clock-mspro-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mspro_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <23>; + }; }; - mspro_fck: mspro_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; + /* CM_ICLKEN3_CORE */ + clock@a18 { + compatible = "ti,clksel"; + reg = <0xa18>; + #clock-cells = <2>; + #address-cells = <0>; + + mad2d_ick: clock-mad2d-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mad2d_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <3>; + }; }; + }; &cm_clockdomains { diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 8b8451399784..2eb73ae7ef3e 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP34xx/OMAP35xx SoC * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h> diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index 9974d5226971..dcc5cfcd1fe6 100644 --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -133,37 +133,66 @@ ti,bit-shift = <2>; }; - usbtll_ick: usbtll_ick@a18 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a18>; - ti,bit-shift = <2>; + /* CM_ICLKEN3_CORE */ + clock@a18 { + compatible = "ti,clksel"; + reg = <0xa18>; + #clock-cells = <2>; + #address-cells = <0>; + + usbtll_ick: clock-usbtll-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "usbtll_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <2>; + }; }; - mmchs3_ick: mmchs3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <30>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + mmchs3_ick: clock-mmchs3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <30>; + }; }; - mmchs3_fck: mmchs3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <30>; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + mmchs3_fck: clock-mmchs3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs3_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <30>; + }; }; - dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 { - #clock-cells = <0>; - compatible = "ti,dss-gate-clock"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - reg = <0x0e00>; - ti,set-rate-parent; + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,dss-gate-clock"; + clock-output-names = "dss1_alwon_fck_3430es2"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; }; dss_ick: dss_ick_3430es2@e10 { diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi index 4e9cc9003594..c5fdb2bd765d 100644 --- a/arch/arm/boot/dts/omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi @@ -58,12 +58,19 @@ ti,set-bit-to-disable; }; - uart4_fck: uart4_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_48m_fck>; + clock@1000 { + compatible = "ti,clksel"; reg = <0x1000>; - ti,bit-shift = <18>; + #clock-cells = <2>; + #address-cells = <0>; + + uart4_fck: clock-uart4-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart4_fck"; + clocks = <&per_48m_fck>; + ti,bit-shift = <18>; + }; }; }; diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index 945537aee3ca..c94eb86d3da7 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -5,21 +5,35 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &cm_clocks { - ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - reg = <0x0a00>; - }; - - ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "ssi_ssr_gate_fck_3430es2"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + }; + }; + + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "ssi_ssr_div_fck_3430es2"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; }; ssi_ssr_fck: ssi_ssr_fck_3430es2 { @@ -36,12 +50,27 @@ clock-div = <2>; }; - hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-hsotgusb-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-hsotgusb-interface-clock"; + clock-output-names = "hsotgusb_ick_3430es2"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + ssi_ick: clock-ssi-ick-3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-ssi-interface-clock"; + clock-output-names = "ssi_ick_3430es2"; + clocks = <&ssi_l4_ick>; + ti,bit-shift = <0>; + }; }; ssi_l4_ick: ssi_l4_ick { @@ -52,20 +81,19 @@ clock-div = <1>; }; - ssi_ick: ssi_ick_3430es2@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-ssi-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <0>; - }; + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; - usim_gate_fck: usim_gate_fck@c00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&omap_96m_fck>; - ti,bit-shift = <9>; - reg = <0x0c00>; + usim_gate_fck: clock-usim-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "usim_gate_fck"; + clocks = <&omap_96m_fck>; + ti,bit-shift = <9>; + }; }; sys_d2_ck: sys_d2_ck { @@ -140,13 +168,20 @@ clock-div = <20>; }; - usim_mux_fck: usim_mux_fck@c40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; - ti,bit-shift = <3>; - reg = <0x0c40>; - ti,index-starts-at-one; + clock@c40 { + compatible = "ti,clksel"; + reg = <0xc40>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_mux_fck: clock-usim-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "usim_mux_fck"; + clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; + ti,bit-shift = <3>; + ti,index-starts-at-one; + }; }; usim_fck: usim_fck { @@ -155,12 +190,19 @@ clocks = <&usim_gate_fck>, <&usim_mux_fck>; }; - usim_ick: usim_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <9>; + clock@c10 { + compatible = "ti,clksel"; + reg = <0xc10>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_ick: clock-usim-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "usim_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <9>; + }; }; }; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 22b33098b1a2..32ac7924a130 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP3 SoC * * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h> diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 0656c32439d2..2e13ca11ceea 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -78,12 +78,35 @@ }; &scm_clocks { - mcbsp5_mux_fck: mcbsp5_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <4>; + /* CONTROL_DEVCONF1 */ + clock@68 { + compatible = "ti,clksel"; reg = <0x68>; + #clock-cells = <2>; + #address-cells = <0>; + + mcbsp5_mux_fck: clock-mcbsp5-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp5_mux_fck"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + }; + + mcbsp3_mux_fck: clock-mcbsp3-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp3_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + }; + + mcbsp4_mux_fck: clock-mcbsp4-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp4_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + }; }; mcbsp5_fck: mcbsp5_fck { @@ -92,12 +115,28 @@ clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; }; - mcbsp1_mux_fck: mcbsp1_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x04>; + /* CONTROL_DEVCONF0 */ + clock@4 { + compatible = "ti,clksel"; + reg = <0x4>; + #clock-cells = <2>; + #address-cells = <0>; + + mcbsp1_mux_fck: clock-mcbsp1-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp1_mux_fck"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + }; + + mcbsp2_mux_fck: clock-mcbsp2-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp2_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <6>; + }; }; mcbsp1_fck: mcbsp1_fck { @@ -106,41 +145,18 @@ clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; }; - mcbsp2_mux_fck: mcbsp2_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <6>; - reg = <0x04>; - }; - mcbsp2_fck: mcbsp2_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; }; - mcbsp3_mux_fck: mcbsp3_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - reg = <0x68>; - }; - mcbsp3_fck: mcbsp3_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; }; - mcbsp4_mux_fck: mcbsp4_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x68>; - }; - mcbsp4_fck: mcbsp4_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; @@ -238,14 +254,87 @@ reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; }; - dpll3_m3_ck: dpll3_m3_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <16>; - ti,max-div = <31>; + /* CM_CLKSEL1_EMU */ + clock@1140 { + compatible = "ti,clksel"; reg = <0x1140>; - ti,index-starts-at-one; + #clock-cells = <2>; + #address-cells = <0>; + + dpll3_m3_ck: clock-dpll3-m3 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll3_m3_ck"; + clocks = <&dpll3_ck>; + ti,bit-shift = <16>; + ti,max-div = <31>; + ti,index-starts-at-one; + }; + + dpll4_m6_ck: clock-dpll4-m6 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m6_ck"; + clocks = <&dpll4_ck>; + ti,bit-shift = <24>; + ti,max-div = <63>; + ti,index-starts-at-one; + }; + + emu_src_mux_ck: clock-emu-src-mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "emu_src_mux_ck"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + }; + + pclk_fck: clock-pclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pclk_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <8>; + ti,max-div = <7>; + ti,index-starts-at-one; + }; + + pclkx2_fck: clock-pclkx2-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pclkx2_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + atclk_fck: clock-atclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "atclk_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <4>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + traceclk_src_fck: clock-traceclk-src-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "traceclk_src_fck"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + ti,bit-shift = <2>; + }; + + traceclk_fck: clock-traceclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "traceclk_fck"; + clocks = <&traceclk_src_fck>; + ti,bit-shift = <11>; + ti,max-div = <7>; + ti,index-starts-at-one; + }; }; dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { @@ -285,16 +374,6 @@ clock-frequency = <0x0>; }; - dpll3_m2_ck: dpll3_m2_ck@d40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <27>; - ti,max-div = <31>; - reg = <0x0d40>; - ti,index-starts-at-one; - }; - core_ck: core_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -345,22 +424,73 @@ clock-div = <1>; }; - omap_96m_fck: omap_96m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&cm_96m_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0d40>; - }; - - dpll4_m3_ck: dpll4_m3_ck@e40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - reg = <0x0e40>; - ti,index-starts-at-one; + /* CM_CLKSEL1_PLL */ + clock@d40 { + compatible = "ti,clksel"; + reg = <0xd40>; + #clock-cells = <2>; + #address-cells = <0>; + + dpll3_m2_ck: clock-dpll3-m2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll3_m2_ck"; + clocks = <&dpll3_ck>; + ti,bit-shift = <27>; + ti,max-div = <31>; + ti,index-starts-at-one; + }; + + omap_96m_fck: clock-omap-96m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_96m_fck"; + clocks = <&cm_96m_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + omap_54m_fck: clock-omap-54m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_54m_fck"; + clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; + ti,bit-shift = <5>; + }; + + omap_48m_fck: clock-omap-48m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_48m_fck"; + clocks = <&cm_96m_d2_fck>, <&sys_altclk>; + ti,bit-shift = <3>; + }; + }; + + /* CM_CLKSEL_DSS */ + clock@e40 { + compatible = "ti,clksel"; + reg = <0xe40>; + #clock-cells = <2>; + #address-cells = <0>; + + dpll4_m3_ck: clock-dpll4-m3 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m3_ck"; + clocks = <&dpll4_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + ti,index-starts-at-one; + }; + + dpll4_m4_ck: clock-dpll4-m4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m4_ck"; + clocks = <&dpll4_ck>; + ti,max-div = <16>; + ti,index-starts-at-one; + }; }; dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { @@ -380,14 +510,6 @@ ti,set-bit-to-disable; }; - omap_54m_fck: omap_54m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; - ti,bit-shift = <5>; - reg = <0x0d40>; - }; - cm_96m_d2_fck: cm_96m_d2_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -396,14 +518,6 @@ clock-div = <2>; }; - omap_48m_fck: omap_48m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&cm_96m_d2_fck>, <&sys_altclk>; - ti,bit-shift = <3>; - reg = <0x0d40>; - }; - omap_12m_fck: omap_12m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -412,15 +526,6 @@ clock-div = <4>; }; - dpll4_m4_ck: dpll4_m4_ck@e40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,max-div = <16>; - reg = <0x0e40>; - ti,index-starts-at-one; - }; - dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; @@ -468,16 +573,6 @@ ti,set-rate-parent; }; - dpll4_m6_ck: dpll4_m6_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <24>; - ti,max-div = <63>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -503,19 +598,37 @@ clock-div = <1>; }; - clkout2_src_gate_ck: clkout2_src_gate_ck@d70 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <7>; - reg = <0x0d70>; - }; - - clkout2_src_mux_ck: clkout2_src_mux_ck@d70 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; - reg = <0x0d70>; + /* CM_CLKOUT_CTRL */ + clock@d70 { + compatible = "ti,clksel"; + reg = <0xd70>; + #clock-cells = <2>; + #address-cells = <0>; + + clkout2_src_gate_ck: clock-clkout2-src-gate { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "clkout2_src_gate_ck"; + clocks = <&core_ck>; + ti,bit-shift = <7>; + }; + + clkout2_src_mux_ck: clock-clkout2-src-mux { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "clkout2_src_mux_ck"; + clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; + }; + + sys_clkout2: clock-sys-clkout2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "sys_clkout2"; + clocks = <&clkout2_src_ck>; + ti,bit-shift = <3>; + ti,max-div = <64>; + ti,index-power-of-two; + }; }; clkout2_src_ck: clkout2_src_ck { @@ -524,16 +637,6 @@ clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; }; - sys_clkout2: sys_clkout2@d70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout2_src_ck>; - ti,bit-shift = <3>; - ti,max-div = <64>; - reg = <0x0d70>; - ti,index-power-of-two; - }; - mpu_ck: mpu_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -558,49 +661,208 @@ clock-div = <1>; }; - l3_ick: l3_ick@a40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,max-div = <3>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - - l4_ick: l4_ick@a40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_ick>; - ti,bit-shift = <2>; - ti,max-div = <3>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - - rm_ick: rm_ick@c40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <1>; - ti,max-div = <3>; - reg = <0x0c40>; - ti,index-starts-at-one; - }; - - gpt10_gate_fck: gpt10_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <11>; - reg = <0x0a00>; - }; - - gpt10_mux_fck: gpt10_mux_fck@a40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0a40>; + /* CM_CLKSEL_CORE */ + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + l3_ick: clock-l3-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l3_ick"; + clocks = <&core_ck>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + l4_ick: clock-l4-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l4_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <2>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + gpt10_mux_fck: clock-gpt10-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt10_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt11_mux_fck: clock-gpt11-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt11_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + }; + }; + + /* CM_CLKSEL_WKUP */ + clock@c40 { + compatible = "ti,clksel"; + reg = <0xc40>; + #clock-cells = <2>; + #address-cells = <0>; + + rm_ick: clock-rm-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "rm_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <1>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + gpt1_mux_fck: clock-gpt1-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt1_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + }; + }; + + /* CM_FCLKEN1_CORE */ + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt10_gate_fck: clock-gpt10-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt10_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <11>; + }; + + gpt11_gate_fck: clock-gpt11-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt11_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <12>; + }; + + mmchs2_fck: clock-mmchs2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs2_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <25>; + }; + + mmchs1_fck: clock-mmchs1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs1_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <24>; + }; + + i2c3_fck: clock-i2c3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c3_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <17>; + }; + + i2c2_fck: clock-i2c2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c2_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <16>; + }; + + i2c1_fck: clock-i2c1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c1_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <15>; + }; + + mcbsp5_gate_fck: clock-mcbsp5-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp5_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <10>; + }; + + mcbsp1_gate_fck: clock-mcbsp1-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp1_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <9>; + }; + + mcspi4_fck: clock-mcspi4-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi4_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <21>; + }; + + mcspi3_fck: clock-mcspi3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi3_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <20>; + }; + + mcspi2_fck: clock-mcspi2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi2_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <19>; + }; + + mcspi1_fck: clock-mcspi1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi1_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <18>; + }; + + uart2_fck: clock-uart2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart2_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <14>; + }; + + uart1_fck: clock-uart1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart1_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <13>; + }; + + hdq_fck: clock-hdq-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "hdq_fck"; + clocks = <&core_12m_fck>; + ti,bit-shift = <22>; + }; }; gpt10_fck: gpt10_fck { @@ -609,22 +871,6 @@ clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; }; - gpt11_gate_fck: gpt11_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <12>; - reg = <0x0a00>; - }; - - gpt11_mux_fck: gpt11_mux_fck@a40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x0a40>; - }; - gpt11_fck: gpt11_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; @@ -639,62 +885,6 @@ clock-div = <1>; }; - mmchs2_fck: mmchs2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <25>; - }; - - mmchs1_fck: mmchs1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <24>; - }; - - i2c3_fck: i2c3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <17>; - }; - - i2c2_fck: i2c2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <16>; - }; - - i2c1_fck: i2c1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <15>; - }; - - mcbsp5_gate_fck: mcbsp5_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <10>; - reg = <0x0a00>; - }; - - mcbsp1_gate_fck: mcbsp1_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <9>; - reg = <0x0a00>; - }; - core_48m_fck: core_48m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -703,54 +893,6 @@ clock-div = <1>; }; - mcspi4_fck: mcspi4_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <21>; - }; - - mcspi3_fck: mcspi3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <20>; - }; - - mcspi2_fck: mcspi2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <19>; - }; - - mcspi1_fck: mcspi1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <18>; - }; - - uart2_fck: uart2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <14>; - }; - - uart1_fck: uart1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <13>; - }; - core_12m_fck: core_12m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -759,14 +901,6 @@ clock-div = <1>; }; - hdq_fck: hdq_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_12m_fck>; - reg = <0x0a00>; - ti,bit-shift = <22>; - }; - core_l3_ick: core_l3_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -775,12 +909,172 @@ clock-div = <1>; }; - sdrc_ick: sdrc_ick@a10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <1>; + /* CM_ICLKEN1_CORE */ + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + sdrc_ick: clock-sdrc-ick { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sdrc_ick"; + clocks = <&core_l3_ick>; + ti,bit-shift = <1>; + }; + + mmchs2_ick: clock-mmchs2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <25>; + }; + + mmchs1_ick: clock-mmchs1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <24>; + }; + + hdq_ick: clock-hdq-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "hdq_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <22>; + }; + + mcspi4_ick: clock-mcspi4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi4_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <21>; + }; + + mcspi3_ick: clock-mcspi3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <20>; + }; + + mcspi2_ick: clock-mcspi2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <19>; + }; + + mcspi1_ick: clock-mcspi1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <18>; + }; + + i2c3_ick: clock-i2c3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <17>; + }; + + i2c2_ick: clock-i2c2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <16>; + }; + + i2c1_ick: clock-i2c1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <15>; + }; + + uart2_ick: clock-uart2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <14>; + }; + + uart1_ick: clock-uart1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <13>; + }; + + gpt11_ick: clock-gpt11-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt11_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <12>; + }; + + gpt10_ick: clock-gpt10-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt10_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <11>; + }; + + mcbsp5_ick: clock-mcbsp5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp5_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <10>; + }; + + mcbsp1_ick: clock-mcbsp1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <9>; + }; + + omapctrl_ick: clock-omapctrl-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "omapctrl_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <6>; + }; + + aes2_ick: clock-aes2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "aes2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <28>; + }; + + sha12_ick: clock-sha12-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sha12_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <27>; + }; }; gpmc_fck: gpmc_fck { @@ -799,164 +1093,36 @@ clock-div = <1>; }; - mmchs2_ick: mmchs2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <25>; - }; - - mmchs1_ick: mmchs1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <24>; - }; - - hdq_ick: hdq_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <22>; - }; - - mcspi4_ick: mcspi4_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <21>; - }; - - mcspi3_ick: mcspi3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <20>; - }; - - mcspi2_ick: mcspi2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <19>; - }; - - mcspi1_ick: mcspi1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <18>; - }; - - i2c3_ick: i2c3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <17>; - }; - - i2c2_ick: i2c2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <16>; - }; - - i2c1_ick: i2c1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <15>; - }; - - uart2_ick: uart2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <14>; - }; - - uart1_ick: uart1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <13>; - }; - - gpt11_ick: gpt11_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <12>; - }; - - gpt10_ick: gpt10_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <11>; - }; - - mcbsp5_ick: mcbsp5_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <10>; - }; - - mcbsp1_ick: mcbsp1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <9>; - }; - - omapctrl_ick: omapctrl_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <6>; - }; - - dss_tv_fck: dss_tv_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_54m_fck>; - reg = <0x0e00>; - ti,bit-shift = <2>; - }; - - dss_96m_fck: dss_96m_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_96m_fck>; - reg = <0x0e00>; - ti,bit-shift = <2>; - }; - - dss2_alwon_fck: dss2_alwon_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x0e00>; - ti,bit-shift = <1>; + /* CM_FCLKEN_DSS */ + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss_tv_fck: clock-dss-tv-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss_tv_fck"; + clocks = <&omap_54m_fck>; + ti,bit-shift = <2>; + }; + + dss_96m_fck: clock-dss-96m-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss_96m_fck"; + clocks = <&omap_96m_fck>; + ti,bit-shift = <2>; + }; + + dss2_alwon_fck: clock-dss2-alwon-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss2_alwon_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <1>; + }; }; dummy_ck: dummy_ck { @@ -965,19 +1131,36 @@ clock-frequency = <0>; }; - gpt1_gate_fck: gpt1_gate_fck@c00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <0>; - reg = <0x0c00>; - }; - - gpt1_mux_fck: gpt1_mux_fck@c40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - reg = <0x0c40>; + /* CM_FCLKEN_WKUP */ + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt1_gate_fck: clock-gpt1-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt1_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <0>; + }; + + gpio1_dbck: clock-gpio1-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio1_dbck"; + clocks = <&wkup_32k_fck>; + ti,bit-shift = <3>; + }; + + wdt2_fck: clock-wdt2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "wdt2_fck"; + clocks = <&wkup_32k_fck>; + ti,bit-shift = <5>; + }; }; gpt1_fck: gpt1_fck { @@ -986,14 +1169,6 @@ clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; }; - aes2_ick: aes2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - ti,bit-shift = <28>; - reg = <0x0a10>; - }; - wkup_32k_fck: wkup_32k_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -1002,76 +1177,60 @@ clock-div = <1>; }; - gpio1_dbck: gpio1_dbck@c00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&wkup_32k_fck>; - reg = <0x0c00>; - ti,bit-shift = <3>; - }; - - sha12_ick: sha12_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <27>; - }; - - wdt2_fck: wdt2_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&wkup_32k_fck>; - reg = <0x0c00>; - ti,bit-shift = <5>; - }; - - wdt2_ick: wdt2_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <5>; - }; - - wdt1_ick: wdt1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <4>; - }; - - gpio1_ick: gpio1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <3>; - }; - - omap_32ksync_ick: omap_32ksync_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <2>; - }; - - gpt12_ick: gpt12_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <1>; - }; - - gpt1_ick: gpt1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <0>; + /* CM_ICLKEN_WKUP */ + clock@c10 { + compatible = "ti,clksel"; + reg = <0xc10>; + #clock-cells = <2>; + #address-cells = <0>; + + wdt2_ick: clock-wdt2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt2_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <5>; + }; + + wdt1_ick: clock-wdt1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <4>; + }; + + gpio1_ick: clock-gpio1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <3>; + }; + + omap_32ksync_ick: clock-omap-32ksync-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "omap_32ksync_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <2>; + }; + + gpt12_ick: clock-gpt12-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt12_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <1>; + }; + + gpt1_ick: clock-gpt1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <0>; + }; }; per_96m_fck: per_96m_fck { @@ -1090,27 +1249,227 @@ clock-div = <1>; }; - uart3_fck: uart3_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_48m_fck>; - reg = <0x1000>; - ti,bit-shift = <11>; - }; - - gpt2_gate_fck: gpt2_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <3>; + /* CM_FCLKEN_PER */ + clock@1000 { + compatible = "ti,clksel"; reg = <0x1000>; - }; - - gpt2_mux_fck: gpt2_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; + #clock-cells = <2>; + #address-cells = <0>; + + uart3_fck: clock-uart3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart3_fck"; + clocks = <&per_48m_fck>; + ti,bit-shift = <11>; + }; + + gpt2_gate_fck: clock-gpt2-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt2_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + }; + + gpt3_gate_fck: clock-gpt3-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt3_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <4>; + }; + + gpt4_gate_fck: clock-gpt4-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt4_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <5>; + }; + + gpt5_gate_fck: clock-gpt5-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt5_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt6_gate_fck: clock-gpt6-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt6_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <7>; + }; + + gpt7_gate_fck: clock-gpt7-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt7_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <8>; + }; + + gpt8_gate_fck: clock-gpt8-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt8_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <9>; + }; + + gpt9_gate_fck: clock-gpt9-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt9_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <10>; + }; + + gpio6_dbck: clock-gpio6-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio6_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <17>; + }; + + gpio5_dbck: clock-gpio5-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio5_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <16>; + }; + + gpio4_dbck: clock-gpio4-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio4_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <15>; + }; + + gpio3_dbck: clock-gpio3-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio3_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <14>; + }; + + gpio2_dbck: clock-gpio2-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio2_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <13>; + }; + + wdt3_fck: clock-wdt3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "wdt3_fck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <12>; + }; + + mcbsp2_gate_fck: clock-mcbsp2-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp2_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <0>; + }; + + mcbsp3_gate_fck: clock-mcbsp3-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp3_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <1>; + }; + + mcbsp4_gate_fck: clock-mcbsp4-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp4_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <2>; + }; + }; + + /* CM_CLKSEL_PER */ + clock@1040 { + compatible = "ti,clksel"; reg = <0x1040>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt2_mux_fck: clock-gpt2-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt2_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + }; + + gpt3_mux_fck: clock-gpt3-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt3_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <1>; + }; + + gpt4_mux_fck: clock-gpt4-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt4_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <2>; + }; + + gpt5_mux_fck: clock-gpt5-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt5_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <3>; + }; + + gpt6_mux_fck: clock-gpt6-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt6_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <4>; + }; + + gpt7_mux_fck: clock-gpt7-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt7_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <5>; + }; + + gpt8_mux_fck: clock-gpt8-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt8_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt9_mux_fck: clock-gpt9-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt9_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + }; }; gpt2_fck: gpt2_fck { @@ -1119,154 +1478,42 @@ clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; }; - gpt3_gate_fck: gpt3_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x1000>; - }; - - gpt3_mux_fck: gpt3_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <1>; - reg = <0x1040>; - }; - gpt3_fck: gpt3_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; }; - gpt4_gate_fck: gpt4_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x1000>; - }; - - gpt4_mux_fck: gpt4_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <2>; - reg = <0x1040>; - }; - gpt4_fck: gpt4_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; }; - gpt5_gate_fck: gpt5_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x1000>; - }; - - gpt5_mux_fck: gpt5_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x1040>; - }; - gpt5_fck: gpt5_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; }; - gpt6_gate_fck: gpt6_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x1000>; - }; - - gpt6_mux_fck: gpt6_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x1040>; - }; - gpt6_fck: gpt6_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; }; - gpt7_gate_fck: gpt7_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <8>; - reg = <0x1000>; - }; - - gpt7_mux_fck: gpt7_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x1040>; - }; - gpt7_fck: gpt7_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; }; - gpt8_gate_fck: gpt8_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <9>; - reg = <0x1000>; - }; - - gpt8_mux_fck: gpt8_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x1040>; - }; - gpt8_fck: gpt8_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; }; - gpt9_gate_fck: gpt9_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <10>; - reg = <0x1000>; - }; - - gpt9_mux_fck: gpt9_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x1040>; - }; - gpt9_fck: gpt9_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; @@ -1281,54 +1528,6 @@ clock-div = <1>; }; - gpio6_dbck: gpio6_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <17>; - }; - - gpio5_dbck: gpio5_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <16>; - }; - - gpio4_dbck: gpio4_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <15>; - }; - - gpio3_dbck: gpio3_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <14>; - }; - - gpio2_dbck: gpio2_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <13>; - }; - - wdt3_fck: wdt3_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <12>; - }; - per_l4_ick: per_l4_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -1337,187 +1536,164 @@ clock-div = <1>; }; - gpio6_ick: gpio6_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <17>; - }; - - gpio5_ick: gpio5_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <16>; - }; - - gpio4_ick: gpio4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <15>; - }; - - gpio3_ick: gpio3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <14>; - }; - - gpio2_ick: gpio2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <13>; - }; - - wdt3_ick: wdt3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <12>; - }; - - uart3_ick: uart3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <11>; - }; - - uart4_ick: uart4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <18>; - }; - - gpt9_ick: gpt9_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <10>; - }; - - gpt8_ick: gpt8_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <9>; - }; - - gpt7_ick: gpt7_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <8>; - }; - - gpt6_ick: gpt6_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <7>; - }; - - gpt5_ick: gpt5_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <6>; - }; - - gpt4_ick: gpt4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <5>; - }; - - gpt3_ick: gpt3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <4>; - }; - - gpt2_ick: gpt2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <3>; - }; - - mcbsp2_ick: mcbsp2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <0>; - }; - - mcbsp3_ick: mcbsp3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <1>; - }; - - mcbsp4_ick: mcbsp4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; + /* CM_ICLKEN_PER */ + clock@1010 { + compatible = "ti,clksel"; reg = <0x1010>; - ti,bit-shift = <2>; - }; - - mcbsp2_gate_fck: mcbsp2_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <0>; - reg = <0x1000>; - }; - - mcbsp3_gate_fck: mcbsp3_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <1>; - reg = <0x1000>; - }; - - mcbsp4_gate_fck: mcbsp4_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x1000>; - }; - - emu_src_mux_ck: emu_src_mux_ck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - reg = <0x1140>; + #clock-cells = <2>; + #address-cells = <0>; + + gpio6_ick: clock-gpio6-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio6_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <17>; + }; + + gpio5_ick: clock-gpio5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio5_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <16>; + }; + + gpio4_ick: clock-gpio4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <15>; + }; + + gpio3_ick: clock-gpio3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <14>; + }; + + gpio2_ick: clock-gpio2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <13>; + }; + + wdt3_ick: clock-wdt3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <12>; + }; + + uart3_ick: clock-uart3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <11>; + }; + + uart4_ick: clock-uart4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <18>; + }; + + gpt9_ick: clock-gpt9-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt9_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <10>; + }; + + gpt8_ick: clock-gpt8-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt8_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <9>; + }; + + gpt7_ick: clock-gpt7-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt7_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <8>; + }; + + gpt6_ick: clock-gpt6-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt6_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <7>; + }; + + gpt5_ick: clock-gpt5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt5_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <6>; + }; + + gpt4_ick: clock-gpt4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <5>; + }; + + gpt3_ick: clock-gpt3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <4>; + }; + + gpt2_ick: clock-gpt2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <3>; + }; + + mcbsp2_ick: clock-mcbsp2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <0>; + }; + + mcbsp3_ick: clock-mcbsp3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <1>; + }; + + mcbsp4_ick: clock-mcbsp4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <2>; + }; }; emu_src_ck: emu_src_ck { @@ -1526,54 +1702,6 @@ clocks = <&emu_src_mux_ck>; }; - pclk_fck: pclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <8>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - pclkx2_fck: pclkx2_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - atclk_fck: atclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <4>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - traceclk_src_fck: traceclk_src_fck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - ti,bit-shift = <2>; - reg = <0x1140>; - }; - - traceclk_fck: traceclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&traceclk_src_fck>; - ti,bit-shift = <11>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - secure_32k_fck: secure_32k_fck { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi index 03d054b2bf9a..4d7eeb133dad 100644 --- a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi +++ b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP4/5 SoC CPU thermal * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Contact: Eduardo Valentin <eduardo.valentin@ti.com> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 609a8dea946b..518652a599bd 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -558,7 +558,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi index 39297868ec85..581e088231b5 100644 --- a/arch/arm/boot/dts/omap443x-clocks.dtsi +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi @@ -8,6 +8,7 @@ bandgap_fclk: bandgap_fclk@1888 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "bandgap_fclk"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x1888>; diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi index 8466161197ae..238aceb799f8 100644 --- a/arch/arm/boot/dts/omap443x.dtsi +++ b/arch/arm/boot/dts/omap443x.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP443x SoC * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "omap4.dtsi" diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi index 3d6db1db94e0..1b27a862ae81 100644 --- a/arch/arm/boot/dts/omap4460.dtsi +++ b/arch/arm/boot/dts/omap4460.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP4460 SoC * * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "omap4.dtsi" diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi index 0f41714cffbb..d9362fef6720 100644 --- a/arch/arm/boot/dts/omap446x-clocks.dtsi +++ b/arch/arm/boot/dts/omap446x-clocks.dtsi @@ -8,6 +8,7 @@ div_ts_ck: div_ts_ck@1888 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "div_ts_ck"; clocks = <&l4_wkup_clk_mux_ck>; ti,bit-shift = <24>; reg = <0x1888>; @@ -17,6 +18,7 @@ bandgap_ts_fclk: bandgap_ts_fclk@1888 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "bandgap_ts_fclk"; clocks = <&div_ts_ck>; ti,bit-shift = <8>; reg = <0x1888>; diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index 1f1c04d8f472..8df73d285638 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -8,18 +8,21 @@ extalt_clkin_ck: extalt_clkin_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "extalt_clkin_ck"; clock-frequency = <59000000>; }; pad_clks_src_ck: pad_clks_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "pad_clks_src_ck"; clock-frequency = <12000000>; }; pad_clks_ck: pad_clks_ck@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "pad_clks_ck"; clocks = <&pad_clks_src_ck>; ti,bit-shift = <8>; reg = <0x0108>; @@ -28,24 +31,28 @@ pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "pad_slimbus_core_clks_ck"; clock-frequency = <12000000>; }; secure_32k_clk_src_ck: secure_32k_clk_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "secure_32k_clk_src_ck"; clock-frequency = <32768>; }; slimbus_src_clk: slimbus_src_clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "slimbus_src_clk"; clock-frequency = <12000000>; }; slimbus_clk: slimbus_clk@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "slimbus_clk"; clocks = <&slimbus_src_clk>; ti,bit-shift = <10>; reg = <0x0108>; @@ -54,84 +61,98 @@ sys_32k_ck: sys_32k_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sys_32k_ck"; clock-frequency = <32768>; }; virt_12000000_ck: virt_12000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_12000000_ck"; clock-frequency = <12000000>; }; virt_13000000_ck: virt_13000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_13000000_ck"; clock-frequency = <13000000>; }; virt_16800000_ck: virt_16800000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_16800000_ck"; clock-frequency = <16800000>; }; virt_19200000_ck: virt_19200000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; virt_26000000_ck: virt_26000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; virt_27000000_ck: virt_27000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_27000000_ck"; clock-frequency = <27000000>; }; virt_38400000_ck: virt_38400000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_38400000_ck"; clock-frequency = <38400000>; }; tie_low_clock_ck: tie_low_clock_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "tie_low_clock_ck"; clock-frequency = <0>; }; utmi_phy_clkout_ck: utmi_phy_clkout_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "utmi_phy_clkout_ck"; clock-frequency = <60000000>; }; xclk60mhsp1_ck: xclk60mhsp1_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp1_ck"; clock-frequency = <60000000>; }; xclk60mhsp2_ck: xclk60mhsp2_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp2_ck"; clock-frequency = <60000000>; }; xclk60motg_ck: xclk60motg_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60motg_ck"; clock-frequency = <60000000>; }; dpll_abe_ck: dpll_abe_ck@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; + clock-output-names = "dpll_abe_ck"; clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; @@ -139,6 +160,7 @@ dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_abe_x2_ck"; clocks = <&dpll_abe_ck>; reg = <0x01f0>; }; @@ -146,6 +168,7 @@ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -157,6 +180,7 @@ abe_24m_fclk: abe_24m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "abe_24m_fclk"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <8>; @@ -165,6 +189,7 @@ abe_clk: abe_clk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_clk"; clocks = <&dpll_abe_m2x2_ck>; ti,max-div = <4>; reg = <0x0108>; @@ -175,6 +200,7 @@ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m3x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -186,6 +212,7 @@ core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "core_hsd_byp_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x012c>; @@ -194,6 +221,7 @@ dpll_core_ck: dpll_core_ck@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; @@ -201,12 +229,14 @@ dpll_core_x2_ck: dpll_core_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m6x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -218,6 +248,7 @@ dpll_core_m2_ck: dpll_core_m2_ck@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m2_ck"; clocks = <&dpll_core_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -229,6 +260,7 @@ ddrphy_ck: ddrphy_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "ddrphy_ck"; clocks = <&dpll_core_m2_ck>; clock-mult = <1>; clock-div = <2>; @@ -237,6 +269,7 @@ dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m5x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -248,6 +281,7 @@ div_core_ck: div_core_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "div_core_ck"; clocks = <&dpll_core_m5x2_ck>; reg = <0x0100>; ti,max-div = <2>; @@ -256,6 +290,7 @@ div_iva_hs_clk: div_iva_hs_clk@1dc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "div_iva_hs_clk"; clocks = <&dpll_core_m5x2_ck>; ti,max-div = <4>; reg = <0x01dc>; @@ -265,6 +300,7 @@ div_mpu_hs_clk: div_mpu_hs_clk@19c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "div_mpu_hs_clk"; clocks = <&dpll_core_m5x2_ck>; ti,max-div = <4>; reg = <0x019c>; @@ -274,6 +310,7 @@ dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m4x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -285,6 +322,7 @@ dll_clk_div_ck: dll_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dll_clk_div_ck"; clocks = <&dpll_core_m4x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -293,6 +331,7 @@ dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2_ck"; clocks = <&dpll_abe_ck>; ti,max-div = <31>; reg = <0x01f0>; @@ -302,6 +341,7 @@ dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "dpll_core_m3x2_gate_ck"; clocks = <&dpll_core_x2_ck>; ti,bit-shift = <8>; reg = <0x0134>; @@ -310,6 +350,7 @@ dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; + clock-output-names = "dpll_core_m3x2_div_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0134>; @@ -319,12 +360,14 @@ dpll_core_m3x2_ck: dpll_core_m3x2_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "dpll_core_m3x2_ck"; clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; }; dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m7x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -336,6 +379,7 @@ iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "iva_hsd_byp_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; ti,bit-shift = <23>; reg = <0x01ac>; @@ -344,6 +388,7 @@ dpll_iva_ck: dpll_iva_ck@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_iva_ck"; clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; assigned-clocks = <&dpll_iva_ck>; @@ -353,12 +398,14 @@ dpll_iva_x2_ck: dpll_iva_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_iva_x2_ck"; clocks = <&dpll_iva_ck>; }; dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_m4x2_ck"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -372,6 +419,7 @@ dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_m5x2_ck"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -385,6 +433,7 @@ dpll_mpu_ck: dpll_mpu_ck@160 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; @@ -392,6 +441,7 @@ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -403,6 +453,7 @@ per_hs_clk_div_ck: per_hs_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "per_hs_clk_div_ck"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -411,6 +462,7 @@ usb_hs_clk_div_ck: usb_hs_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "usb_hs_clk_div_ck"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <3>; @@ -419,6 +471,7 @@ l3_div_ck: l3_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3_div_ck"; clocks = <&div_core_ck>; ti,bit-shift = <4>; ti,max-div = <2>; @@ -428,6 +481,7 @@ l4_div_ck: l4_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l4_div_ck"; clocks = <&l3_div_ck>; ti,bit-shift = <8>; ti,max-div = <2>; @@ -437,6 +491,7 @@ lp_clk_div_ck: lp_clk_div_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "lp_clk_div_ck"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <16>; @@ -445,6 +500,7 @@ mpu_periphclk: mpu_periphclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_periphclk"; clocks = <&dpll_mpu_ck>; clock-mult = <1>; clock-div = <2>; @@ -453,6 +509,7 @@ ocp_abe_iclk: ocp_abe_iclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "ocp_abe_iclk"; clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>; ti,bit-shift = <24>; reg = <0x0528>; @@ -462,6 +519,7 @@ per_abe_24m_fclk: per_abe_24m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "per_abe_24m_fclk"; clocks = <&dpll_abe_m2_ck>; clock-mult = <1>; clock-div = <4>; @@ -470,6 +528,7 @@ dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "dummy_ck"; clock-frequency = <0>; }; }; @@ -478,6 +537,7 @@ sys_clkin_ck: sys_clkin_ck@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin_ck"; clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; reg = <0x0110>; ti,index-starts-at-one; @@ -486,6 +546,7 @@ abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_bypass_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; ti,bit-shift = <24>; reg = <0x0108>; @@ -494,6 +555,7 @@ abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_refclk_mux_ck"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; reg = <0x010c>; }; @@ -501,6 +563,7 @@ dbgclk_mux_ck: dbgclk_mux_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dbgclk_mux_ck"; clocks = <&sys_clkin_ck>; clock-mult = <1>; clock-div = <1>; @@ -509,6 +572,7 @@ l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "l4_wkup_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; reg = <0x0108>; }; @@ -516,6 +580,7 @@ syc_clk_div_ck: syc_clk_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "syc_clk_div_ck"; clocks = <&sys_clkin_ck>; reg = <0x0100>; ti,max-div = <2>; @@ -524,6 +589,7 @@ usim_ck: usim_ck@1858 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "usim_ck"; clocks = <&dpll_per_m4x2_ck>; ti,bit-shift = <24>; reg = <0x1858>; @@ -533,6 +599,7 @@ usim_fclk: usim_fclk@1858 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usim_fclk"; clocks = <&usim_ck>; ti,bit-shift = <8>; reg = <0x1858>; @@ -541,6 +608,7 @@ trace_clk_div_ck: trace_clk_div_ck { #clock-cells = <0>; compatible = "ti,clkdm-gate-clock"; + clock-output-names = "trace_clk_div_ck"; clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>; }; }; @@ -548,6 +616,7 @@ &prm_clockdomains { emu_sys_clkdm: emu_sys_clkdm { compatible = "ti,clockdomain"; + clock-output-names = "emu_sys_clkdm"; clocks = <&trace_clk_div_ck>; }; }; @@ -556,6 +625,7 @@ per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "per_hsd_byp_clk_mux_ck"; clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; ti,bit-shift = <23>; reg = <0x014c>; @@ -564,6 +634,7 @@ dpll_per_ck: dpll_per_ck@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; @@ -571,6 +642,7 @@ dpll_per_m2_ck: dpll_per_m2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <31>; reg = <0x0150>; @@ -580,6 +652,7 @@ dpll_per_x2_ck: dpll_per_x2_ck@150 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_per_x2_ck"; clocks = <&dpll_per_ck>; reg = <0x0150>; }; @@ -587,6 +660,7 @@ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -598,6 +672,7 @@ dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "dpll_per_m3x2_gate_ck"; clocks = <&dpll_per_x2_ck>; ti,bit-shift = <8>; reg = <0x0154>; @@ -606,6 +681,7 @@ dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; + clock-output-names = "dpll_per_m3x2_div_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; reg = <0x0154>; @@ -615,12 +691,14 @@ dpll_per_m3x2_ck: dpll_per_m3x2_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "dpll_per_m3x2_ck"; clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; }; dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m4x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -632,6 +710,7 @@ dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m5x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -643,6 +722,7 @@ dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m6x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -654,6 +734,7 @@ dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m7x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; ti,autoidle-shift = <8>; @@ -665,6 +746,7 @@ dpll_usb_ck: dpll_usb_ck@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; + clock-output-names = "dpll_usb_ck"; clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; @@ -672,6 +754,7 @@ dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; + clock-output-names = "dpll_usb_clkdcoldo_ck"; clocks = <&dpll_usb_ck>; ti,clock-div = <1>; ti,autoidle-shift = <8>; @@ -683,6 +766,7 @@ dpll_usb_m2_ck: dpll_usb_m2_ck@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_usb_m2_ck"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; ti,autoidle-shift = <8>; @@ -694,6 +778,7 @@ ducati_clk_mux_ck: ducati_clk_mux_ck@100 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "ducati_clk_mux_ck"; clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; reg = <0x0100>; }; @@ -701,6 +786,7 @@ func_12m_fclk: func_12m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <16>; @@ -709,6 +795,7 @@ func_24m_clk: func_24m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_24m_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; @@ -717,6 +804,7 @@ func_24mc_fclk: func_24mc_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_24mc_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <8>; @@ -725,6 +813,7 @@ func_48m_fclk: func_48m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "func_48m_fclk"; clocks = <&dpll_per_m2x2_ck>; reg = <0x0108>; ti,dividers = <4>, <8>; @@ -733,6 +822,7 @@ func_48mc_fclk: func_48mc_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_48mc_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <4>; @@ -741,6 +831,7 @@ func_64m_fclk: func_64m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "func_64m_fclk"; clocks = <&dpll_per_m4x2_ck>; reg = <0x0108>; ti,dividers = <2>, <4>; @@ -749,6 +840,7 @@ func_96m_fclk: func_96m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "func_96m_fclk"; clocks = <&dpll_per_m2x2_ck>; reg = <0x0108>; ti,dividers = <2>, <4>; @@ -757,6 +849,7 @@ init_60m_fclk: init_60m_fclk@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "init_60m_fclk"; clocks = <&dpll_usb_m2_ck>; reg = <0x0104>; ti,dividers = <1>, <8>; @@ -765,6 +858,7 @@ per_abe_nc_fclk: per_abe_nc_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "per_abe_nc_fclk"; clocks = <&dpll_abe_m2_ck>; reg = <0x0108>; ti,max-div = <2>; @@ -773,6 +867,7 @@ usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy_cm_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0640>; @@ -782,6 +877,7 @@ &cm2_clockdomains { l3_init_clkdm: l3_init_clkdm { compatible = "ti,clockdomain"; + clock-output-names = "l3_init_clkdm"; clocks = <&dpll_usb_ck>; }; }; @@ -790,6 +886,7 @@ auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk0_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0310>; @@ -798,6 +895,7 @@ auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk0_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0310>; @@ -806,12 +904,14 @@ auxclk0_src_ck: auxclk0_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk0_src_ck"; clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; }; auxclk0_ck: auxclk0_ck@310 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk0_ck"; clocks = <&auxclk0_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -821,6 +921,7 @@ auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk1_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0314>; @@ -829,6 +930,7 @@ auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk1_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0314>; @@ -837,12 +939,14 @@ auxclk1_src_ck: auxclk1_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk1_src_ck"; clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; }; auxclk1_ck: auxclk1_ck@314 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk1_ck"; clocks = <&auxclk1_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -852,6 +956,7 @@ auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk2_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0318>; @@ -860,6 +965,7 @@ auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk2_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0318>; @@ -868,12 +974,14 @@ auxclk2_src_ck: auxclk2_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk2_src_ck"; clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; }; auxclk2_ck: auxclk2_ck@318 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk2_ck"; clocks = <&auxclk2_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -883,6 +991,7 @@ auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk3_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x031c>; @@ -891,6 +1000,7 @@ auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk3_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x031c>; @@ -899,12 +1009,14 @@ auxclk3_src_ck: auxclk3_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk3_src_ck"; clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; }; auxclk3_ck: auxclk3_ck@31c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk3_ck"; clocks = <&auxclk3_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -914,6 +1026,7 @@ auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk4_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0320>; @@ -922,6 +1035,7 @@ auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk4_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0320>; @@ -930,12 +1044,14 @@ auxclk4_src_ck: auxclk4_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk4_src_ck"; clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; }; auxclk4_ck: auxclk4_ck@320 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk4_ck"; clocks = <&auxclk4_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -945,6 +1061,7 @@ auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk5_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0324>; @@ -953,6 +1070,7 @@ auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk5_src_mux_ck"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0324>; @@ -961,12 +1079,14 @@ auxclk5_src_ck: auxclk5_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk5_src_ck"; clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; }; auxclk5_ck: auxclk5_ck@324 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk5_ck"; clocks = <&auxclk5_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -976,6 +1096,7 @@ auxclkreq0_ck: auxclkreq0_ck@210 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq0_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0210>; @@ -984,6 +1105,7 @@ auxclkreq1_ck: auxclkreq1_ck@214 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq1_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0214>; @@ -992,6 +1114,7 @@ auxclkreq2_ck: auxclkreq2_ck@218 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq2_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0218>; @@ -1000,6 +1123,7 @@ auxclkreq3_ck: auxclkreq3_ck@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq3_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x021c>; @@ -1008,6 +1132,7 @@ auxclkreq4_ck: auxclkreq4_ck@220 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq4_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0220>; @@ -1016,6 +1141,7 @@ auxclkreq5_ck: auxclkreq5_ck@224 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq5_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; ti,bit-shift = <2>; reg = <0x0224>; @@ -1025,6 +1151,7 @@ &cm1 { mpuss_cm: mpuss_cm@300 { compatible = "ti,omap4-cm"; + clock-output-names = "mpuss_cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1032,6 +1159,7 @@ mpuss_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "mpuss_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1039,6 +1167,7 @@ tesla_cm: tesla_cm@400 { compatible = "ti,omap4-cm"; + clock-output-names = "tesla_cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1046,6 +1175,7 @@ tesla_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "tesla_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1053,6 +1183,7 @@ abe_cm: abe_cm@500 { compatible = "ti,omap4-cm"; + clock-output-names = "abe_cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1060,6 +1191,7 @@ abe_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "abe_clkctrl"; reg = <0x20 0x6c>; #clock-cells = <2>; }; @@ -1070,6 +1202,7 @@ &cm2 { l4_ao_cm: l4_ao_cm@600 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_ao_cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1077,6 +1210,7 @@ l4_ao_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_ao_clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; @@ -1084,6 +1218,7 @@ l3_1_cm: l3_1_cm@700 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_1_cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1091,6 +1226,7 @@ l3_1_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_1_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1098,6 +1234,7 @@ l3_2_cm: l3_2_cm@800 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_2_cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1105,6 +1242,7 @@ l3_2_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_2_clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; @@ -1112,6 +1250,7 @@ ducati_cm: ducati_cm@900 { compatible = "ti,omap4-cm"; + clock-output-names = "ducati_cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1119,6 +1258,7 @@ ducati_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "ducati_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1126,6 +1266,7 @@ l3_dma_cm: l3_dma_cm@a00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_dma_cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1133,6 +1274,7 @@ l3_dma_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_dma_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1140,6 +1282,7 @@ l3_emif_cm: l3_emif_cm@b00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_emif_cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1147,6 +1290,7 @@ l3_emif_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_emif_clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; @@ -1154,6 +1298,7 @@ d2d_cm: d2d_cm@c00 { compatible = "ti,omap4-cm"; + clock-output-names = "d2d_cm"; reg = <0xc00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1161,6 +1306,7 @@ d2d_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "d2d_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1168,6 +1314,7 @@ l4_cfg_cm: l4_cfg_cm@d00 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_cfg_cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1175,6 +1322,7 @@ l4_cfg_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_cfg_clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; @@ -1182,6 +1330,7 @@ l3_instr_cm: l3_instr_cm@e00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_instr_cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1189,6 +1338,7 @@ l3_instr_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_instr_clkctrl"; reg = <0x20 0x24>; #clock-cells = <2>; }; @@ -1196,6 +1346,7 @@ ivahd_cm: ivahd_cm@f00 { compatible = "ti,omap4-cm"; + clock-output-names = "ivahd_cm"; reg = <0xf00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1203,6 +1354,7 @@ ivahd_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "ivahd_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; @@ -1210,6 +1362,7 @@ iss_cm: iss_cm@1000 { compatible = "ti,omap4-cm"; + clock-output-names = "iss_cm"; reg = <0x1000 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1217,6 +1370,7 @@ iss_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "iss_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; @@ -1224,6 +1378,7 @@ l3_dss_cm: l3_dss_cm@1100 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_dss_cm"; reg = <0x1100 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1231,6 +1386,7 @@ l3_dss_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_dss_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1238,6 +1394,7 @@ l3_gfx_cm: l3_gfx_cm@1200 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_gfx_cm"; reg = <0x1200 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1245,6 +1402,7 @@ l3_gfx_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_gfx_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1252,6 +1410,7 @@ l3_init_cm: l3_init_cm@1300 { compatible = "ti,omap4-cm"; + clock-output-names = "l3_init_cm"; reg = <0x1300 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1259,26 +1418,30 @@ l3_init_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3_init_clkctrl"; reg = <0x20 0xc4>; #clock-cells = <2>; }; }; - l4_per_cm: l4_per_cm@1400 { + l4_per_cm: clock@1400 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_per_cm"; reg = <0x1400 0x200>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1400 0x200>; l4_per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4_per_clkctrl"; reg = <0x20 0x144>; #clock-cells = <2>; }; l4_secure_clkctrl: clock@1a0 { - compatible = "ti,clkctrl-l4-secure", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4_secure_clkctrl"; reg = <0x1a0 0x3c>; #clock-cells = <2>; }; @@ -1288,6 +1451,7 @@ &prm { l4_wkup_cm: l4_wkup_cm@1800 { compatible = "ti,omap4-cm"; + clock-output-names = "l4_wkup_cm"; reg = <0x1800 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1295,6 +1459,7 @@ l4_wkup_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4_wkup_clkctrl"; reg = <0x20 0x5c>; #clock-cells = <2>; }; @@ -1302,6 +1467,7 @@ emu_sys_cm: emu_sys_cm@1a00 { compatible = "ti,omap4-cm"; + clock-output-names = "emu_sys_cm"; reg = <0x1a00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1309,6 +1475,7 @@ emu_sys_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "emu_sys_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; diff --git a/arch/arm/boot/dts/omap5-core-thermal.dtsi b/arch/arm/boot/dts/omap5-core-thermal.dtsi index 02e76338bfbc..e0d8e39a0014 100644 --- a/arch/arm/boot/dts/omap5-core-thermal.dtsi +++ b/arch/arm/boot/dts/omap5-core-thermal.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP543x SoC CORE thermal * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Contact: Eduardo Valentin <eduardo.valentin@ti.com> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi index bf8fa9372e57..1b4b7d9136c8 100644 --- a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi +++ b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP543x SoC GPU thermal * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Contact: Eduardo Valentin <eduardo.valentin@ti.com> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts index 76e499d89d24..3851120857d7 100644 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ b/arch/arm/boot/dts/omap5-igep0050.dts @@ -128,7 +128,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@3 { + ethernet: ethernet@3 { compatible = "usb424,7500"; reg = <3>; }; diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index 06cc3a19ddaa..3b505fe415ed 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -482,7 +482,7 @@ clocks = <&usb_phy_cm_clk32k>, <&sys_clkin>, <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; - clock-names = "wkupclk", + clock-names = "wkupclk", "sysclk", "refclk"; #phy-cells = <0>; diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 51d5fcae5081..453da9f18a99 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -209,7 +209,7 @@ #size-cells = <0>; }; - ethernet: usbether@3 { + ethernet: ethernet@3 { compatible = "usb424,9730"; reg = <3>; }; diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 42f2c447727d..5cf3b0e78c15 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -8,12 +8,14 @@ pad_clks_src_ck: pad_clks_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "pad_clks_src_ck"; clock-frequency = <12000000>; }; pad_clks_ck: pad_clks_ck@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "pad_clks_ck"; clocks = <&pad_clks_src_ck>; ti,bit-shift = <8>; reg = <0x0108>; @@ -22,18 +24,21 @@ secure_32k_clk_src_ck: secure_32k_clk_src_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "secure_32k_clk_src_ck"; clock-frequency = <32768>; }; slimbus_src_clk: slimbus_src_clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "slimbus_src_clk"; clock-frequency = <12000000>; }; slimbus_clk: slimbus_clk@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "slimbus_clk"; clocks = <&slimbus_src_clk>; ti,bit-shift = <10>; reg = <0x0108>; @@ -42,66 +47,77 @@ sys_32k_ck: sys_32k_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "sys_32k_ck"; clock-frequency = <32768>; }; virt_12000000_ck: virt_12000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_12000000_ck"; clock-frequency = <12000000>; }; virt_13000000_ck: virt_13000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_13000000_ck"; clock-frequency = <13000000>; }; virt_16800000_ck: virt_16800000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_16800000_ck"; clock-frequency = <16800000>; }; virt_19200000_ck: virt_19200000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_19200000_ck"; clock-frequency = <19200000>; }; virt_26000000_ck: virt_26000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_26000000_ck"; clock-frequency = <26000000>; }; virt_27000000_ck: virt_27000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_27000000_ck"; clock-frequency = <27000000>; }; virt_38400000_ck: virt_38400000_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "virt_38400000_ck"; clock-frequency = <38400000>; }; xclk60mhsp1_ck: xclk60mhsp1_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp1_ck"; clock-frequency = <60000000>; }; xclk60mhsp2_ck: xclk60mhsp2_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "xclk60mhsp2_ck"; clock-frequency = <60000000>; }; dpll_abe_ck: dpll_abe_ck@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; + clock-output-names = "dpll_abe_ck"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; @@ -109,12 +125,14 @@ dpll_abe_x2_ck: dpll_abe_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_abe_x2_ck"; clocks = <&dpll_abe_ck>; }; dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m2x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; reg = <0x01f0>; @@ -124,6 +142,7 @@ abe_24m_fclk: abe_24m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "abe_24m_fclk"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <8>; @@ -132,6 +151,7 @@ abe_clk: abe_clk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_clk"; clocks = <&dpll_abe_m2x2_ck>; ti,max-div = <4>; reg = <0x0108>; @@ -141,6 +161,7 @@ abe_iclk: abe_iclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "abe_iclk"; clocks = <&aess_fclk>; ti,bit-shift = <24>; reg = <0x0528>; @@ -150,6 +171,7 @@ abe_lp_clk_div: abe_lp_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "abe_lp_clk_div"; clocks = <&dpll_abe_m2x2_ck>; clock-mult = <1>; clock-div = <16>; @@ -158,6 +180,7 @@ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_abe_m3x2_ck"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; reg = <0x01f4>; @@ -167,6 +190,7 @@ dpll_core_byp_mux: dpll_core_byp_mux@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_core_byp_mux"; clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; ti,bit-shift = <23>; reg = <0x012c>; @@ -175,6 +199,7 @@ dpll_core_ck: dpll_core_ck@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; + clock-output-names = "dpll_core_ck"; clocks = <&sys_clkin>, <&dpll_core_byp_mux>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; @@ -182,12 +207,14 @@ dpll_core_x2_ck: dpll_core_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_core_x2_ck"; clocks = <&dpll_core_ck>; }; dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h21x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0150>; @@ -197,6 +224,7 @@ c2c_fclk: c2c_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "c2c_fclk"; clocks = <&dpll_core_h21x2_ck>; clock-mult = <1>; clock-div = <1>; @@ -205,6 +233,7 @@ c2c_iclk: c2c_iclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "c2c_iclk"; clocks = <&c2c_fclk>; clock-mult = <1>; clock-div = <2>; @@ -213,6 +242,7 @@ dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h11x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0138>; @@ -222,6 +252,7 @@ dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h12x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x013c>; @@ -231,6 +262,7 @@ dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h13x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0140>; @@ -240,6 +272,7 @@ dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h14x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0144>; @@ -249,6 +282,7 @@ dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h22x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0154>; @@ -258,6 +292,7 @@ dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h23x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x0158>; @@ -267,6 +302,7 @@ dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_h24x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; reg = <0x015c>; @@ -276,6 +312,7 @@ dpll_core_m2_ck: dpll_core_m2_ck@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m2_ck"; clocks = <&dpll_core_ck>; ti,max-div = <31>; reg = <0x0130>; @@ -285,6 +322,7 @@ dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_core_m3x2_ck"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; reg = <0x0134>; @@ -294,6 +332,7 @@ iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "iva_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; @@ -302,6 +341,7 @@ dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_iva_byp_mux"; clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x01ac>; @@ -310,6 +350,7 @@ dpll_iva_ck: dpll_iva_ck@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_iva_ck"; clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; assigned-clocks = <&dpll_iva_ck>; @@ -319,12 +360,14 @@ dpll_iva_x2_ck: dpll_iva_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_iva_x2_ck"; clocks = <&dpll_iva_ck>; }; dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_h11x2_ck"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <63>; reg = <0x01b8>; @@ -336,6 +379,7 @@ dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_iva_h12x2_ck"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <63>; reg = <0x01bc>; @@ -347,6 +391,7 @@ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "mpu_dpll_hs_clk_div"; clocks = <&dpll_core_h12x2_ck>; clock-mult = <1>; clock-div = <1>; @@ -355,6 +400,7 @@ dpll_mpu_ck: dpll_mpu_ck@160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; + clock-output-names = "dpll_mpu_ck"; clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; @@ -362,6 +408,7 @@ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_mpu_m2_ck"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; reg = <0x0170>; @@ -371,6 +418,7 @@ per_dpll_hs_clk_div: per_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "per_dpll_hs_clk_div"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -379,6 +427,7 @@ usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "usb_dpll_hs_clk_div"; clocks = <&dpll_abe_m3x2_ck>; clock-mult = <1>; clock-div = <3>; @@ -387,6 +436,7 @@ l3_iclk_div: l3_iclk_div@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3_iclk_div"; ti,max-div = <2>; ti,bit-shift = <4>; reg = <0x100>; @@ -397,6 +447,7 @@ gpu_l3_iclk: gpu_l3_iclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "gpu_l3_iclk"; clocks = <&l3_iclk_div>; clock-mult = <1>; clock-div = <1>; @@ -405,6 +456,7 @@ l4_root_clk_div: l4_root_clk_div@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l4_root_clk_div"; ti,max-div = <2>; ti,bit-shift = <8>; reg = <0x100>; @@ -415,6 +467,7 @@ slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "slimbus1_slimbus_clk"; clocks = <&slimbus_clk>; ti,bit-shift = <11>; reg = <0x0560>; @@ -423,6 +476,7 @@ aess_fclk: aess_fclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "aess_fclk"; clocks = <&abe_clk>; ti,bit-shift = <24>; ti,max-div = <2>; @@ -432,6 +486,7 @@ mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "mcasp_sync_mux_ck"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; ti,bit-shift = <26>; reg = <0x0540>; @@ -440,6 +495,7 @@ mcasp_gfclk: mcasp_gfclk@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "mcasp_gfclk"; clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; ti,bit-shift = <24>; reg = <0x0540>; @@ -448,6 +504,7 @@ dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; + clock-output-names = "dummy_ck"; clock-frequency = <0>; }; }; @@ -455,6 +512,7 @@ sys_clkin: sys_clkin@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "sys_clkin"; clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; reg = <0x0110>; ti,index-starts-at-one; @@ -463,6 +521,7 @@ abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_bypass_clk_mux"; clocks = <&sys_clkin>, <&sys_32k_ck>; reg = <0x0108>; }; @@ -470,6 +529,7 @@ abe_dpll_clk_mux: abe_dpll_clk_mux@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_clk_mux"; clocks = <&sys_clkin>, <&sys_32k_ck>; reg = <0x010c>; }; @@ -477,6 +537,7 @@ custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "custefuse_sys_gfclk_div"; clocks = <&sys_clkin>; clock-mult = <1>; clock-div = <2>; @@ -485,6 +546,7 @@ dss_syc_gfclk_div: dss_syc_gfclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dss_syc_gfclk_div"; clocks = <&sys_clkin>; clock-mult = <1>; clock-div = <1>; @@ -493,6 +555,7 @@ wkupaon_iclk_mux: wkupaon_iclk_mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "wkupaon_iclk_mux"; clocks = <&sys_clkin>, <&abe_lp_clk_div>; reg = <0x0108>; }; @@ -500,6 +563,7 @@ l3instr_ts_gclk_div: l3instr_ts_gclk_div { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "l3instr_ts_gclk_div"; clocks = <&wkupaon_iclk_mux>; clock-mult = <1>; clock-div = <1>; @@ -511,6 +575,7 @@ dpll_per_byp_mux: dpll_per_byp_mux@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_per_byp_mux"; clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x014c>; @@ -519,6 +584,7 @@ dpll_per_ck: dpll_per_ck@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_per_ck"; clocks = <&sys_clkin>, <&dpll_per_byp_mux>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; @@ -526,12 +592,14 @@ dpll_per_x2_ck: dpll_per_x2_ck { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; + clock-output-names = "dpll_per_x2_ck"; clocks = <&dpll_per_ck>; }; dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h11x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; reg = <0x0158>; @@ -541,6 +609,7 @@ dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h12x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; reg = <0x015c>; @@ -550,6 +619,7 @@ dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_h14x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; reg = <0x0164>; @@ -559,6 +629,7 @@ dpll_per_m2_ck: dpll_per_m2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2_ck"; clocks = <&dpll_per_ck>; ti,max-div = <31>; reg = <0x0150>; @@ -568,6 +639,7 @@ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m2x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; reg = <0x0150>; @@ -577,6 +649,7 @@ dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_per_m3x2_ck"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; reg = <0x0154>; @@ -586,6 +659,7 @@ dpll_unipro1_ck: dpll_unipro1_ck@200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_unipro1_ck"; clocks = <&sys_clkin>, <&sys_clkin>; reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; }; @@ -593,6 +667,7 @@ dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_unipro1_clkdcoldo"; clocks = <&dpll_unipro1_ck>; clock-mult = <1>; clock-div = <1>; @@ -601,6 +676,7 @@ dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_unipro1_m2_ck"; clocks = <&dpll_unipro1_ck>; ti,max-div = <127>; reg = <0x0210>; @@ -610,6 +686,7 @@ dpll_unipro2_ck: dpll_unipro2_ck@1c0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; + clock-output-names = "dpll_unipro2_ck"; clocks = <&sys_clkin>, <&sys_clkin>; reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; }; @@ -617,6 +694,7 @@ dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_unipro2_clkdcoldo"; clocks = <&dpll_unipro2_ck>; clock-mult = <1>; clock-div = <1>; @@ -625,6 +703,7 @@ dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_unipro2_m2_ck"; clocks = <&dpll_unipro2_ck>; ti,max-div = <127>; reg = <0x01d0>; @@ -634,6 +713,7 @@ dpll_usb_byp_mux: dpll_usb_byp_mux@18c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "dpll_usb_byp_mux"; clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; ti,bit-shift = <23>; reg = <0x018c>; @@ -642,6 +722,7 @@ dpll_usb_ck: dpll_usb_ck@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; + clock-output-names = "dpll_usb_ck"; clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; @@ -649,6 +730,7 @@ dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "dpll_usb_clkdcoldo"; clocks = <&dpll_usb_ck>; clock-mult = <1>; clock-div = <1>; @@ -657,6 +739,7 @@ dpll_usb_m2_ck: dpll_usb_m2_ck@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "dpll_usb_m2_ck"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; reg = <0x0190>; @@ -666,6 +749,7 @@ func_128m_clk: func_128m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_128m_clk"; clocks = <&dpll_per_h11x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -674,6 +758,7 @@ func_12m_fclk: func_12m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_12m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <16>; @@ -682,6 +767,7 @@ func_24m_clk: func_24m_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_24m_clk"; clocks = <&dpll_per_m2_ck>; clock-mult = <1>; clock-div = <4>; @@ -690,6 +776,7 @@ func_48m_fclk: func_48m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_48m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <4>; @@ -698,6 +785,7 @@ func_96m_fclk: func_96m_fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; + clock-output-names = "func_96m_fclk"; clocks = <&dpll_per_m2x2_ck>; clock-mult = <1>; clock-div = <2>; @@ -706,6 +794,7 @@ l3init_60m_fclk: l3init_60m_fclk@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "l3init_60m_fclk"; clocks = <&dpll_usb_m2_ck>; reg = <0x0104>; ti,dividers = <1>, <8>; @@ -714,6 +803,7 @@ iss_ctrlclk: iss_ctrlclk@1320 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "iss_ctrlclk"; clocks = <&func_96m_fclk>; ti,bit-shift = <8>; reg = <0x1320>; @@ -722,6 +812,7 @@ lli_txphy_clk: lli_txphy_clk@f20 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "lli_txphy_clk"; clocks = <&dpll_unipro1_clkdcoldo>; ti,bit-shift = <8>; reg = <0x0f20>; @@ -730,6 +821,7 @@ lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "lli_txphy_ls_clk"; clocks = <&dpll_unipro1_m2_ck>; ti,bit-shift = <9>; reg = <0x0f20>; @@ -738,6 +830,7 @@ usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "usb_phy_cm_clk32k"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x0640>; @@ -746,6 +839,7 @@ fdif_fclk: fdif_fclk@1328 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "fdif_fclk"; clocks = <&dpll_per_h11x2_ck>; ti,bit-shift = <24>; ti,max-div = <2>; @@ -755,6 +849,7 @@ gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpu_core_gclk_mux"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; ti,bit-shift = <24>; reg = <0x1520>; @@ -763,6 +858,7 @@ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "gpu_hyd_gclk_mux"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; ti,bit-shift = <25>; reg = <0x1520>; @@ -771,6 +867,7 @@ hsi_fclk: hsi_fclk@1638 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "hsi_fclk"; clocks = <&dpll_per_m2x2_ck>; ti,bit-shift = <24>; ti,max-div = <2>; @@ -781,6 +878,7 @@ &cm_core_clockdomains { l3init_clkdm: l3init_clkdm { compatible = "ti,clockdomain"; + clock-output-names = "l3init_clkdm"; clocks = <&dpll_usb_ck>; }; }; @@ -789,6 +887,7 @@ auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk0_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0310>; @@ -797,6 +896,7 @@ auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk0_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0310>; @@ -805,12 +905,14 @@ auxclk0_src_ck: auxclk0_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk0_src_ck"; clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; }; auxclk0_ck: auxclk0_ck@310 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk0_ck"; clocks = <&auxclk0_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -820,6 +922,7 @@ auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk1_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0314>; @@ -828,6 +931,7 @@ auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk1_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0314>; @@ -836,12 +940,14 @@ auxclk1_src_ck: auxclk1_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk1_src_ck"; clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; }; auxclk1_ck: auxclk1_ck@314 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk1_ck"; clocks = <&auxclk1_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -851,6 +957,7 @@ auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk2_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0318>; @@ -859,6 +966,7 @@ auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk2_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0318>; @@ -867,12 +975,14 @@ auxclk2_src_ck: auxclk2_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk2_src_ck"; clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; }; auxclk2_ck: auxclk2_ck@318 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk2_ck"; clocks = <&auxclk2_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -882,6 +992,7 @@ auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk3_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x031c>; @@ -890,6 +1001,7 @@ auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk3_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x031c>; @@ -898,12 +1010,14 @@ auxclk3_src_ck: auxclk3_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk3_src_ck"; clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; }; auxclk3_ck: auxclk3_ck@31c { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk3_ck"; clocks = <&auxclk3_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -913,6 +1027,7 @@ auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "auxclk4_src_gate_ck"; clocks = <&dpll_core_m3x2_ck>; ti,bit-shift = <8>; reg = <0x0320>; @@ -921,6 +1036,7 @@ auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; + clock-output-names = "auxclk4_src_mux_ck"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; ti,bit-shift = <1>; reg = <0x0320>; @@ -929,12 +1045,14 @@ auxclk4_src_ck: auxclk4_src_ck { #clock-cells = <0>; compatible = "ti,composite-clock"; + clock-output-names = "auxclk4_src_ck"; clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; }; auxclk4_ck: auxclk4_ck@320 { #clock-cells = <0>; compatible = "ti,divider-clock"; + clock-output-names = "auxclk4_ck"; clocks = <&auxclk4_src_ck>; ti,bit-shift = <16>; ti,max-div = <16>; @@ -944,6 +1062,7 @@ auxclkreq0_ck: auxclkreq0_ck@210 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq0_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x0210>; @@ -952,6 +1071,7 @@ auxclkreq1_ck: auxclkreq1_ck@214 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq1_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x0214>; @@ -960,6 +1080,7 @@ auxclkreq2_ck: auxclkreq2_ck@218 { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq2_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x0218>; @@ -968,6 +1089,7 @@ auxclkreq3_ck: auxclkreq3_ck@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; + clock-output-names = "auxclkreq3_ck"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; ti,bit-shift = <2>; reg = <0x021c>; @@ -977,6 +1099,7 @@ &cm_core_aon { mpu_cm: mpu_cm@300 { compatible = "ti,omap4-cm"; + clock-output-names = "mpu_cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -984,6 +1107,7 @@ mpu_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "mpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -991,6 +1115,7 @@ dsp_cm: dsp_cm@400 { compatible = "ti,omap4-cm"; + clock-output-names = "dsp_cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -998,6 +1123,7 @@ dsp_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "dsp_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1005,6 +1131,7 @@ abe_cm: abe_cm@500 { compatible = "ti,omap4-cm"; + clock-output-names = "abe_cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1012,6 +1139,7 @@ abe_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "abe_clkctrl"; reg = <0x20 0x64>; #clock-cells = <2>; }; @@ -1022,6 +1150,7 @@ &cm_core { l3main1_cm: l3main1_cm@700 { compatible = "ti,omap4-cm"; + clock-output-names = "l3main1_cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1029,6 +1158,7 @@ l3main1_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3main1_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1036,6 +1166,7 @@ l3main2_cm: l3main2_cm@800 { compatible = "ti,omap4-cm"; + clock-output-names = "l3main2_cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1043,6 +1174,7 @@ l3main2_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3main2_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1050,6 +1182,7 @@ ipu_cm: ipu_cm@900 { compatible = "ti,omap4-cm"; + clock-output-names = "ipu_cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1057,6 +1190,7 @@ ipu_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "ipu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1064,6 +1198,7 @@ dma_cm: dma_cm@a00 { compatible = "ti,omap4-cm"; + clock-output-names = "dma_cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1071,6 +1206,7 @@ dma_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "dma_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1078,6 +1214,7 @@ emif_cm: emif_cm@b00 { compatible = "ti,omap4-cm"; + clock-output-names = "emif_cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1085,6 +1222,7 @@ emif_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "emif_clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; @@ -1092,6 +1230,7 @@ l4cfg_cm: l4cfg_cm@d00 { compatible = "ti,omap4-cm"; + clock-output-names = "l4cfg_cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1099,6 +1238,7 @@ l4cfg_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l4cfg_clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; @@ -1106,6 +1246,7 @@ l3instr_cm: l3instr_cm@e00 { compatible = "ti,omap4-cm"; + clock-output-names = "l3instr_cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1113,26 +1254,30 @@ l3instr_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3instr_clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; - l4per_cm: l4per_cm@1000 { + l4per_cm: clock@1000 { compatible = "ti,omap4-cm"; + clock-output-names = "l4per_cm"; reg = <0x1000 0x200>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1000 0x200>; l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4per", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4per_clkctrl"; reg = <0x20 0x15c>; #clock-cells = <2>; }; l4sec_clkctrl: clock@1a0 { - compatible = "ti,clkctrl-l4sec", "ti,clkctrl"; + compatible = "ti,clkctrl"; + clock-output-names = "l4sec_clkctrl"; reg = <0x1a0 0x3c>; #clock-cells = <2>; }; @@ -1140,6 +1285,7 @@ dss_cm: dss_cm@1400 { compatible = "ti,omap4-cm"; + clock-output-names = "dss_cm"; reg = <0x1400 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1147,6 +1293,7 @@ dss_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "dss_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1154,6 +1301,7 @@ gpu_cm: gpu_cm@1500 { compatible = "ti,omap4-cm"; + clock-output-names = "gpu_cm"; reg = <0x1500 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1161,6 +1309,7 @@ gpu_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "gpu_clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; @@ -1168,6 +1317,7 @@ l3init_cm: l3init_cm@1600 { compatible = "ti,omap4-cm"; + clock-output-names = "l3init_cm"; reg = <0x1600 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1175,6 +1325,7 @@ l3init_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "l3init_clkctrl"; reg = <0x20 0xd4>; #clock-cells = <2>; }; @@ -1184,6 +1335,7 @@ &prm { wkupaon_cm: wkupaon_cm@1900 { compatible = "ti,omap4-cm"; + clock-output-names = "wkupaon_cm"; reg = <0x1900 0x100>; #address-cells = <1>; #size-cells = <1>; @@ -1191,6 +1343,7 @@ wkupaon_clkctrl: clk@20 { compatible = "ti,clkctrl"; + clock-output-names = "wkupaon_clkctrl"; reg = <0x20 0x5c>; #clock-cells = <2>; }; @@ -1201,6 +1354,7 @@ fref_xtal_ck: fref_xtal_ck { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "fref_xtal_ck"; clocks = <&sys_clkin>; ti,bit-shift = <28>; reg = <0x14>; diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi index 31f59de5190b..7af41361c480 100644 --- a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi +++ b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi @@ -28,7 +28,7 @@ partitions { label = "rofs"; }; - rwfs@6000000 { + rwfs@2a00000 { reg = <0x2a00000 0x1600000>; // 22MB label = "rwfs"; }; diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi b/arch/arm/boot/dts/openbmc-flash-layout.dtsi index 6c26524e93e1..b47e14063c38 100644 --- a/arch/arm/boot/dts/openbmc-flash-layout.dtsi +++ b/arch/arm/boot/dts/openbmc-flash-layout.dtsi @@ -20,7 +20,7 @@ partitions { label = "kernel"; }; - rofs@c0000 { + rofs@4c0000 { reg = <0x4c0000 0x1740000>; label = "rofs"; }; diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts index 422958d13d42..03471d30bfd9 100644 --- a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts +++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index 0043e0040153..f17e25ac98dd 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -1,10 +1,5 @@ -/* - * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> /* * TODO: add Orion USB device port init when kernel.org support is added. diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts index 0ca6208a267d..d57859998350 100644 --- a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts +++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> * Copyright (C) Sylver Bruneau <sylver.bruneau@googlemail.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/; diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi index f667012b26ca..819f9efb7058 100644 --- a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi +++ b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi @@ -1,10 +1,5 @@ -/* - * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk> #include "orion5x.dtsi" diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi index d1ed71c60209..86b87fb26dc9 100644 --- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi +++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi @@ -1,10 +1,5 @@ -/* - * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> #include "orion5x.dtsi" diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts index ea081afa469d..4f4888ec9138 100644 --- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts @@ -1,10 +1,5 @@ -/* - * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk> /dts-v1/; diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts index 487324f7c54e..fd78aa02a3c5 100644 --- a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts +++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts @@ -1,10 +1,5 @@ -/* - * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> /dts-v1/; diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 61e631b3fd8b..2d41f5c166ee 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -1,10 +1,5 @@ -/* - * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) diff --git a/arch/arm/boot/dts/ox810se-wd-mbwe.dts b/arch/arm/boot/dts/ox810se-wd-mbwe.dts index 7e2fcb220aea..c59e06ff2423 100644 --- a/arch/arm/boot/dts/ox810se-wd-mbwe.dts +++ b/arch/arm/boot/dts/ox810se-wd-mbwe.dts @@ -103,6 +103,10 @@ }; }; +ða { + status = "okay"; +}; + &uart1 { status = "okay"; diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi index 0755e5864c4a..96c0745f7b70 100644 --- a/arch/arm/boot/dts/ox810se.dtsi +++ b/arch/arm/boot/dts/ox810se.dtsi @@ -81,6 +81,24 @@ ranges; interrupt-parent = <&intc>; + etha: ethernet@40400000 { + compatible = "oxsemi,ox810se-dwmac", "snps,dwmac"; + reg = <0x40400000 0x2000>; + interrupts = <8>; + interrupt-names = "macirq"; + mac-address = [000000000000]; /* Filled in by U-Boot */ + phy-mode = "rgmii"; + + clocks = <&stdclk 6>, <&gmacclk>; + clock-names = "gmac", "stmmaceth"; + resets = <&reset 6>; + + /* Regmap for sys registers */ + oxsemi,sys-ctrl = <&sys>; + + status = "disabled"; + }; + apb-bridge@44000000 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi index 90846a7655b4..dde4364892bf 100644 --- a/arch/arm/boot/dts/ox820.dtsi +++ b/arch/arm/boot/dts/ox820.dtsi @@ -287,7 +287,7 @@ clocks = <&armclk>; }; - gic: gic@1000 { + gic: interrupt-controller@1000 { compatible = "arm,arm11mp-gic"; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/pxa25x.dtsi index a248bf038033..5f8300e356ad 100644 --- a/arch/arm/boot/dts/pxa25x.dtsi +++ b/arch/arm/boot/dts/pxa25x.dtsi @@ -38,9 +38,12 @@ compatible = "marvell,pdma-1.0"; reg = <0x40000000 0x10000>; interrupts = <25>; - #dma-channels = <16>; #dma-cells = <2>; + /* For backwards compatibility: */ + #dma-channels = <16>; + dma-channels = <16>; #dma-requests = <40>; + dma-requests = <40>; status = "okay"; }; diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index ccbecad9c5c7..a2cbfb3be609 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -12,9 +12,12 @@ compatible = "marvell,pdma-1.0"; reg = <0x40000000 0x10000>; interrupts = <25>; - #dma-channels = <32>; #dma-cells = <2>; + /* For backwards compatibility: */ + #dma-channels = <32>; + dma-channels = <32>; #dma-requests = <75>; + dma-requests = <75>; status = "okay"; }; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi index 8a6721d436bd..147c99191dc2 100644 --- a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi +++ b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi @@ -189,31 +189,31 @@ regulators { regulator-v3 { - regulator-compatible= "V3(DCDC)"; + regulator-compatible = "V3(DCDC)"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1800000>; }; regulator-v4 { - regulator-compatible= "V4(DCDC)"; + regulator-compatible = "V4(DCDC)"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1800000>; }; regulator-v5 { - regulator-compatible= "V5(LDO)"; + regulator-compatible = "V5(LDO)"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2000000>; }; reg_vcc_sdio: regulator-v6 { - regulator-compatible= "V6(LDO)"; + regulator-compatible = "V6(LDO)"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; regulator-v7 { - regulator-compatible= "V7(LDO)"; + regulator-compatible = "V7(LDO)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index d19674812cd2..f9c216f91865 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -122,9 +122,12 @@ compatible = "marvell,pdma-1.0"; reg = <0x40000000 0x10000>; interrupts = <25>; - #dma-channels = <32>; #dma-cells = <2>; + /* For backwards compatibility: */ + #dma-channels = <32>; + dma-channels = <32>; #dma-requests = <100>; + dma-requests = <100>; status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts b/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts new file mode 100644 index 000000000000..215613c65250 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Luca Weiss <luca@z3ntu.xyz> + */ + +/dts-v1/; + +#include "qcom-msm8226.dtsi" +#include "qcom-pm8226.dtsi" + +/delete-node/ &adsp_region; + +/ { + model = "ASUS ZenWatch 2"; + compatible = "asus,sparrow", "qcom,apq8026"; + chassis-type = "watch"; + qcom,msm-id = <199 0x20000>; + qcom,board-id = <8 3005>; + + reserved-memory { + sbl_region: sbl@2f00000 { + reg = <0x02f00000 0x100000>; + no-map; + }; + external_image_region: external-image@3100000 { + reg = <0x3100000 0x200000>; + no-map; + }; + peripheral_region: peripheral@3300000 { + reg = <0x3300000 0x600000>; + no-map; + }; + adsp_region: adsp@3900000 { + reg = <0x3900000 0x1400000>; + no-map; + }; + modem_region: modem@4d00000 { + reg = <0x4d00000 0x1b00000>; + no-map; + }; + modem_efs_region: modem-efs@7f00000 { + reg = <0x7f00000 0x100000>; + no-map; + }; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_default_state>; + }; +}; + +&adsp { + status = "okay"; +}; + +&blsp1_uart1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart1_default_state>; + + bluetooth { + compatible = "brcm,bcm43430a1-bt"; + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_state>; + + host-wakeup-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>; + }; +}; + +&pm8226_vib { + status = "okay"; +}; + +&rpm_requests { + pm8226-regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + }; + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1337500>; + }; + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l7: l7 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + }; + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + pm8226_l15: l15 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + pm8226_l27: l27 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; +}; + +&sdhc_3 { + status = "okay"; + + max-frequency = <100000000>; + non-removable; + + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pm8226_l6>; + + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_hostwake_default_state>; + }; +}; + +&smbb { + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <350000>; + qcom,fast-charge-safe-voltage = <4430000>; + qcom,fast-charge-high-threshold-voltage = <4400000>; + qcom,auto-recharge-threshold-voltage = <4300000>; + qcom,minimum-input-voltage = <4400000>; +}; + +&tlmm { + blsp1_uart1_default_state: blsp1-uart1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <8>; + bias-disable; + }; + + bluetooth_default_state: bluetooth-default-state { + pins = "gpio48", "gpio61"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + input-enable; + }; + + wlan_hostwake_default_state: wlan-hostwake-default-state { + pins = "gpio46"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + wlan_regulator_default_state: wlan-regulator-default-state { + pins = "gpio35"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&usb { + status = "okay"; + extcon = <&smbb>; + dr_mode = "peripheral"; +}; + +&usb_hs_phy { + extcon = <&smbb>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; diff --git a/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts b/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts index f350c4e8c194..193569f0ca5f 100644 --- a/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts +++ b/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts @@ -8,6 +8,8 @@ #include "qcom-msm8226.dtsi" #include "qcom-pm8226.dtsi" +/delete-node/ &adsp_region; + / { model = "LG G Watch R"; compatible = "lg,lenok", "qcom,apq8026"; @@ -16,11 +18,46 @@ aliases { serial0 = &blsp1_uart3; + serial1 = &blsp1_uart4; }; chosen { stdout-path = "serial0:115200n8"; }; + + reserved-memory { + adsp_region: adsp@3300000 { + reg = <0x03300000 0x1400000>; + no-map; + }; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + gpio = <&tlmm 46 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_default_state>; + }; +}; + +&adsp { + status = "okay"; +}; + +&blsp1_i2c1 { + status = "okay"; + + fuel-gauge@55 { + compatible = "ti,bq27421"; + reg = <0x55>; + }; }; &blsp1_i2c5 { @@ -57,14 +94,30 @@ status = "okay"; }; +&blsp1_uart4 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart4_default_state>; + + bluetooth { + compatible = "brcm,bcm43430a0-bt"; + + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_state>; + + host-wakeup-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + }; +}; + &rpm_requests { pm8226-regulators { compatible = "qcom,rpm-pm8226-regulators"; - pm8226_s1: s1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1275000>; - }; pm8226_s3: s3 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; @@ -195,24 +248,55 @@ bus-width = <8>; non-removable; +}; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; +&sdhc_3 { + status = "okay"; + + max-frequency = <100000000>; + non-removable; + + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pm8226_l6>; + + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "brcm,bcm43430a0-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_hostwake_default_state>; + }; +}; + +&smbb { + qcom,fast-charge-safe-current = <450000>; + qcom,fast-charge-current-limit = <400000>; + qcom,fast-charge-safe-voltage = <4350000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,auto-recharge-threshold-voltage = <4240000>; + qcom,minimum-input-voltage = <4450000>; }; &tlmm { - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <10>; - bias-disable; - }; + blsp1_uart4_default_state: blsp1-uart4-default-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "blsp_uart4"; + drive-strength = <8>; + bias-disable; + }; - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; + bluetooth_default_state: bluetooth-default-state { + pins = "gpio47", "gpio48"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; }; touch_pins: touch { @@ -234,4 +318,31 @@ output-high; }; }; + + wlan_hostwake_default_state: wlan-hostwake-default-state { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + wlan_regulator_default_state: wlan-regulator-default-state { + pins = "gpio46"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&usb { + status = "okay"; + extcon = <&smbb>; + dr_mode = "peripheral"; +}; + +&usb_hs_phy { + extcon = <&smbb>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; }; diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index d664ccd454c5..573e4dc66bb0 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> #include "qcom-msm8660.dtsi" @@ -83,7 +84,7 @@ soc { pinctrl@800000 { - /* eMMMC pins, all 8 data lines connected */ + /* eMMC pins, all 8 data lines connected */ dragon_sdcc1_pins: sdcc1 { mux { pins = "gpio159", "gpio160", "gpio161", @@ -158,6 +159,19 @@ }; }; + dragon_gsbi3_i2c_pins: gsbi3_i2c { + mux { + pins = "gpio43", "gpio44"; + function = "gsbi3"; + }; + pinconf { + pins = "gpio43", "gpio44"; + drive-strength = <8>; + /* These have external pull-up 2.2kOhm to 1.8V */ + bias-disable; + }; + }; + dragon_gsbi8_i2c_pins: gsbi8_i2c { mux { pins = "gpio64", "gpio65"; @@ -239,6 +253,22 @@ bias-pull-up; }; }; + + dragon_tma340_gpios: tma340 { + reset { + /* RESET line, TS_ATTN, WAKE_CTP */ + pins = "gpio58"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + irq { + pins = "gpio61"; /* IRQ line */ + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; qcom,ssbi@500000 { @@ -273,7 +303,7 @@ }; gpio@150 { - dragon_ethernet_gpios: ethernet-gpios { + dragon_ethernet_gpios: ethernet-state { pinconf { pins = "gpio7"; function = "normal"; @@ -282,7 +312,7 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_bmp085_gpios: bmp085-gpios { + dragon_bmp085_gpios: bmp085-state { pinconf { pins = "gpio16"; function = "normal"; @@ -291,7 +321,7 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_mpu3050_gpios: mpu3050-gpios { + dragon_mpu3050_gpios: mpu3050-state { pinconf { pins = "gpio17"; function = "normal"; @@ -300,7 +330,7 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_sdcc3_gpios: sdcc3-gpios { + dragon_sdcc3_gpios: sdcc3-state { pinconf { pins = "gpio22"; function = "normal"; @@ -309,7 +339,7 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_sdcc5_gpios: sdcc5-gpios { + dragon_sdcc5_gpios: sdcc5-state { pinconf { pins = "gpio26"; function = "normal"; @@ -319,7 +349,7 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_ak8975_gpios: ak8975-gpios { + dragon_ak8975_gpios: ak8975-state { pinconf { pins = "gpio33"; function = "normal"; @@ -328,9 +358,9 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_cm3605_gpios: cm3605-gpios { + dragon_cm3605_gpios: cm3605-state { /* Pin 34 connected to the proxy IRQ */ - pinconf_gpio34 { + gpio34-pins { pins = "gpio34"; function = "normal"; input-enable; @@ -338,7 +368,7 @@ power-source = <PM8058_GPIO_S3>; }; /* Pin 35 connected to ASET */ - pinconf_gpio35 { + gpio35-pins { pins = "gpio35"; function = "normal"; output-high; @@ -346,7 +376,7 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_veth_gpios: veth-gpios { + dragon_veth_gpios: veth-state { pinconf { pins = "gpio40"; function = "normal"; @@ -416,6 +446,7 @@ compatible = "qcom,pm8058-led"; reg = <0x131>; label = "pm8058:red"; + color = <LED_COLOR_ID_RED>; default-state = "off"; }; led@132 { @@ -426,6 +457,7 @@ compatible = "qcom,pm8058-led"; reg = <0x132>; label = "pm8058:yellow"; + color = <LED_COLOR_ID_YELLOW>; default-state = "off"; linux,default-trigger = "mmc0"; }; @@ -433,12 +465,53 @@ compatible = "qcom,pm8058-led"; reg = <0x133>; label = "pm8058:green"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; default-state = "on"; linux,default-trigger = "heartbeat"; }; }; }; + gsbi@16200000 { + qcom,mode = <GSBI_PROT_I2C>; + status = "okay"; + + gsbi3_i2c: i2c@16280000 { + pinctrl-names = "default"; + pinctrl-0 = <&dragon_gsbi3_i2c_pins>; + status = "okay"; + + touchscreen@24 { + compatible = "cypress,cy8ctma340"; + reg = <0x24>; + /* Certainly we can do at least 400 kHz */ + clock-frequency = <400000>; + /* IRQ on GPIO61 called /CTP_INT */ + interrupt-parent = <&tlmm>; + interrupts = <61 IRQ_TYPE_EDGE_FALLING>; + /* + * The I2C bus is using a PCA9306 level translator from L16A + * to L2B so these two voltages are needed and L16A is + * kind of the IO voltage, however L16Aisn't really fed to + * the TMA340, which relies entirely on L2B (PM8901 L2). + */ + vcpin-supply = <&pm8058_l16>; + vdd-supply = <&pm8901_l2>; + /* GPIO58, called WAKE_CTP */ + reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + active-interval-ms = <0>; + touch-timeout-ms = <255>; + lowpower-interval-ms = <10>; + bootloader-key = /bits/ 8 <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_tma340_gpios>; + }; + }; + }; + gsbi@19800000 { status = "okay"; qcom,mode = <GSBI_PROT_I2C>; @@ -629,7 +702,8 @@ bias-pull-down; }; l2 { - regulator-min-microvolt = <2850000>; + /* TMA340 requires strictly 3.3V */ + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; bias-pull-down; }; @@ -674,14 +748,14 @@ bias-pull-down; }; - /* LVS0 thru 3 and mvs0 are just switches */ + /* LVS0 thru 3 and mvs are just switches */ lvs0 { regulator-always-on; }; lvs1 { }; lvs2 { }; lvs3 { }; - mvs0 {}; + mvs { }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index 9a835335bf78..fee278e32cb6 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -24,9 +24,9 @@ ramoops@88d00000{ compatible = "ramoops"; reg = <0x88d00000 0x100000>; - record-size = <0x00020000>; - console-size = <0x00020000>; - ftrace-size = <0x00020000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; }; }; @@ -44,12 +44,12 @@ gpio-keys { compatible = "gpio-keys"; - volume_up { + key-volume-up { label = "Volume Up"; gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>; linux,code = <KEY_VOLUMEUP>; }; - volume_down { + key-volume-down { label = "Volume Down"; gpios = <&pm8921_gpio 38 GPIO_ACTIVE_HIGH>; linux,code = <KEY_VOLUMEDOWN>; @@ -98,8 +98,8 @@ * tabla2x-slim-VDDIO_CDC */ s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; qcom,switch-mode-frequency = <3200000>; regulator-always-on; }; @@ -212,13 +212,12 @@ }; }; - dsi0: mdss_dsi@4700000 { + dsi0: dsi@4700000 { status = "okay"; vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/ vdd-supply = <&pm8921_l8>; vddio-supply = <&pm8921_lvs7>; avdd-supply = <&pm8921_l11>; - vcss-supply = <&ext_3p3v>; panel@0 { reg = <0>; @@ -342,17 +341,17 @@ }; }; - imem@2a03f000 { - compatible = "syscon", "simple-mfd"; + sram@2a03f000 { + compatible = "qcom,apq8064-imem", "syscon", "simple-mfd"; reg = <0x2a03f000 0x1000>; reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x65c>; - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts index e068a8d0adf0..529629a0a9dc 100644 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -82,8 +82,8 @@ }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; qcom,switch-mode-frequency = <3200000>; }; @@ -196,8 +196,8 @@ qcom,ssbi@500000 { pmic@0 { gpio@150 { - wlan_default_gpios: wlan-gpios { - pios { + wlan_default_gpios: wlan-gpios-state { + pinconf { pins = "gpio43"; function = "normal"; bias-disable; @@ -215,7 +215,7 @@ vdda_refclk-supply = <&v3p3_fixed>; pinctrl-0 = <&pcie_pins>; pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; }; amba { @@ -230,9 +230,9 @@ sdcc3: mmc@12180000 { status = "okay"; vmmc-supply = <&v3p3_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; }; /* WLAN */ sdcc4: mmc@121c0000 { diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 2638b380be20..a7f90217661b 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-apq8064-v2.0.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { @@ -39,6 +40,7 @@ led@1 { label = "apq8064:green:user1"; + color = <LED_COLOR_ID_GREEN>; gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>; default-state = "on"; }; @@ -108,8 +110,8 @@ }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; qcom,switch-mode-frequency = <3200000>; }; @@ -240,8 +242,8 @@ }; sata0: sata@29000000 { - status = "okay"; - target-supply = <&pm8921_s4>; + status = "okay"; + target-supply = <&pm8921_s4>; }; /* OTG */ @@ -285,14 +287,14 @@ vdda_refclk-supply = <&ext_3p3v>; pinctrl-0 = <&pcie_pins>; pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; }; qcom,ssbi@500000 { pmic@0 { gpio@150 { - wlan_default_gpios: wlan-gpios { - pios { + wlan_default_gpios: wlan-gpios-state { + pinconf { pins = "gpio43"; function = "normal"; bias-disable; @@ -300,8 +302,8 @@ }; }; - notify_led: nled { - pios { + notify_led: nled-state { + pinconf { pins = "gpio18"; function = "normal"; bias-disable; @@ -324,9 +326,9 @@ sdcc3: mmc@12180000 { status = "okay"; vmmc-supply = <&pm8921_l6>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; }; /* WLAN */ sdcc4: mmc@121c0000 { @@ -341,7 +343,6 @@ status = "okay"; core-vdda-supply = <&pm8921_hdmi_switch>; - hdmi-mux-supply = <&ext_3p3v>; hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi index cbe42c4153a0..b4d286a6fab1 100644 --- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi @@ -76,7 +76,7 @@ pinconf { pins = "gpio20", "gpio21"; drive-strength = <2>; - bias-disable = <0>; + bias-disable; }; }; @@ -116,7 +116,7 @@ pinconf { pins = "gpio24", "gpio25"; drive-strength = <2>; - bias-disable = <0>; + bias-disable; }; }; @@ -141,7 +141,7 @@ pinconf { pins = "gpio8", "gpio9"; drive-strength = <2>; - bias-disable = <0>; + bias-disable; }; }; @@ -166,7 +166,7 @@ pinconf { pins = "gpio12", "gpio13"; drive-strength = <2>; - bias-disable = <0>; + bias-disable; }; }; @@ -229,7 +229,7 @@ pinconf { pins = "gpio16", "gpio17"; drive-strength = <2>; - bias-disable = <0>; + bias-disable; }; }; @@ -282,7 +282,7 @@ pinconf { pins = "gpio84", "gpio85"; drive-strength = <2>; - bias-disable = <0>; + bias-disable; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts index 0cee62c7b8b0..c07c5474750d 100644 --- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts +++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts @@ -23,28 +23,28 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - camera-focus { + key-camera-focus { label = "camera_focus"; gpios = <&pm8921_gpio 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_CAMERA_FOCUS>; }; - camera-snapshot { + key-camera-snapshot { label = "camera_snapshot"; gpios = <&pm8921_gpio 4 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_CAMERA>; }; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pm8921_gpio 29 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_VOLUMEDOWN>; }; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm8921_gpio 35 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -334,7 +334,7 @@ qcom,ssbi@500000 { pmic@0 { gpio@150 { - gpio_keys_pin_a: gpio-keys-pin-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio3", "gpio4", "gpio29", "gpio35"; function = "normal"; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 4d562c94c31c..942aa2278355 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -2,6 +2,7 @@ /dts-v1/; #include <dt-bindings/clock/qcom,gcc-msm8960.h> +#include <dt-bindings/clock/qcom,lcc-msm8960.h> #include <dt-bindings/reset/qcom,gcc-msm8960.h> #include <dt-bindings/clock/qcom,mmcc-msm8960.h> #include <dt-bindings/clock/qcom,rpmcc.h> @@ -105,7 +106,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&gcc 7>; + thermal-sensors = <&tsens 7>; coefficients = <1199 0>; trips { @@ -126,7 +127,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&gcc 8>; + thermal-sensors = <&tsens 8>; coefficients = <1132 0>; trips { @@ -147,7 +148,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&gcc 9>; + thermal-sensors = <&tsens 9>; coefficients = <1199 0>; trips { @@ -168,7 +169,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&gcc 10>; + thermal-sensors = <&tsens 10>; coefficients = <1132 0>; trips { @@ -227,7 +228,7 @@ smd { compatible = "qcom,smd"; - modem@0 { + modem-edge { interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&l2cc 8 3>; @@ -236,7 +237,7 @@ status = "disabled"; }; - q6@1 { + q6-edge { interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&l2cc 8 15>; @@ -245,7 +246,7 @@ status = "disabled"; }; - dsps@3 { + dsps-edge { interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&sps_sic_non_secure 0x4080 0>; @@ -254,7 +255,7 @@ status = "disabled"; }; - riva@6 { + riva-edge { interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&l2cc 8 25>; @@ -315,7 +316,7 @@ firmware { scm { - compatible = "qcom,scm-apq8064"; + compatible = "qcom,scm-apq8064", "qcom,scm"; clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; clock-names = "core"; @@ -430,8 +431,8 @@ }; sps_sic_non_secure: sps-sic-non-secure@12100000 { - compatible = "syscon"; - reg = <0x12100000 0x10000>; + compatible = "syscon"; + reg = <0x12100000 0x10000>; }; gsbi1: gsbi@12440000 { @@ -796,27 +797,41 @@ }; qfprom: qfprom@700000 { - compatible = "qcom,qfprom"; - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; + compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ranges; - tsens_calib: calib { + tsens_calib: calib@404 { reg = <0x404 0x10>; }; - tsens_backup: backup_calib { + tsens_backup: backup_calib@414 { reg = <0x414 0x10>; }; }; gcc: clock-controller@900000 { - compatible = "qcom,gcc-apq8064"; + compatible = "qcom,gcc-apq8064", "syscon"; reg = <0x00900000 0x4000>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; - #thermal-sensor-cells = <1>; + clocks = <&cxo_board>, + <&pxo_board>, + <&lcc PLL4>; + clock-names = "cxo", "pxo", "pll4"; + + tsens: thermal-sensor { + compatible = "qcom,msm8960-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; }; lcc: clock-controller@28000000 { @@ -824,33 +839,66 @@ reg = <0x28000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, <0>, + <0>, <0>, + <0>; + clock-names = "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; }; mmcc: clock-controller@4000000 { compatible = "qcom,mmcc-apq8064"; reg = <0x4000000 0x1000>; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; }; l2cc: clock-controller@2011000 { - compatible = "syscon"; - reg = <0x2011000 0x1000>; + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; }; rpm@108000 { - compatible = "qcom,rpm-apq8064"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; + compatible = "qcom,rpm-apq8064"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; - interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ack", "err", "wakeup"; + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ack", "err", "wakeup"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; + compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; }; regulators { @@ -1002,43 +1050,43 @@ }; sata_phy0: phy@1b400000 { - compatible = "qcom,apq8064-sata-phy"; - status = "disabled"; - reg = <0x1b400000 0x200>; - reg-names = "phy_mem"; - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - #phy-cells = <0>; + compatible = "qcom,apq8064-sata-phy"; + status = "disabled"; + reg = <0x1b400000 0x200>; + reg-names = "phy_mem"; + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + #phy-cells = <0>; }; sata0: sata@29000000 { - compatible = "qcom,apq8064-ahci", "generic-ahci"; - status = "disabled"; - reg = <0x29000000 0x180>; - interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_iface", - "iface", - "bus", - "rxoob", - "core_pmalive"; - - assigned-clocks = <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; - - phys = <&sata_phy0>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; + compatible = "qcom,apq8064-ahci", "generic-ahci"; + status = "disabled"; + reg = <0x29000000 0x180>; + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_iface", + "iface", + "bus", + "rxoob", + "core_pmalive"; + + assigned-clocks = <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + phys = <&sata_phy0>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; }; /* Temporary fixed regulator */ - sdcc1bam:dma@12402000{ + sdcc1bam: dma-controller@12402000{ compatible = "qcom,bam-v1.3.0"; reg = <0x12402000 0x8000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; @@ -1048,7 +1096,7 @@ qcom,ee = <0>; }; - sdcc3bam:dma@12182000{ + sdcc3bam: dma-controller@12182000{ compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; @@ -1058,7 +1106,7 @@ qcom,ee = <0>; }; - sdcc4bam:dma@121c2000{ + sdcc4bam: dma-controller@121c2000{ compatible = "qcom,bam-v1.3.0"; reg = <0x121c2000 0x8000>; interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; @@ -1074,18 +1122,18 @@ #size-cells = <1>; ranges; sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - pinctrl-names = "default"; - pinctrl-0 = <&sdcc1_pins>; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + pinctrl-names = "default"; + pinctrl-0 = <&sdcc1_pins>; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; + reg = <0x12400000 0x2000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; @@ -1094,36 +1142,36 @@ }; sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <192000000>; + max-frequency = <192000000>; no-1-8-v; dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; dma-names = "tx", "rx"; }; sdcc4: mmc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x2000>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x121c0000 0x2000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <48000000>; + max-frequency = <48000000>; dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; dma-names = "tx", "rx"; pinctrl-names = "default"; @@ -1238,7 +1286,7 @@ reg = <0x5700000 0x70>; }; - dsi0: mdss_dsi@4700000 { + dsi0: dsi@4700000 { compatible = "qcom,mdss-dsi-ctrl"; label = "MDSS DSI CTRL->0"; #address-cells = <1>; @@ -1268,6 +1316,9 @@ <&dsi0_phy 1>; syscon-sfpb = <&mmss_sfpb>; phys = <&dsi0_phy>; + phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1296,9 +1347,10 @@ <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk", "ref"; + clock-names = "iface", "ref"; clocks = <&mmcc DSI_M_AHB_CLK>, <&pxo_board>; + status = "disabled"; }; @@ -1367,11 +1419,11 @@ }; pcie: pci@1b500000 { - compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; - reg = <0x1b500000 0x1000 - 0x1b502000 0x80 - 0x1b600000 0x100 - 0x0ff00000 0x100000>; + compatible = "qcom,pcie-apq8064"; + reg = <0x1b500000 0x1000>, + <0x1b502000 0x80>, + <0x1b600000 0x100>, + <0x0ff00000 0x100000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; @@ -1379,8 +1431,8 @@ num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ - 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */ + ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */ + <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; @@ -1417,7 +1469,6 @@ "slave_iface"; phys = <&hdmi_phy>; - phy-names = "hdmi-phy"; ports { #address-cells = <1>; @@ -1545,7 +1596,7 @@ qcom,mmio = <&riva>; - bt { + bluetooth { compatible = "qcom,wcnss-bt"; }; diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 83793b835d40..91716298ec5e 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/gpio/gpio.h> #include "qcom-msm8974.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" @@ -16,331 +17,293 @@ chosen { stdout-path = "serial0:115200n8"; }; +}; + +&blsp1_uart2 { + status = "okay"; +}; - soc { - serial@f991e000 { +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <200000>; + + eeprom: eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <32>; + read-only; + }; +}; + +&otg { + status = "okay"; + + phys = <&usb_hs2_phy>; + phy-select = <&tcsr 0xb000 1>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@b { status = "okay"; + v3p3-supply = <&pm8941_l24>; + v1p8-supply = <&pm8941_l6>; + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x63>; + }; + }; +}; + +&rpm_requests { + pm8841-regulators { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; }; - sdhci@f9824900 { - bus-width = <8>; - non-removable; - status = "okay"; + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; + pm8841_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; + pm8841_s4: s4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; }; + }; - sdhci@f98a4900 { - cd-gpios = <&msmgpio 62 0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - bus-width = <4>; - status = "okay"; + pm8941-regulators { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vin_5vs-supply = <&pm8941_5v>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; }; - usb@f9a55000 { - status = "okay"; - phys = <&usb_hs2_phy>; - phy-select = <&tcsr 0xb000 1>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - hnp-disable; - srp-disable; - adp-disable; - ulpi { - phy@b { - status = "okay"; - v3p3-supply = <&pm8941_l24>; - v1p8-supply = <&pm8941_l6>; - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x63>; - }; - }; - }; - - - pinctrl@fd510000 { - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - }; - }; - - spi8_default: spi8_default { - mosi { - pins = "gpio45"; - function = "blsp_spi8"; - }; - miso { - pins = "gpio46"; - function = "blsp_spi8"; - }; - cs { - pins = "gpio47"; - function = "blsp_spi8"; - }; - clk { - pins = "gpio48"; - function = "blsp_spi8"; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - }; - - i2c@f9967000 { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c11_pins>; - pinctrl-names = "default"; + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - eeprom: eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - read-only; - }; + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; }; }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "okay"; + + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; +}; + +&tlmm { + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_on: sdc2-on { + clk { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vin_5vs-supply = <&pm8941_5v>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-system-load = <200000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; + cd { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 52240fc7a1a6..f2fb7c975af8 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -95,7 +95,7 @@ firmware { scm { - compatible = "qcom,scm"; + compatible = "qcom,scm-apq8084", "qcom,scm"; clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; clock-names = "core", "bus", "iface"; }; @@ -239,11 +239,16 @@ reg = <0xf9011000 0x1000>; }; + sram@fc190000 { + compatible = "qcom,apq8084-rpm-stats"; + reg = <0xfc190000 0x10000>; + }; + qfprom: qfprom@fc4bc000 { + compatible = "qcom,apq8084-qfprom", "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - compatible = "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; tsens_calib: calib@d0 { reg = <0xd0 0x18>; }; @@ -383,14 +388,9 @@ reg = <0xfc400000 0x4000>; }; - tcsr_mutex_regs: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x80>; + tcsr_mutex: hwlock@fd484000 { + compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex"; + reg = <0xfd484000 0x1000>; #hwlock-cells = <1>; }; @@ -419,29 +419,29 @@ status = "disabled"; }; - sdhci@f9824900 { + mmc@f9824900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; - sdhci@f98a4900 { + mmc@f98a4900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; @@ -470,7 +470,7 @@ qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm_requests { + rpm-requests { compatible = "qcom,rpm-apq8084"; qcom,smd-channels = "rpm_requests"; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts index 028ac8e24797..cf7da1ab177c 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT +#include <dt-bindings/leds/common.h> #include "qcom-ipq4018-ap120c-ac.dtsi" / { @@ -10,17 +11,22 @@ power { label = "ap120c-ac:green:power"; + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_GREEN>; gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; default-state = "on"; }; wlan { label = "ap120c-ac:green:wlan"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_GREEN>; gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; }; support { label = "ap120c-ac:green:support"; + color = <LED_COLOR_ID_GREEN>; gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; panic-indicator; }; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts index b7916fc26d68..c4f89b712fd9 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT +#include <dt-bindings/leds/common.h> #include "qcom-ipq4018-ap120c-ac.dtsi" / { @@ -8,18 +9,24 @@ status: status { label = "ap120c-ac:blue:status"; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; default-state = "keep"; }; wlan2g { label = "ap120c-ac:green:wlan2g"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_GREEN>; gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tpt"; }; wlan5g { label = "ap120c-ac:red:wlan5g"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_RED>; gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy1tpt"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi index 1f3b1ce82108..af9a26fb5d4a 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi @@ -11,7 +11,7 @@ keys { compatible = "gpio-keys"; - reset { + key-reset { label = "reset"; gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; linux,code = <KEY_RESTART>; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index 0c10d9e096db..0505270cf508 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -14,6 +14,7 @@ * */ +#include <dt-bindings/gpio/gpio.h> #include "qcom-ipq4019.dtsi" / { @@ -64,7 +65,7 @@ }; }; - blsp_dma: dma@7884000 { + blsp_dma: dma-controller@7884000 { status = "okay"; }; @@ -72,7 +73,7 @@ pinctrl-0 = <&spi_0_pins>; pinctrl-names = "default"; status = "okay"; - cs-gpios = <&tlmm 54 0>; + cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; mx25l25635e@0 { #address-cells = <1>; @@ -89,7 +90,7 @@ status = "okay"; }; - cryptobam: dma@8e04000 { + cryptobam: dma-controller@8e04000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts index a7b1201dd614..79b0c6318e52 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts @@ -8,7 +8,7 @@ compatible = "qcom,ipq4019-dk04.1-c1", "qcom,ipq4019"; soc { - dma@7984000 { + dma-controller@7984000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi index 7a337dc08741..a63b3778636d 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi @@ -79,7 +79,7 @@ status = "okay"; }; - dma@7884000 { + dma-controller@7884000 { status = "okay"; }; @@ -87,20 +87,20 @@ pinctrl-0 = <&spi_0_pins>; pinctrl-names = "default"; status = "okay"; - cs-gpios = <&tlmm 12 0>; + cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <24000000>; }; }; pci@40000000 { status = "okay"; - perst-gpio = <&tlmm 38 0x1>; + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; qpic-nand@79b0000 { diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts index 06f9f2cb2fe9..ea2987fcbff8 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2018, The Linux Foundation. All rights reserved. +#include <dt-bindings/gpio/gpio.h> #include "qcom-ipq4019-ap.dk07.1.dtsi" / { @@ -10,7 +11,7 @@ soc { pci@40000000 { status = "okay"; - perst-gpio = <&tlmm 38 0x1>; + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; spi@78b6000 { @@ -50,13 +51,13 @@ pinctrl-0 = <&spi_0_pins>; pinctrl-names = "default"; status = "okay"; - cs-gpios = <&tlmm 12 0>; + cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <24000000>; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi index 94872518b5a2..0107f552f520 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi @@ -52,7 +52,7 @@ status = "okay"; }; - dma@7884000 { + dma-controller@7884000 { status = "okay"; }; @@ -62,7 +62,7 @@ status = "okay"; }; - dma@7984000 { + dma-controller@7984000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 7dec0553636e..b23591110bd2 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -142,7 +142,8 @@ clocks { sleep_clk: sleep_clk { compatible = "fixed-clock"; - clock-frequency = <32768>; + clock-frequency = <32000>; + clock-output-names = "gcc_sleep_clk_src"; #clock-cells = <0>; }; @@ -155,7 +156,7 @@ firmware { scm { - compatible = "qcom,scm-ipq4019"; + compatible = "qcom,scm-ipq4019", "qcom,scm"; }; }; @@ -186,6 +187,7 @@ gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq4019"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x1800000 0x60000>; }; @@ -219,19 +221,20 @@ status = "disabled"; }; - sdhci: sdhci@7824900 { + sdhci: mmc@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x11c>, <0x7824000 0x800>; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; bus-width = <8>; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_DCD_XO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; - blsp_dma: dma@7884000 { + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07884000 0x23000>; interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; @@ -251,8 +254,8 @@ clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 5>, <&blsp_dma 4>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -265,8 +268,8 @@ clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 7>, <&blsp_dma 6>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -274,13 +277,13 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b7000 0x600>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -288,17 +291,17 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b8000 0x600>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; - dmas = <&blsp_dma 11>, <&blsp_dma 10>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; status = "disabled"; }; - cryptobam: dma@8e04000 { + cryptobam: dma-controller@8e04000 { compatible = "qcom,bam-v1.7.0"; reg = <0x08e04000 0x20000>; interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; @@ -380,8 +383,8 @@ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 1>, <&blsp_dma 0>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 0>, <&blsp_dma 1>; + dma-names = "tx", "rx"; }; blsp1_uart2: serial@78b0000 { @@ -392,8 +395,8 @@ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 3>, <&blsp_dma 2>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; }; watchdog: watchdog@b017000 { @@ -410,7 +413,7 @@ }; pcie0: pci@40000000 { - compatible = "qcom,pcie-ipq4019", "snps,dw-pcie"; + compatible = "qcom,pcie-ipq4019"; reg = <0x40000000 0xf1d 0x40000f20 0xa8 0x80000 0x2000 @@ -469,7 +472,7 @@ status = "disabled"; }; - qpic_bam: dma@7984000 { + qpic_bam: dma-controller@7984000 { compatible = "qcom,bam-v1.7.0"; reg = <0x7984000 0x1a000>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; @@ -644,7 +647,7 @@ clocks = <&gcc GCC_USB3_MASTER_CLK>, <&gcc GCC_USB3_SLEEP_CLK>, <&gcc GCC_USB3_MOCK_UTMI_CLK>; - clock-names = "master", "sleep", "mock_utmi"; + clock-names = "core", "sleep", "mock_utmi"; ranges; status = "disabled"; diff --git a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi new file mode 100644 index 000000000000..9d06255104c7 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "qcom-ipq8062.dtsi" + +&rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; + + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq8062.dtsi b/arch/arm/boot/dts/qcom-ipq8062.dtsi new file mode 100644 index 000000000000..5d3ebd3e2e51 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "qcom-ipq8064-v2.0.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8062"; + compatible = "qcom,ipq8062", "qcom,ipq8064"; +}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index b63d01d10189..a654d3c22c4f 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -7,12 +7,6 @@ soc { pinmux@800000 { - i2c4_pins: i2c4_pinmux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - bias-disable; - }; - buttons_pins: buttons_pins { mux { pins = "gpio54", "gpio65"; diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts index 596d129d4a95..5a65cce2500c 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-ipq8064.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> / { model = "MikroTik RB3011UiAS-RM"; @@ -187,12 +188,12 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&buttons_pins>; pinctrl-names = "default"; - button@1 { + button { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>; @@ -208,6 +209,7 @@ led@7 { label = "rb3011:green:user"; + color = <LED_COLOR_ID_GREEN>; gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; default-state = "off"; }; @@ -305,15 +307,6 @@ }; }; - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - mdio1_pins: mdio1_pins { mux { pins = "gpio10", "gpio11"; diff --git a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi new file mode 100644 index 000000000000..ac9c44f0c164 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8064.dtsi" + +&rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; + + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi index 65330065390a..411c8d63c38e 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-ipq8064.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> / { model = "Qualcomm Technologies, Inc. IPQ8064-v1.0"; @@ -36,7 +37,7 @@ cs-gpios = <&qcom_pinmux 20 0>; - flash: m25p80@0 { + flash: flash@0 { compatible = "s25fl256s1"; #address-cells = <1>; #size-cells = <1>; @@ -65,19 +66,19 @@ status = "okay"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&buttons_pins>; pinctrl-names = "default"; - button@1 { + button-1 { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; linux,input-type = <1>; debounce-interval = <60>; }; - button@2 { + button-2 { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; @@ -107,6 +108,7 @@ led@9 { label = "status_led_fail"; + function = LED_FUNCTION_STATUS; gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; @@ -119,6 +121,7 @@ led@53 { label = "status_led_pass"; + function = LED_FUNCTION_STATUS; gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; default-state = "off"; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi new file mode 100644 index 000000000000..0442580b22de --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8064-v2.0.dtsi" + +&rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; + + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi new file mode 100644 index 000000000000..2f117d576daf --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8064.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8064-v2.0"; + + aliases { + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; +}; + +&gsbi4 { + qcom,mode = <GSBI_PROT_I2C_UART>; + status = "okay"; + + serial@16340000 { + status = "okay"; + }; + /* + * The i2c device on gsbi4 should not be enabled. + * On ipq806x designs gsbi4 i2c is meant for exclusive + * RPM usage. Turning this on in kernel manifests as + * i2c failure for the RPM. + */ +}; + +&pcie0 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie1 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie2 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&sata { + ports-implemented = <0x1>; +}; + +&ss_phy_0 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; + +&ss_phy_1 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 996f4458d9fc..90c08b51680a 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -292,19 +292,22 @@ }; smem: smem@41000000 { + compatible = "qcom,smem"; reg = <0x41000000 0x200000>; no-map; + + hwlocks = <&sfpb_mutex 3>; }; }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -329,24 +332,64 @@ ranges; compatible = "simple-bus"; - lpass@28100000 { - compatible = "qcom,lpass-cpu"; - status = "disabled"; - clocks = <&lcc AHBIX_CLK>, - <&lcc MI2S_OSR_CLK>, - <&lcc MI2S_BIT_CLK>; - clock-names = "ahbix-clk", - "mi2s-osr-clk", - "mi2s-bit-clk"; - interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "lpass-irq-lpaif"; - reg = <0x28100000 0x10000>; - reg-names = "lpass-lpaif"; + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <7>; + snps,rd_osr_lmt = <7>; + snps,blen = <16 0 0 0 0 0 0>; + }; + + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + rpm: rpm@108000 { + compatible = "qcom,rpm-ipq8064"; + reg = <0x00108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ack", "err", "wakeup"; + + clocks = <&gcc RPM_MSG_RAM_H_CLK>; + clock-names = "ram"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; + #clock-cells = <1>; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x00500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; + + qfprom: qfprom@700000 { + compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + speedbin_efuse: speedbin@c0 { + reg = <0xc0 0x4>; + }; + tsens_calib: calib@400 { + reg = <0x400 0xb>; + }; + tsens_calib_backup: calib_backup@410 { + reg = <0x410 0xb>; + }; }; qcom_pinmux: pinmux@800000 { compatible = "qcom,ipq8064-pinctrl"; - reg = <0x800000 0x4000>; + reg = <0x00800000 0x4000>; gpio-controller; gpio-ranges = <&qcom_pinmux 0 0 69>; @@ -382,6 +425,13 @@ }; }; + i2c4_pins: i2c4-default { + pins = "gpio12", "gpio13"; + function = "gsbi4"; + drive-strength = <12>; + bias-disable; + }; + spi_pins: spi_pins { mux { pins = "gpio18", "gpio19", "gpio21"; @@ -424,6 +474,8 @@ pullups { pins = "gpio39"; + function = "nand"; + drive-strength = <10>; bias-pull-up; }; @@ -431,9 +483,61 @@ pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47"; + function = "nand"; + drive-strength = <10>; bias-bus-hold; }; }; + + mdio0_pins: mdio0-pins { + mux { + pins = "gpio0", "gpio1"; + function = "mdio"; + drive-strength = <8>; + bias-disable; + }; + }; + + rgmii2_pins: rgmii2-pins { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", + "gpio51", "gpio52", "gpio59", + "gpio60", "gpio61", "gpio62"; + function = "rgmii2"; + drive-strength = <8>; + bias-disable; + }; + }; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064", "syscon"; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor@900000 { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + }; + + sfpb_mutex: hwlock@1200600 { + compatible = "qcom,sfpb-mutex"; + reg = <0x01200600 0x100>; + + #hwlock-cells = <1>; }; intc: interrupt-controller@2000000 { @@ -465,46 +569,236 @@ cpu-offset = <0x80000>; }; + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x02011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu_l2_aux"; + }; + acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; }; + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; }; - adm_dma: dma-controller@18300000 { - compatible = "qcom,adm"; - reg = <0x18300000 0x100000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; + saw1: regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; - clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; - clock-names = "core", "iface"; + nss_common: syscon@03000000 { + compatible = "syscon"; + reg = <0x03000000 0x0000FFFF>; + }; - resets = <&gcc ADM0_RESET>, - <&gcc ADM0_PBUS_RESET>, - <&gcc ADM0_C0_RESET>, - <&gcc ADM0_C1_RESET>, - <&gcc ADM0_C2_RESET>; - reset-names = "clk", "pbus", "c0", "c1", "c2"; - qcom,ee = <0>; + usb3_0: usb3@100f8800 { + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x100f8800 0x8000>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_0_MASTER_RESET>; + reset-names = "master"; status = "disabled"; + + dwc3_0: dwc3@10000000 { + compatible = "snps,dwc3"; + reg = <0x10000000 0xcd00>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + phys = <&hs_phy_0>, <&ss_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; }; - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + hs_phy_0: phy@100f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x100f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; }; - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + ss_phy_0: phy@100f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x100f8830 0x30>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb3_1: usb3@110f8800 { + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x110f8800 0x8000>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_1_MASTER_RESET>; + reset-names = "master"; + + status = "disabled"; + + dwc3_1: dwc3@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0xcd00>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + phys = <&hs_phy_1>, <&ss_phy_1>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; + }; + + hs_phy_1: phy@110f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_1_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + ss_phy_1: phy@110f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x110f8830 0x30>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + sdcc3bam: dma-controller@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc1bam: dma-controller@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x8000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sdcc3: mmc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + sd-uhs-sdr104; + sd-uhs-ddr50; + vqmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc1: mmc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x2000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; + }; + + gsbi1: gsbi@12440000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12440000 0x100>; + cell-index = <1>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi1_serial: serial@12450000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12450000 0x100>, + <0x12400000 0x03>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + + status = "disabled"; + }; + + gsbi1_i2c: i2c@12460000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x12460000 0x1000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; }; gsbi2: gsbi@12480000 { @@ -530,7 +824,7 @@ status = "disabled"; }; - i2c@124a0000 { + gsbi2_i2c: i2c@124a0000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x124a0000 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; @@ -581,6 +875,106 @@ }; }; + gsbi6: gsbi@16500000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16500000 0x100>; + cell-index = <6>; + clocks = <&gcc GSBI6_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi6_i2c: i2c@16580000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16580000 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + gsbi6_spi: spi@16580000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x16580000 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gsbi7: gsbi@16600000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <7>; + reg = <0x16600000 0x100>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + syscon-tcsr = <&tcsr>; + + gsbi7_serial: serial@16640000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16640000 0x1000>, + <0x16600000 0x1000>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16680000 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + adm_dma: dma-controller@18300000 { + compatible = "qcom,adm"; + reg = <0x18300000 0x100000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc ADM0_RESET>, + <&gcc ADM0_PBUS_RESET>, + <&gcc ADM0_C0_RESET>, + <&gcc ADM0_C1_RESET>, + <&gcc ADM0_C2_RESET>; + reset-names = "clk", "pbus", "c0", "c1", "c2"; + qcom,ee = <0>; + + status = "disabled"; + }; + gsbi5: gsbi@1a200000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <5>; @@ -588,6 +982,7 @@ clocks = <&gcc GSBI5_H_CLK>; clock-names = "iface"; #address-cells = <1>; + #size-cells = <1>; ranges; status = "disabled"; @@ -631,27 +1026,9 @@ }; }; - gsbi7: gsbi@16600000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <7>; - reg = <0x16600000 0x100>; - clocks = <&gcc GSBI7_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - syscon-tcsr = <&tcsr>; - - gsbi7_serial: serial@16640000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16640000 0x1000>, - <0x16600000 0x1000>; - interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-ipq8064", "syscon"; + reg = <0x1a400000 0x100>; }; rng@1a500000 { @@ -661,17 +1038,6 @@ clock-names = "core"; }; - sata_phy: sata-phy@1b400000 { - compatible = "qcom,ipq806x-sata-phy"; - reg = <0x1b400000 0x200>; - - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - - #phy-cells = <0>; - status = "disabled"; - }; - nand: nand-controller@1ac00000 { compatible = "qcom,ipq806x-nand"; reg = <0x1ac00000 0x800>; @@ -694,106 +1060,17 @@ status = "disabled"; }; - sata: sata@29000000 { - compatible = "qcom,ipq806x-ahci", "generic-ahci"; - reg = <0x29000000 0x180>; - - interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_face", "iface", "core", - "rxoob", "pmalive"; + sata_phy: sata-phy@1b400000 { + compatible = "qcom,ipq806x-sata-phy"; + reg = <0x1b400000 0x200>; - assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; - phys = <&sata_phy>; - phy-names = "sata-phy"; + #phy-cells = <0>; status = "disabled"; }; - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x00500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; - - qfprom: qfprom@700000 { - compatible = "qcom,qfprom"; - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - tsens_calib: calib@400 { - reg = <0x400 0xb>; - }; - tsens_calib_backup: calib_backup@410 { - reg = <0x410 0xb>; - }; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - tsens: thermal-sensor@900000 { - compatible = "qcom,ipq8064-tsens"; - - nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; - nvmem-cell-names = "calib", "calib_backup"; - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow"; - - #qcom,sensors = <11>; - #thermal-sensor-cells = <1>; - }; - }; - - rpm: rpm@108000 { - compatible = "qcom,rpm-ipq8064"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ack", "err", "wakeup"; - - clocks = <&gcc RPM_MSG_RAM_H_CLK>; - clock-names = "ram"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; - #clock-cells = <1>; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-ipq8064", "syscon"; - reg = <0x1a400000 0x100>; - }; - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-ipq8064"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - pcie0: pci@1b500000 { compatible = "qcom,pcie-ipq8064"; reg = <0x1b500000 0x1000 @@ -808,7 +1085,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ + ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; @@ -842,7 +1119,7 @@ pinctrl-names = "default"; status = "disabled"; - perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; }; pcie1: pci@1b700000 { @@ -859,7 +1136,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ + ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -893,7 +1170,7 @@ pinctrl-names = "default"; status = "disabled"; - perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; }; pcie2: pci@1b900000 { @@ -910,7 +1187,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ + ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; @@ -944,12 +1221,7 @@ pinctrl-names = "default"; status = "disabled"; - perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; - }; - - nss_common: syscon@03000000 { - compatible = "syscon"; - reg = <0x03000000 0x0000FFFF>; + perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; }; qsgmii_csr: syscon@1bb00000 { @@ -957,22 +1229,60 @@ reg = <0x1bb00000 0x000001FF>; }; - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <7>; - snps,rd_osr_lmt = <7>; - snps,blen = <16 0 0 0 0 0 0>; + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-ipq8064"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + lpass@28100000 { + compatible = "qcom,lpass-cpu"; + status = "disabled"; + clocks = <&lcc AHBIX_CLK>, + <&lcc MI2S_OSR_CLK>, + <&lcc MI2S_BIT_CLK>; + clock-names = "ahbix-clk", + "mi2s-osr-clk", + "mi2s-bit-clk"; + interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "lpass-irq-lpaif"; + reg = <0x28100000 0x10000>; + reg-names = "lpass-lpaif"; + }; + + sata: sata@29000000 { + compatible = "qcom,ipq806x-ahci", "generic-ahci"; + reg = <0x29000000 0x180>; + + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_face", "iface", "core", + "rxoob", "pmalive"; + + assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + phys = <&sata_phy>; + phy-names = "sata-phy"; + status = "disabled"; }; gmac0: ethernet@37000000 { device_type = "network"; - compatible = "qcom,ipq806x-gmac"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; reg = <0x37000000 0x200000>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; snps,axi-config = <&stmmac_axi_setup>; snps,pbl = <32>; - snps,aal = <1>; + snps,aal; qcom,nss-common = <&nss_common>; qcom,qsgmii-csr = <&qsgmii_csr>; @@ -989,14 +1299,14 @@ gmac1: ethernet@37200000 { device_type = "network"; - compatible = "qcom,ipq806x-gmac"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; reg = <0x37200000 0x200000>; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; snps,axi-config = <&stmmac_axi_setup>; snps,pbl = <32>; - snps,aal = <1>; + snps,aal; qcom,nss-common = <&nss_common>; qcom,qsgmii-csr = <&qsgmii_csr>; @@ -1013,14 +1323,14 @@ gmac2: ethernet@37400000 { device_type = "network"; - compatible = "qcom,ipq806x-gmac"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; reg = <0x37400000 0x200000>; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; snps,axi-config = <&stmmac_axi_setup>; snps,pbl = <32>; - snps,aal = <1>; + snps,aal; qcom,nss-common = <&nss_common>; qcom,qsgmii-csr = <&qsgmii_csr>; @@ -1037,14 +1347,14 @@ gmac3: ethernet@37600000 { device_type = "network"; - compatible = "qcom,ipq806x-gmac"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; reg = <0x37600000 0x200000>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; snps,axi-config = <&stmmac_axi_setup>; snps,pbl = <32>; - snps,aal = <1>; + snps,aal; qcom,nss-common = <&nss_common>; qcom,qsgmii-csr = <&qsgmii_csr>; @@ -1058,168 +1368,5 @@ status = "disabled"; }; - - hs_phy_0: phy@100f8800 { - compatible = "qcom,ipq806x-usb-phy-hs"; - reg = <0x100f8800 0x30>; - clocks = <&gcc USB30_0_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - status = "disabled"; - }; - - ss_phy_0: phy@100f8830 { - compatible = "qcom,ipq806x-usb-phy-ss"; - reg = <0x100f8830 0x30>; - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - status = "disabled"; - }; - - usb3_0: usb3@100f8800 { - compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x100f8800 0x8000>; - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "core"; - - ranges; - - resets = <&gcc USB30_0_MASTER_RESET>; - reset-names = "master"; - - status = "disabled"; - - dwc3_0: dwc3@10000000 { - compatible = "snps,dwc3"; - reg = <0x10000000 0xcd00>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - phys = <&hs_phy_0>, <&ss_phy_0>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - snps,dis_u3_susphy_quirk; - }; - }; - - hs_phy_1: phy@110f8800 { - compatible = "qcom,ipq806x-usb-phy-hs"; - reg = <0x110f8800 0x30>; - clocks = <&gcc USB30_1_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - }; - - ss_phy_1: phy@110f8830 { - compatible = "qcom,ipq806x-usb-phy-ss"; - reg = <0x110f8830 0x30>; - clocks = <&gcc USB30_1_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - }; - - usb3_1: usb3@110f8800 { - compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x110f8800 0x8000>; - clocks = <&gcc USB30_1_MASTER_CLK>; - clock-names = "core"; - - ranges; - - resets = <&gcc USB30_1_MASTER_RESET>; - reset-names = "master"; - - status = "disabled"; - - dwc3_1: dwc3@11000000 { - compatible = "snps,dwc3"; - reg = <0x11000000 0xcd00>; - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - phys = <&hs_phy_1>, <&ss_phy_1>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - snps,dis_u3_susphy_quirk; - }; - }; - - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sdcc1bam: dma@12402000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12402000 0x8000>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc3bam: dma@12182000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x8000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc SDC3_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - amba: amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-1_8v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - sd-uhs-sdr104; - sd-uhs-ddr50; - vqmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; - dma-names = "tx", "rx"; - }; - }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi new file mode 100644 index 000000000000..803e6ff99ef8 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8065.dtsi" + +&rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; + + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = <775000>; + regulator-max-microvolt = <1275000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = <775000>; + regulator-max-microvolt = <1275000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom-ipq8065.dtsi new file mode 100644 index 000000000000..ea49f6cc416d --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8064-v2.0.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8065"; + compatible = "qcom,ipq8065", "qcom,ipq8064"; +}; diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi index 10ad929759ed..49de1821ac3a 100644 --- a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi @@ -114,7 +114,7 @@ }; &pmicgpio { - usb_vbus_5v_pins: usb_vbus_5v_pins { + usb_vbus_5v_pins: usb-vbus-5v-state { pins = "gpio4"; function = "normal"; output-high; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index c32415f0e66d..b47c86412de2 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -139,6 +139,7 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-mdm9615"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; }; @@ -151,7 +152,7 @@ }; l2cc: clock-controller@2011000 { - compatible = "syscon"; + compatible = "qcom,kpss-gcc", "syscon"; reg = <0x02011000 0x1000>; }; @@ -320,6 +321,7 @@ pmicgpio: gpio@150 { compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; + reg = <0x150>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; @@ -329,7 +331,7 @@ }; }; - sdcc1bam: dma@12182000{ + sdcc1bam: dma-controller@12182000{ compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; @@ -339,7 +341,7 @@ qcom,ee = <0>; }; - sdcc2bam: dma@12142000{ + sdcc2bam: dma-controller@12142000{ compatible = "qcom,bam-v1.3.0"; reg = <0x12142000 0x8000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; @@ -360,7 +362,7 @@ arm,primecell-periphid = <0x00051180>; reg = <0x12180000 0x2000>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; clock-names = "mclk", "apb_pclk"; bus-width = <8>; @@ -380,7 +382,7 @@ status = "disabled"; reg = <0x12140000 0x2000>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; clock-names = "mclk", "apb_pclk"; bus-width = <4>; @@ -410,7 +412,7 @@ interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ack", "err", "wakeup"; + interrupt-names = "ack", "err", "wakeup"; regulators { compatible = "qcom,rpm-pm8018-regulators"; diff --git a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts index d159188c8b95..290e1df631f0 100644 --- a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts +++ b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts @@ -18,8 +18,6 @@ }; }; -&soc { - serial@f991f000 { - status = "ok"; - }; +&blsp1_uart3 { + status = "ok"; }; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 7d48599502b3..cf2d56929428 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/reset/qcom,gcc-msm8974.h> / { #address-cells = <1>; @@ -43,13 +45,6 @@ }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_block 0 0x80>; - - #hwlock-cells = <1>; - }; - reserved-memory { #address-cells = <1>; #size-cells = <1>; @@ -59,6 +54,11 @@ reg = <0x3000000 0x100000>; no-map; }; + + adsp_region: adsp@dc00000 { + reg = <0x0dc00000 0x1900000>; + no-map; + }; }; smd { @@ -72,6 +72,35 @@ rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8226"; qcom,smd-channels = "rpm_requests"; + + rpmpd: power-controller { + compatible = "qcom,msm8226-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; }; }; }; @@ -85,6 +114,31 @@ hwlocks = <&tcsr_mutex 3>; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; @@ -104,45 +158,60 @@ reg = <0xf9011000 0x1000>; }; - sdhc_1: sdhci@f9824900 { + sdhc_1: mmc@f9824900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_default_state>; status = "disabled"; }; - sdhc_2: sdhci@f98a4900 { + sdhc_2: mmc@f98a4900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_default_state>; status = "disabled"; }; - sdhc_3: sdhci@f9864900 { + sdhc_3: mmc@f9864900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; + pinctrl-names = "default"; + pinctrl-0 = <&sdhc3_default_state>; + status = "disabled"; + }; + + blsp1_uart1: serial@f991d000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991d000 0x1000>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; status = "disabled"; }; @@ -229,6 +298,44 @@ #size-cells = <0>; }; + usb: usb@f9a55000 { + compatible = "qcom,ci-hdrc"; + reg = <0xf9a55000 0x200>, + <0xf9a55200 0x200>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <75000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + phy_type = "ulpi"; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs_phy: phy { + compatible = "qcom,usb-hs-phy-msm8226", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; + reset-names = "phy", "por"; + qcom,init-seq = /bits/ 8 <0x0 0x44 + 0x1 0x68 0x2 0x24 0x3 0x13>; + }; + }; + }; + gcc: clock-controller@fc400000 { compatible = "qcom,gcc-msm8226"; reg = <0xfc400000 0x4000>; @@ -281,6 +388,57 @@ drive-strength = <2>; bias-disable; }; + + sdhc1_default_state: sdhc1-default-state { + clk { + pins = "sdc1_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_default_state: sdhc2-default-state { + clk { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc3_default_state: sdhc3-default-state { + clk { + pins = "gpio44"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; + + cmd { + pins = "gpio43"; + function = "sdc3"; + drive-strength = <8>; + bias-pull-up; + }; + + data { + pins = "gpio39", "gpio40", "gpio41", "gpio42"; + function = "sdc3"; + drive-strength = <8>; + bias-pull-up; + }; + }; }; restart@fc4ab000 { @@ -374,9 +532,44 @@ reg = <0xfc428000 0x4000>; }; - tcsr_mutex_block: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; + tcsr_mutex: hwlock@fd484000 { + compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; + reg = <0xfd484000 0x1000>; + #hwlock-cells = <1>; + }; + + adsp: remoteproc@fe200000 { + compatible = "qcom,msm8226-adsp-pil"; + reg = <0xfe200000 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8226_VDDCX>; + power-domain-names = "cx"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&adsp_region>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + smd-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 8>; + qcom,smd-edge = <1>; + + label = "lpass"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index 414280d9bdba..be18f1be29a1 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts @@ -15,38 +15,23 @@ stdout-path = "serial0:115200n8"; }; - soc { - gsbi@19c00000 { - status = "okay"; - qcom,mode = <GSBI_PROT_I2C_UART>; - serial@19c40000 { - status = "okay"; - }; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; +}; - amba { - /* eMMC */ - sdcc1: mmc@12400000 { - status = "okay"; - vmmc-supply = <&vsdcc_fixed>; - }; +&gsbi12 { + qcom,mode = <GSBI_PROT_I2C_UART>; + status = "okay"; +}; - /* External micro SD card */ - sdcc3: mmc@12180000 { - status = "okay"; - vmmc-supply = <&vsdcc_fixed>; - }; - }; - }; +&gsbi12_serial { + status = "okay"; }; &pm8058 { @@ -76,3 +61,15 @@ keypad,num-columns = <5>; }; }; + +/* eMMC */ +&sdcc1 { + vmmc-supply = <&vsdcc_fixed>; + status = "okay"; +}; + +/* External micro SD card */ +&sdcc3 { + vmmc-supply = <&vsdcc_fixed>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 1e8aab357f9c..ddce7d64ba99 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -50,22 +50,25 @@ }; clocks { - cxo_board { + cxo_board: cxo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; + clock-output-names = "cxo_board"; }; - pxo_board { + pxo_board: pxo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; + clock-output-names = "pxo_board"; }; - sleep_clk { + sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; + clock-output-names = "sleep_clk"; }; }; @@ -126,8 +129,62 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8660"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + }; + + gsbi1: gsbi@16000000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16000000 0x100>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi1_spi: spi@16080000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x16080000 0x1000>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16200000 0x100>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + status = "disabled"; + + gsbi3_i2c: i2c@16280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16280000 0x1000>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; gsbi6: gsbi@16500000 { @@ -211,6 +268,7 @@ ranges; syscon-tcsr = <&tcsr>; + status = "disabled"; gsbi8_i2c: i2c@19880000 { compatible = "qcom,i2c-qup-v1.1.1"; @@ -390,25 +448,27 @@ }; l2cc: clock-controller@2082000 { - compatible = "syscon"; - reg = <0x02082000 0x1000>; + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x02082000 0x1000>; }; rpm: rpm@104000 { - compatible = "qcom,rpm-msm8660"; - reg = <0x00104000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ack", "err", "wakeup"; + compatible = "qcom,rpm-msm8660"; + reg = <0x00104000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ack", "err", "wakeup"; clocks = <&gcc RPM_MSG_RAM_H_CLK>; clock-names = "ram"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; + compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&pxo_board>; + clock-names = "pxo"; }; pm8901-regulators { @@ -484,80 +544,80 @@ #size-cells = <1>; ranges; sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; + reg = <0x12400000 0x8000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc2: mmc@12140000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12140000 0x8000>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; + reg = <0x12140000 0x8000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <48000000>; + max-frequency = <48000000>; no-1-8-v; }; sdcc4: mmc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x8000>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - max-frequency = <48000000>; + status = "disabled"; + reg = <0x121c0000 0x8000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + max-frequency = <48000000>; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc5: mmc@12200000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12200000 0x8000>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12200000 0x8000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <48000000>; + max-frequency = <48000000>; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts b/arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts new file mode 100644 index 000000000000..c8d34de8a71e --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/msm8916-samsung-e5.dts" +#include "qcom-msm8916-smp.dtsi" diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts b/arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts new file mode 100644 index 000000000000..85be286c8608 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/msm8916-samsung-e7.dts" +#include "qcom-msm8916-smp.dtsi" diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts b/arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts new file mode 100644 index 000000000000..d3abe0536238 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/msm8916-samsung-grandmax.dts" +#include "qcom-msm8916-smp.dtsi" diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 4af01039c3b2..9157e3c4f48f 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -15,318 +15,6 @@ stdout-path = "serial0:115200n8"; }; - soc { - gsbi@16400000 { - status = "okay"; - qcom,mode = <GSBI_PROT_I2C_UART>; - serial@16440000 { - status = "okay"; - }; - }; - - amba { - /* eMMC */ - sdcc1: mmc@12400000 { - status = "okay"; - }; - - /* External micro SD card */ - sdcc3: mmc@12180000 { - status = "okay"; - }; - }; - - rpm@108000 { - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s4>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - vdd_ncp-supply = <&pm8921_l6>; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l21_l23_l29-supply = <&pm8921_s8>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - /* Buck SMPS */ - pm8921_s1: s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - pm8921_s2: s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8921_s3: s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <4800000>; - bias-pull-down; - }; - - pm8921_s4: s4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>; - }; - - pm8921_s7: s7 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - pm8921_s8: s8 { - regulator-always-on; - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - /* PMOS LDO */ - pm8921_l1: l1 { - regulator-always-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - pm8921_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8921_l3: l3 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - bias-pull-down; - }; - - pm8921_l4: l4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l5: l5 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l6: l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l7: l7 { - regulator-always-on; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l8: l8 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l9: l9 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l10: l10 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l11: l11 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - - pm8921_l12: l12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8921_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l16: l16 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - bias-pull-down; - }; - - pm8921_l17: l17 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l18: l18 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - bias-pull-down; - }; - - pm8921_l21: l21 { - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - pm8921_l22: l22 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - bias-pull-down; - }; - - pm8921_l23: l23 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l24: l24 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - - pm8921_l25: l25 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - bias-pull-down; - }; - - /* Low Voltage Switch */ - pm8921_lvs1: lvs1 { - bias-pull-down; - }; - - pm8921_lvs2: lvs2 { - bias-pull-down; - }; - - pm8921_lvs3: lvs3 { - bias-pull-down; - }; - - pm8921_lvs4: lvs4 { - bias-pull-down; - }; - - pm8921_lvs5: lvs5 { - bias-pull-down; - }; - - pm8921_lvs6: lvs6 { - bias-pull-down; - }; - - pm8921_lvs7: lvs7 { - bias-pull-down; - }; - - pm8921_ncp: ncp { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - }; - }; - }; - - gsbi@16000000 { - status = "okay"; - qcom,mode = <GSBI_PROT_SPI>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_default>; - spi@16080000 { - status = "okay"; - eth@0 { - compatible = "micrel,ks8851"; - reg = <0>; - interrupt-parent = <&msmgpio>; - interrupts = <90 8>; - spi-max-frequency = <5400000>; - vdd-supply = <&ext_l2>; - vdd-io-supply = <&pm8921_lvs6>; - reset-gpios = <&msmgpio 89 0>; - }; - }; - }; - - pinctrl@800000 { - spi1_default: spi1_default { - mux { - pins = "gpio6", "gpio7", "gpio9"; - function = "gsbi1"; - }; - - mosi { - pins = "gpio6"; - drive-strength = <12>; - bias-disable; - }; - - miso { - pins = "gpio7"; - drive-strength = <12>; - bias-disable; - }; - - cs { - pins = "gpio8"; - drive-strength = <12>; - bias-disable; - output-low; - }; - - clk { - pins = "gpio9"; - drive-strength = <12>; - bias-disable; - }; - }; - }; - }; - regulators { compatible = "simple-bus"; @@ -340,6 +28,71 @@ }; }; +&gsbi1 { + qcom,mode = <GSBI_PROT_SPI>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_default>; + status = "okay"; +}; + +&gsbi1_spi { + status = "okay"; + + ethernet@0 { + compatible = "micrel,ks8851"; + reg = <0>; + interrupt-parent = <&msmgpio>; + interrupts = <90 8>; + spi-max-frequency = <5400000>; + vdd-supply = <&ext_l2>; + vdd-io-supply = <&pm8921_lvs6>; + reset-gpios = <&msmgpio 89 0>; + }; +}; + +&gsbi5 { + qcom,mode = <GSBI_PROT_I2C_UART>; + status = "okay"; +}; + +&gsbi5_serial { + status = "okay"; +}; + +&msmgpio { + spi1_default: spi1_default { + mux { + pins = "gpio6", "gpio7", "gpio9"; + function = "gsbi1"; + }; + + mosi { + pins = "gpio6"; + drive-strength = <12>; + bias-disable; + }; + + miso { + pins = "gpio7"; + drive-strength = <12>; + bias-disable; + }; + + cs { + pins = "gpio8"; + drive-strength = <12>; + bias-disable; + output-low; + }; + + clk { + pins = "gpio9"; + drive-strength = <12>; + bias-disable; + }; + }; +}; + &pmicintc { keypad@148 { linux,keymap = < @@ -352,3 +105,249 @@ keypad,num-columns = <5>; }; }; + +&rpm { + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s4>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + vdd_ncp-supply = <&pm8921_l6>; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l21_l23_l29-supply = <&pm8921_s8>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s2: s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8921_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + bias-pull-down; + }; + + pm8921_s4: s4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>; + }; + + pm8921_s7: s7 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s8: s8 { + regulator-always-on; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8921_l1: l1 { + regulator-always-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l3: l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + bias-pull-down; + }; + + pm8921_l4: l4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l5: l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l6: l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l7: l7 { + regulator-always-on; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l8: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l10: l10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l11: l11 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8921_l12: l12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l16: l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + bias-pull-down; + }; + + pm8921_l17: l17 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l18: l18 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + bias-pull-down; + }; + + pm8921_l21: l21 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8921_l22: l22 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + bias-pull-down; + }; + + pm8921_l23: l23 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l24: l24 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8921_l25: l25 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8921_lvs1: lvs1 { + bias-pull-down; + }; + + pm8921_lvs2: lvs2 { + bias-pull-down; + }; + + pm8921_lvs3: lvs3 { + bias-pull-down; + }; + + pm8921_lvs4: lvs4 { + bias-pull-down; + }; + + pm8921_lvs5: lvs5 { + bias-pull-down; + }; + + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + + pm8921_lvs7: lvs7 { + bias-pull-down; + }; + + pm8921_ncp: ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; +}; + +/* eMMC */ +&sdcc1 { + status = "okay"; +}; + +/* External micro SD card */ +&sdcc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 2a0ec97a264f..c5740da3754c 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -3,6 +3,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8960.h> +#include <dt-bindings/clock/qcom,lcc-msm8960.h> #include <dt-bindings/mfd/qcom-rpm.h> #include <dt-bindings/soc/qcom,gsbi.h> @@ -56,14 +57,14 @@ }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; clock-output-names = "cxo_board"; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -78,6 +79,15 @@ }; }; + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -118,8 +128,13 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8960"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; + clocks = <&cxo_board>, + <&pxo_board>, + <&lcc PLL4>; + clock-names = "cxo", "pxo", "pll4"; }; lcc: clock-controller@28000000 { @@ -127,27 +142,60 @@ reg = <0x28000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, <0>, + <0>, <0>, + <0>; + clock-names = "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; }; clock-controller@4000000 { compatible = "qcom,mmcc-msm8960"; reg = <0x4000000 0x1000>; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; }; l2cc: clock-controller@2011000 { - compatible = "syscon"; - reg = <0x2011000 0x1000>; + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; }; - rpm@108000 { - compatible = "qcom,rpm-msm8960"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; + rpm: rpm@108000 { + compatible = "qcom,rpm-msm8960"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; - interrupts = <0 19 0>, <0 21 0>, <0 22 0>; - interrupt-names = "ack", "err", "wakeup"; + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ack", "err", "wakeup"; regulators { compatible = "qcom,rpm-pm8921-regulators"; @@ -192,7 +240,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16440000 0x1000>, <0x16400000 0x1000>; - interrupts = <0 154 0x0>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -249,31 +297,22 @@ clock-names = "core"; }; - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; + reg = <0x12400000 0x8000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; @@ -281,18 +320,18 @@ }; sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <192000000>; + max-frequency = <192000000>; no-1-8-v; vmmc-supply = <&vsdcc_fixed>; }; @@ -303,7 +342,7 @@ reg = <0x1a400000 0x100>; }; - gsbi@16000000 { + gsbi1: gsbi@16000000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <1>; reg = <0x16000000 0x100>; @@ -313,12 +352,12 @@ #size-cells = <1>; ranges; - spi@16080000 { + gsbi1_spi: spi@16080000 { compatible = "qcom,spi-qup-v1.1.1"; #address-cells = <1>; #size-cells = <0>; reg = <0x16080000 0x1000>; - interrupts = <0 147 0>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <24000000>; cs-gpios = <&msmgpio 8 0>; diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts deleted file mode 100644 index 6d77e0f8ca4d..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts +++ /dev/null @@ -1,409 +0,0 @@ -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> - - -/ { - model = "Fairphone 2"; - compatible = "fairphone,fp2", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>; - linux,code = <KEY_CAMERA>; - wakeup-source; - debounce-interval = <15>; - }; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; - wakeup-source; - debounce-interval = <15>; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - wakeup-source; - debounce-interval = <15>; - }; - }; - - vibrator { - compatible = "gpio-vibrator"; - enable-gpios = <&msmgpio 86 GPIO_ACTIVE_HIGH>; - vcc-supply = <&pm8941_l18>; - }; - - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3350000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; -}; - -&soc { - serial@f991e000 { - status = "okay"; - }; - - remoteproc@fb21b000 { - status = "okay"; - - vddmx-supply = <&pm8841_s1>; - vddcx-supply = <&pm8841_s2>; - - pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; - - smd-edge { - qcom,remote-pid = <4>; - label = "pronto"; - - wcnss { - status = "okay"; - }; - }; - }; - - pinctrl@fd510000 { - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - wcnss_pin_a: wcnss-pin-active { - wlan { - pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; - function = "wlan"; - - drive-strength = <6>; - bias-pull-down; - }; - - bt { - pins = "gpio35", "gpio43", "gpio44"; - function = "bt"; - - drive-strength = <2>; - bias-pull-down; - }; - - fm { - pins = "gpio41", "gpio42"; - function = "fm"; - - drive-strength = <2>; - bias-pull-down; - }; - }; - }; - - sdhci@f9824900 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - status = "okay"; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - bus-width = <4>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>; - }; - - usb@f9a55000 { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; - - imem@fe805000 { - status = "okay"; - - reboot-mode { - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; - }; - }; -}; - -&spmi_bus { - pm8941@0 { - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio1", "gpio2", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = <PM8941_GPIO_S3>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 069136170198..6daceaa87802 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -2,8 +2,8 @@ #include "qcom-msm8974.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" -#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { @@ -12,213 +12,31 @@ aliases { serial0 = &blsp1_uart1; - serial1 = &blsp2_uart10; + serial1 = &blsp2_uart4; }; chosen { stdout-path = "serial0:115200n8"; }; - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <815000>; - regulator-max-microvolt = <900000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEUP>; + }; + + key-volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEDOWN>; }; }; @@ -229,7 +47,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 26 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -237,525 +55,599 @@ }; }; -&soc { - serial@f991d000 { - status = "okay"; +&blsp1_i2c1 { + status = "okay"; + clock-frequency = <100000>; + + charger: bq24192@6b { + compatible = "ti,bq24192"; + reg = <0x6b>; + interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>; + + omit-battery-class; + + usb_otg_vbus: usb-otg-vbus { }; }; - pinctrl@fd510000 { - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; + fuelgauge: max17048@36 { + compatible = "maxim,max17048"; + reg = <0x36>; - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x4d>; - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; + pinctrl-names = "default"; + pinctrl-0 = <&fuelgauge_pin>; - i2c1_pins: i2c1 { - mux { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; + maxim,alert-low-soc-level = <2>; + }; +}; - drive-strength = <2>; - bias-disable; - }; - }; +&blsp1_i2c2 { + status = "okay"; + clock-frequency = <355000>; - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; + synaptics@70 { + compatible = "syna,rmi4-i2c"; + reg = <0x70>; - drive-strength = <2>; - bias-disable; - }; - }; + interrupts-extended = <&tlmm 5 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; - i2c3_pins: i2c3 { - mux { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; - }; - }; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pin>; - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; + #address-cells = <1>; + #size-cells = <0>; - drive-strength = <2>; - bias-disable; - }; + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; }; - i2c12_pins: i2c12 { - mux { - pins = "gpio87", "gpio88"; - function = "blsp_i2c12"; - drive-strength = <2>; - bias-disable; - }; + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; }; + }; +}; - mpu6515_pin: mpu6515 { - irq { - pins = "gpio73"; - function = "gpio"; - bias-disable; - input-enable; - }; - }; +&blsp1_i2c3 { + status = "okay"; + clock-frequency = <100000>; + + avago_apds993@39 { + compatible = "avago,apds9930"; + reg = <0x39>; + interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8941_l17>; + vddio-supply = <&pm8941_lvs1>; + led-max-microamp = <100000>; + amstaos,proximity-diodes = <0>; + }; +}; - touch_pin: touch { - int { - pins = "gpio5"; - function = "gpio"; +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <355000>; - drive-strength = <2>; - bias-disable; - input-enable; - }; + led-controller@38 { + compatible = "ti,lm3630a"; + status = "okay"; + reg = <0x38>; - reset { - pins = "gpio8"; - function = "gpio"; + #address-cells = <1>; + #size-cells = <0>; - drive-strength = <2>; - bias-pull-up; - }; + led@0 { + reg = <0>; + led-sources = <0 1>; + label = "lcd-backlight"; + default-brightness = <200>; }; + }; +}; - panel_pin: panel { - te { - pins = "gpio12"; - function = "mdp_vsync"; +&blsp2_i2c6 { + status = "okay"; + clock-frequency = <100000>; - drive-strength = <2>; - bias-disable; - }; - }; + mpu6515@68 { + compatible = "invensense,mpu6515"; + reg = <0x68>; + interrupts-extended = <&tlmm 73 IRQ_TYPE_EDGE_FALLING>; + vddio-supply = <&pm8941_lvs1>; - bt_pin: bt { - hostwake { - pins = "gpio42"; - function = "gpio"; - }; + pinctrl-names = "default"; + pinctrl-0 = <&mpu6515_pin>; - devwake { - pins = "gpio62"; - function = "gpio"; + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + ak8963@f { + compatible = "asahi-kasei,ak8963"; + reg = <0x0f>; + gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>; + vid-supply = <&pm8941_lvs1>; + vdd-supply = <&pm8941_l17>; }; - shutdown { - pins = "gpio41"; - function = "gpio"; + bmp280@76 { + compatible = "bosch,bmp280"; + reg = <0x76>; + vdda-supply = <&pm8941_lvs1>; + vddd-supply = <&pm8941_l17>; }; }; + }; +}; - blsp2_uart10_pin_a: blsp2-uart10-pin-active { - tx { - pins = "gpio53"; - function = "blsp_uart10"; +&blsp1_uart1 { + status = "okay"; +}; - drive-strength = <2>; - bias-disable; - }; +&blsp2_uart4 { + status = "okay"; - rx { - pins = "gpio54"; - function = "blsp_uart10"; + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; - drive-strength = <2>; - bias-pull-up; - }; + pinctrl-names = "default"; + pinctrl-0 = <&bt_pin>; - cts { - pins = "gpio55"; - function = "blsp_uart10"; + host-wakeup-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; + }; +}; - drive-strength = <2>; - bias-pull-up; - }; +&dsi0 { + status = "okay"; - rts { - pins = "gpio56"; - function = "blsp_uart10"; + vdda-supply = <&pm8941_l2>; + vdd-supply = <&pm8941_lvs3>; + vddio-supply = <&pm8941_l12>; - drive-strength = <2>; - bias-disable; + panel: panel@0 { + reg = <0>; + compatible = "lg,acx467akm-7"; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_pin>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; }; }; }; +}; - sdhci@f9824900 { - status = "okay"; +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; +&dsi0_phy { + status = "okay"; - bus-width = <8>; - non-removable; + vddio-supply = <&pm8941_l12>; +}; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; +&mdss { + status = "okay"; +}; - sdhci@f98a4900 { - status = "okay"; +&otg { + status = "okay"; - max-frequency = <100000000>; - bus-width = <4>; - non-removable; - vmmc-supply = <&vreg_wlan>; - vqmmc-supply = <&pm8941_s3>; + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>; + extcon = <&charger>, <&usb_id>; + vbus-supply = <&usb_otg_vbus>; - #address-cells = <1>; - #size-cells = <0>; + hnp-disable; + srp-disable; + adp-disable; - bcrmf@1 { - compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; - reg = <1>; + ulpi { + phy@a { + status = "okay"; - brcm,drive-strength = <10>; + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_sleep_clk_pin>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; }; }; +}; - gpio-keys { - compatible = "gpio-keys"; +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio2", "gpio3"; + function = "normal"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; + bias-pull-up; + power-source = <PM8941_GPIO_S3>; + }; - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_VOLUMEUP>; - }; + fuelgauge_pin: fuelgauge-int-state { + pins = "gpio9"; + function = "normal"; - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_VOLUMEDOWN>; - }; + bias-disable; + input-enable; + power-source = <PM8941_GPIO_S3>; }; - serial@f9960000 { - status = "okay"; + wlan_sleep_clk_pin: wl-sleep-clk-state { + pins = "gpio16"; + function = "func2"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_uart10_pin_a>; + output-high; + power-source = <PM8941_GPIO_S3>; + }; - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <3000000>; + wlan_regulator_pin: wl-reg-active-state { + pins = "gpio17"; + function = "normal"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_pin>; + bias-disable; + power-source = <PM8941_GPIO_S3>; + }; - host-wakeup-gpios = <&msmgpio 42 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&msmgpio 62 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&msmgpio 41 GPIO_ACTIVE_HIGH>; - }; + otg { + gpio-hog; + gpios = <35 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "otg-gpio"; }; +}; - i2c@f9967000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c11_pins>; - clock-frequency = <355000>; - qcom,src-freq = <50000000>; +&pm8941_lpg { + status = "okay"; - led-controller@38 { - compatible = "ti,lm3630a"; - status = "okay"; - reg = <0x38>; + qcom,power-source = <1>; - #address-cells = <1>; - #size-cells = <0>; + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; - led@0 { - reg = <0>; - led-sources = <0 1>; - label = "lcd-backlight"; - default-brightness = <200>; - }; + #address-cells = <1>; + #size-cells = <0>; + + led@7 { + reg = <7>; + color = <LED_COLOR_ID_RED>; + }; + + led@6 { + reg = <6>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_BLUE>; }; }; +}; - i2c@f9968000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c12_pins>; - clock-frequency = <100000>; - qcom,src-freq = <50000000>; - - mpu6515@68 { - compatible = "invensense,mpu6515"; - reg = <0x68>; - interrupts-extended = <&msmgpio 73 IRQ_TYPE_EDGE_FALLING>; - vddio-supply = <&pm8941_lvs1>; - - pinctrl-names = "default"; - pinctrl-0 = <&mpu6515_pin>; - - mount-matrix = "0", "-1", "0", - "-1", "0", "0", - "0", "0", "1"; - - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - ak8963@f { - compatible = "asahi-kasei,ak8963"; - reg = <0x0f>; - gpios = <&msmgpio 67 0>; - vid-supply = <&pm8941_lvs1>; - vdd-supply = <&pm8941_l17>; - }; - - bmp280@76 { - compatible = "bosch,bmp280"; - reg = <0x76>; - vdda-supply = <&pm8941_lvs1>; - vddd-supply = <&pm8941_l17>; - }; - }; +&rpm_requests { + pm8841-regulators { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; }; }; - i2c@f9923000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <100000>; - qcom,src-freq = <50000000>; + pm8941-regulators { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; - charger: bq24192@6b { - compatible = "ti,bq24192"; - reg = <0x6b>; - interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>; + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; - omit-battery-class; + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; - usb_otg_vbus: usb-otg-vbus { }; + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; }; - fuelgauge: max17048@36 { - compatible = "maxim,max17048"; - reg = <0x36>; + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; - maxim,double-soc; - maxim,rcomp = /bits/ 8 <0x4d>; + pm8941_l3: l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; - interrupt-parent = <&msmgpio>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; - pinctrl-names = "default"; - pinctrl-0 = <&fuelgauge_pin>; + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - maxim,alert-low-soc-level = <2>; + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; }; - }; - i2c@f9924000 { - status = "okay"; + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; - clock-frequency = <355000>; - qcom,src-freq = <50000000>; + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; - synaptics@70 { - compatible = "syna,rmi4-i2c"; - reg = <0x70>; + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; - interrupts-extended = <&msmgpio 5 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; + pm8941_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; - pinctrl-names = "default"; - pinctrl-0 = <&touch_pin>; + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; - #address-cells = <1>; - #size-cells = <0>; + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - }; + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; }; - }; - i2c@f9925000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <100000>; - qcom,src-freq = <50000000>; - - avago_apds993@39 { - compatible = "avago,apds9930"; - reg = <0x39>; - interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&pm8941_l17>; - vddio-supply = <&pm8941_lvs1>; - led-max-microamp = <100000>; - amstaos,proximity-diodes = <0>; + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; }; - }; - usb@f9a55000 { - status = "okay"; + pm8941_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; - extcon = <&charger>, <&usb_id>; - vbus-supply = <&usb_otg_vbus>; + pm8941_l19: l19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; - hnp-disable; - srp-disable; - adp-disable; + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; - ulpi { - phy@a { - status = "okay"; + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; + pm8941_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; }; + + pm8941_lvs1: lvs1 {}; + pm8941_lvs3: lvs3 {}; }; +}; - mdss@fd900000 { - status = "okay"; +&sdhc_1 { + status = "okay"; - mdp@fd900000 { - status = "okay"; - }; + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; - dsi@fd922800 { - status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; - vdda-supply = <&pm8941_l2>; - vdd-supply = <&pm8941_lvs3>; - vddio-supply = <&pm8941_l12>; +&sdhc_2 { + status = "okay"; - #address-cells = <1>; - #size-cells = <0>; + max-frequency = <100000000>; + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pm8941_s3>; + non-removable; - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; - panel: panel@0 { - reg = <0>; - compatible = "lg,acx467akm-7"; + bcrmf@1 { + compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; + reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&panel_pin>; + brcm,drive-strength = <10>; - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin>; + }; +}; + +&tlmm { + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; }; - dsi-phy@fd922a00 { - status = "okay"; + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; - vddio-supply = <&pm8941_l12>; + sdc2_on: sdc2-on { + clk { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; }; }; -}; -&spmi_bus { - pm8941@0 { - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3"; - function = "normal"; + mpu6515_pin: mpu6515 { + pins = "gpio73"; + function = "gpio"; + bias-disable; + input-enable; + }; - bias-pull-up; - power-source = <PM8941_GPIO_S3>; - }; + touch_pin: touch { + int { + pins = "gpio5"; + function = "gpio"; - fuelgauge_pin: fuelgauge-int { - pins = "gpio9"; - function = "normal"; + drive-strength = <2>; + bias-disable; + input-enable; + }; - bias-disable; - input-enable; - power-source = <PM8941_GPIO_S3>; - }; + reset { + pins = "gpio8"; + function = "gpio"; - wlan_sleep_clk_pin: wl-sleep-clk { - pins = "gpio16"; - function = "func2"; + drive-strength = <2>; + bias-pull-up; + }; + }; - output-high; - power-source = <PM8941_GPIO_S3>; - }; + panel_pin: panel { + pins = "gpio12"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + }; - wlan_regulator_pin: wl-reg-active { - pins = "gpio17"; - function = "normal"; + bt_pin: bt { + hostwake { + pins = "gpio42"; + function = "gpio"; + }; - bias-disable; - power-source = <PM8941_GPIO_S3>; - }; + devwake { + pins = "gpio62"; + function = "gpio"; + }; - otg { - gpio-hog; - gpios = <35 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "otg-gpio"; - }; + shutdown { + pins = "gpio41"; + function = "gpio"; }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts deleted file mode 100644 index 96e1c978b878..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ /dev/null @@ -1,908 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974pro.dtsi" -#include "qcom-pma8084.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "Samsung Galaxy S5"; - compatible = "samsung,klte", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart1; - mmc0 = &sdhc_1; /* SDC1 eMMC slot */ - mmc1 = &sdhc_2; /* SDC2 SD card slot */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - smd { - rpm { - rpm_requests { - pma8084-regulators { - compatible = "qcom,rpm-pma8084-regulators"; - status = "okay"; - - pma8084_s1: s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - pma8084_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pma8084_s3: s3 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pma8084_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_s5: s5 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - - pma8084_s6: s6 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - pma8084_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pma8084_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pma8084_l3: l3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1200000>; - }; - - pma8084_l4: l4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1225000>; - }; - - pma8084_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pma8084_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pma8084_l11: l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pma8084_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pma8084_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pma8084_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l15: l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pma8084_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pma8084_l17: l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pma8084_l18: l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pma8084_l19: l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - pma8084_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - pma8084_l21: l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - pma8084_l22: l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - pma8084_l23: l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pma8084_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - pma8084_l25: l25 { - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - }; - - pma8084_l26: l26 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2050000>; - }; - - pma8084_l27: l27 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1225000>; - }; - - pma8084_lvs1: lvs1 {}; - pma8084_lvs2: lvs2 {}; - pma8084_lvs3: lvs3 {}; - pma8084_lvs4: lvs4 {}; - - pma8084_5vs1: 5vs1 {}; - }; - }; - }; - }; - - i2c-gpio-touchkey { - compatible = "i2c-gpio"; - #address-cells = <1>; - #size-cells = <0>; - sda-gpios = <&msmgpio 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_touchkey_pins>; - - touchkey@20 { - compatible = "cypress,tm2-touchkey"; - reg = <0x20>; - - interrupt-parent = <&pma8084_gpios>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touchkey_pin>; - - vcc-supply = <&max77826_ldo15>; - vdd-supply = <&pma8084_l19>; - - linux,keycodes = <KEY_APPSELECT KEY_BACK>; - }; - }; - - i2c-gpio-led { - compatible = "i2c-gpio"; - #address-cells = <1>; - #size-cells = <0>; - scl-gpios = <&msmgpio 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&msmgpio 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_led_gpioex_pins>; - - i2c-gpio,delay-us = <2>; - - gpio_expander: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - - gpio-controller; - #gpio-cells = <2>; - - vcc-supply = <&pma8084_s4>; - - pinctrl-names = "default"; - pinctrl-0 = <&gpioex_pin>; - - reset-gpios = <&msmgpio 145 GPIO_ACTIVE_LOW>; - }; - - led-controller@30 { - compatible = "panasonic,an30259a"; - reg = <0x30>; - - #address-cells = <1>; - #size-cells = <0>; - - led@1 { - reg = <1>; - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - }; - - led@2 { - reg = <2>; - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - }; - - led@3 { - reg = <3>; - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_BLUE>; - }; - }; - }; - - vreg_wlan: wlan-regulator { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_expander 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vreg_panel: panel-regulator { - compatible = "regulator-fixed"; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_en_pin>; - - regulator-name = "panel-vddr-reg"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - gpio = <&pma8084_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /delete-node/ vreg-boost; - - adsp-pil { - cx-supply = <&pma8084_s2>; - }; -}; - -&soc { - serial@f991e000 { - status = "okay"; - }; - - /* blsp2_uart8 */ - serial@f995e000 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart8_pins_active>; - pinctrl-1 = <&blsp2_uart8_pins_sleep>; - - bluetooth { - compatible = "brcm,bcm43540-bt"; - max-speed = <3000000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_pins>; - device-wakeup-gpios = <&msmgpio 91 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&msmgpio>; - interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wakeup"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-down { - label = "volume_down"; - gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <15>; - }; - - home-key { - label = "home_key"; - gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_HOMEPAGE>; - wakeup-source; - debounce-interval = <15>; - }; - - volume-up { - label = "volume_up"; - gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <15>; - }; - }; - - pinctrl@fd510000 { - blsp2_uart8_pins_active: blsp2-uart8-pins-active { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "blsp_uart8"; - drive-strength = <8>; - bias-disable; - }; - - blsp2_uart8_pins_sleep: blsp2-uart8-pins-sleep { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - bt_pins: bt-pins { - hostwake { - pins = "gpio75"; - function = "gpio"; - drive-strength = <16>; - input-enable; - }; - - devwake { - pins = "gpio91"; - function = "gpio"; - drive-strength = <2>; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <4>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <4>; - bias-pull-up; - }; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk-cmd-data { - pins = "gpio35", "gpio36", "gpio37", "gpio38", - "gpio39", "gpio40"; - function = "sdc3"; - drive-strength = <8>; - bias-disable; - }; - }; - - sdhc2_cd_pin: sdhc2-cd { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc3_pin_a: sdhc3-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c6_pins: i2c6 { - mux { - pins = "gpio29", "gpio30"; - function = "blsp_i2c6"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c12_pins: i2c12 { - mux { - pins = "gpio87", "gpio88"; - function = "blsp_i2c12"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c_touchkey_pins: i2c-touchkey { - mux { - pins = "gpio95", "gpio96"; - function = "gpio"; - input-enable; - bias-pull-up; - }; - }; - - i2c_led_gpioex_pins: i2c-led-gpioex { - mux { - pins = "gpio120", "gpio121"; - function = "gpio"; - input-enable; - bias-pull-down; - }; - }; - - gpioex_pin: gpioex { - res { - pins = "gpio145"; - function = "gpio"; - - bias-pull-up; - drive-strength = <2>; - }; - }; - - wifi_pin: wifi { - int { - pins = "gpio92"; - function = "gpio"; - - input-enable; - bias-pull-down; - }; - }; - - panel_te_pin: panel { - te { - pins = "gpio12"; - function = "mdp_vsync"; - - drive-strength = <2>; - bias-disable; - }; - }; - }; - - sdhc_1: sdhci@f9824900 { - status = "okay"; - - vmmc-supply = <&pma8084_l20>; - vqmmc-supply = <&pma8084_s4>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhc_2: sdhci@f9864900 { - status = "okay"; - - max-frequency = <100000000>; - - vmmc-supply = <&pma8084_l21>; - vqmmc-supply = <&pma8084_l13>; - - bus-width = <4>; - - /* cd-gpio is intentionally disabled. If enabled, an SD card - * present during boot is not initialized correctly. Without - * cd-gpios the driver resorts to polling, so hotplug works. - */ - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a /* &sdhc2_cd_pin */>; - // cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; - }; - - sdhci@f98a4900 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - max-frequency = <100000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc3_pin_a>; - - vmmc-supply = <&vreg_wlan>; - vqmmc-supply = <&pma8084_s4>; - - bus-width = <4>; - non-removable; - - wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - - interrupt-parent = <&msmgpio>; - interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>; - }; - }; - - usb@f9a55000 { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - /*extcon = <&smbb>, <&usb_id>;*/ - /*vbus-supply = <&chg_otg>;*/ - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "okay"; - - v1p8-supply = <&pma8084_l6>; - v3p3-supply = <&pma8084_l24>; - - /*extcon = <&smbb>;*/ - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; - - i2c@f9924000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - reg = <0x20>; - - interrupt-parent = <&pma8084_gpios>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - vdd-supply = <&max77826_ldo13>; - vio-supply = <&pma8084_lvs2>; - - pinctrl-names = "default"; - pinctrl-0 = <&touch_pin>; - - syna,startup-delay-ms = <100>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - }; - }; - }; - - i2c@f9928000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins>; - - pmic@60 { - reg = <0x60>; - compatible = "maxim,max77826"; - - regulators { - max77826_ldo1: LDO1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - max77826_ldo2: LDO2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - max77826_ldo3: LDO3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - max77826_ldo4: LDO4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo5: LDO5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo6: LDO6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo7: LDO7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo8: LDO8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo9: LDO9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo10: LDO10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2950000>; - }; - - max77826_ldo11: LDO11 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2950000>; - }; - - max77826_ldo12: LDO12 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo13: LDO13 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo14: LDO14 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo15: LDO15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_buck: BUCK { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - max77826_buckboost: BUCKBOOST { - regulator-min-microvolt = <3400000>; - regulator-max-microvolt = <3400000>; - }; - }; - }; - }; - - i2c@f9968000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c12_pins>; - - fuelgauge@36 { - compatible = "maxim,max17048"; - reg = <0x36>; - - maxim,double-soc; - maxim,rcomp = /bits/ 8 <0x56>; - - interrupt-parent = <&pma8084_gpios>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&fuelgauge_pin>; - }; - }; - - adreno@fdb00000 { - status = "ok"; - }; - - mdss@fd900000 { - status = "ok"; - - mdp@fd900000 { - status = "ok"; - }; - - dsi@fd922800 { - status = "ok"; - - vdda-supply = <&pma8084_l2>; - vdd-supply = <&pma8084_l22>; - vddio-supply = <&pma8084_l12>; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; - - panel: panel@0 { - reg = <0>; - compatible = "samsung,s6e3fa2"; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_te_pin &panel_rst_pin>; - - iovdd-supply = <&pma8084_lvs4>; - vddr-supply = <&vreg_panel>; - - reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>; - te-gpios = <&msmgpio 12 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - }; - - dsi-phy@fd922a00 { - status = "ok"; - - vddio-supply = <&pma8084_l12>; - }; - }; - - remoteproc@fc880000 { - cx-supply = <&pma8084_s2>; - mss-supply = <&pma8084_s6>; - mx-supply = <&pma8084_s1>; - pll-supply = <&pma8084_l12>; - }; -}; - -&spmi_bus { - pma8084@0 { - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = <PMA8084_GPIO_S4>; - }; - - touchkey_pin: touchkey-int-pin { - pins = "gpio6"; - function = "normal"; - bias-disable; - input-enable; - power-source = <PMA8084_GPIO_S4>; - }; - - touch_pin: touchscreen-int-pin { - pins = "gpio8"; - function = "normal"; - bias-disable; - input-enable; - power-source = <PMA8084_GPIO_S4>; - }; - - panel_en_pin: panel-en-pin { - pins = "gpio14"; - function = "normal"; - bias-pull-up; - power-source = <PMA8084_GPIO_S4>; - qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; - }; - - wlan_sleep_clk_pin: wlan-sleep-clk-pin { - pins = "gpio16"; - function = "func2"; - - output-high; - power-source = <PMA8084_GPIO_S4>; - qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; - }; - - panel_rst_pin: panel-rst-pin { - pins = "gpio17"; - function = "normal"; - bias-disable; - power-source = <PMA8084_GPIO_S4>; - qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; - }; - - - fuelgauge_pin: fuelgauge-int-pin { - pins = "gpio21"; - function = "normal"; - bias-disable; - input-enable; - power-source = <PMA8084_GPIO_S4>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts deleted file mode 100644 index 79e2cfbbb1ba..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-amami.dts +++ /dev/null @@ -1,435 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> - -/ { - model = "Sony Xperia Z1 Compact"; - compatible = "sony,xperia-amami", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_VOLUMEDOWN>; - }; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_CAMERA>; - }; - - camera-focus { - label = "camera_focus"; - gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_CAMERA_FOCUS>; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_VOLUMEUP>; - }; - }; - - memory@0 { - reg = <0 0x40000000>, <0x40000000 0x40000000>; - device_type = "memory"; - }; - - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-system-load = <200000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; -}; - -&soc { - sdhci@f9824900 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - status = "okay"; - - bus-width = <4>; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - }; - - serial@f991e000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_pin_a>; - }; - - - pinctrl@fd510000 { - blsp1_uart2_pin_a: blsp1-uart2-pin-active { - rx { - pins = "gpio5"; - function = "blsp_uart2"; - - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio4"; - function = "blsp_uart2"; - - drive-strength = <4>; - bias-disable; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - }; - - dma-controller@f9944000 { - qcom,controlled-remotely; - }; - - usb@f9a55000 { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; -}; - -&spmi_bus { - pm8941@0 { - charger@1000 { - qcom,fast-charge-safe-current = <1300000>; - qcom,fast-charge-current-limit = <1300000>; - qcom,dc-current-limit = <1300000>; - qcom,fast-charge-safe-voltage = <4400000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,fast-charge-low-threshold-voltage = <3400000>; - qcom,auto-recharge-threshold-voltage = <4200000>; - qcom,minimum-input-voltage = <4300000>; - }; - - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3", "gpio4", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = <PM8941_GPIO_S3>; - }; - }; - - coincell@2800 { - status = "okay"; - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; - }; - }; - - pm8941@1 { - wled@d800 { - status = "okay"; - - qcom,cs-out; - qcom,current-limit = <20>; - qcom,current-boost-limit = <805>; - qcom,switching-freq = <1600>; - qcom,ovp = <29>; - qcom,num-strings = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts deleted file mode 100644 index e66937e3f7dd..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts +++ /dev/null @@ -1,723 +0,0 @@ -#include "qcom-msm8974pro.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> - -/ { - model = "Sony Xperia Z2 Tablet"; - compatible = "sony,xperia-castor", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart2; - serial1 = &blsp2_uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_VOLUMEDOWN>; - }; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_CAMERA>; - }; - - camera-focus { - label = "camera_focus"; - gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_CAMERA_FOCUS>; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_VOLUMEUP>; - }; - }; - - smd { - rpm { - rpm_requests { - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-system-load = <154000>; - }; - - s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-allow-set-load; - regulator-system-load = <500000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; - - vreg_bl_vddio: lcd-backlight-vddio { - compatible = "regulator-fixed"; - regulator-name = "vreg_bl_vddio"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - - gpio = <&msmgpio 69 0>; - enable-active-high; - - vin-supply = <&pm8941_s3>; - startup-delay-us = <70000>; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_backlight_en_pin_a>; - }; - - vreg_vsp: lcd-dcdc-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_vsp"; - regulator-min-microvolt = <5600000>; - regulator-max-microvolt = <5600000>; - - gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_dcdc_en_pin_a>; - }; - - vreg_wlan: wlan-regulator { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_regulator_pin>; - }; -}; - -&soc { - sdhci@f9824900 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f9864900 { - status = "okay"; - - max-frequency = <100000000>; - non-removable; - vmmc-supply = <&vreg_wlan>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc3_pin_a>; - - #address-cells = <1>; - #size-cells = <0>; - - bcrmf@1 { - compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - brcm,drive-strength = <10>; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_sleep_clk_pin>; - }; - }; - - sdhci@f98a4900 { - status = "okay"; - - bus-width = <4>; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - }; - - serial@f991e000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_pin_a>; - }; - - serial@f995d000 { - status = "ok"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_uart7_pin_a>; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <3000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_pin>, - <&bt_dev_wake_pin>, - <&bt_reg_on_pin>; - - host-wakeup-gpios = <&msmgpio 95 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&msmgpio 96 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&pm8941_gpios 16 GPIO_ACTIVE_HIGH>; - }; - }; - - usb@f9a55000 { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; - - pinctrl@fd510000 { - blsp1_uart2_pin_a: blsp1-uart2-pin-active { - rx { - pins = "gpio5"; - function = "blsp_uart2"; - - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio4"; - function = "blsp_uart2"; - - drive-strength = <4>; - bias-disable; - }; - }; - - blsp2_uart7_pin_a: blsp2-uart7-pin-active { - tx { - pins = "gpio41"; - function = "blsp_uart7"; - - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio42"; - function = "blsp_uart7"; - - drive-strength = <2>; - bias-pull-up; - }; - - cts { - pins = "gpio43"; - function = "blsp_uart7"; - - drive-strength = <2>; - bias-pull-up; - }; - - rts { - pins = "gpio44"; - function = "blsp_uart7"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c8_pins: i2c8 { - mux { - pins = "gpio47", "gpio48"; - function = "blsp_i2c8"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - - drive-strength = <2>; - bias-disable; - }; - }; - - lcd_backlight_en_pin_a: lcd-backlight-vddio { - pins = "gpio69"; - drive-strength = <10>; - output-low; - bias-disable; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - sdhc3_pin_a: sdhc3-pin-active { - clk { - pins = "gpio40"; - function = "sdc3"; - - drive-strength = <10>; - bias-disable; - }; - - cmd { - pins = "gpio39"; - function = "sdc3"; - - drive-strength = <10>; - bias-pull-up; - }; - - data { - pins = "gpio35", "gpio36", "gpio37", "gpio38"; - function = "sdc3"; - - drive-strength = <10>; - bias-pull-up; - }; - }; - - ts_int_pin: synaptics { - pin { - pins = "gpio86"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - input-enable; - }; - }; - - bt_host_wake_pin: bt-host-wake { - pins = "gpio95"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - output-low; - }; - - bt_dev_wake_pin: bt-dev-wake { - pins = "gpio96"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - }; - - i2c@f9964000 { - status = "okay"; - - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_pins>; - - synaptics@2c { - compatible = "syna,rmi4-i2c"; - reg = <0x2c>; - - interrupt-parent = <&msmgpio>; - interrupts = <86 IRQ_TYPE_EDGE_FALLING>; - - #address-cells = <1>; - #size-cells = <0>; - - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_pin>; - - syna,startup-delay-ms = <10>; - - rmi-f01@1 { - reg = <0x1>; - syna,nosleep = <1>; - }; - - rmi-f11@11 { - reg = <0x11>; - syna,f11-flip-x = <1>; - syna,sensor-type = <1>; - }; - }; - }; - - i2c@f9967000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c11_pins>; - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - lp8566_wled: backlight@2c { - compatible = "ti,lp8556"; - reg = <0x2c>; - power-supply = <&vreg_bl_vddio>; - - bl-name = "backlight"; - dev-ctrl = /bits/ 8 <0x05>; - init-brt = /bits/ 8 <0x3f>; - rom_a0h { - rom-addr = /bits/ 8 <0xa0>; - rom-val = /bits/ 8 <0xff>; - }; - rom_a1h { - rom-addr = /bits/ 8 <0xa1>; - rom-val = /bits/ 8 <0x3f>; - }; - rom_a2h { - rom-addr = /bits/ 8 <0xa2>; - rom-val = /bits/ 8 <0x20>; - }; - rom_a3h { - rom-addr = /bits/ 8 <0xa3>; - rom-val = /bits/ 8 <0x5e>; - }; - rom_a4h { - rom-addr = /bits/ 8 <0xa4>; - rom-val = /bits/ 8 <0x02>; - }; - rom_a5h { - rom-addr = /bits/ 8 <0xa5>; - rom-val = /bits/ 8 <0x04>; - }; - rom_a6h { - rom-addr = /bits/ 8 <0xa6>; - rom-val = /bits/ 8 <0x80>; - }; - rom_a7h { - rom-addr = /bits/ 8 <0xa7>; - rom-val = /bits/ 8 <0xf7>; - }; - rom_a9h { - rom-addr = /bits/ 8 <0xa9>; - rom-val = /bits/ 8 <0x80>; - }; - rom_aah { - rom-addr = /bits/ 8 <0xaa>; - rom-val = /bits/ 8 <0x0f>; - }; - rom_aeh { - rom-addr = /bits/ 8 <0xae>; - rom-val = /bits/ 8 <0x0f>; - }; - }; - }; -}; - -&spmi_bus { - pm8941@0 { - charger@1000 { - qcom,fast-charge-safe-current = <1500000>; - qcom,fast-charge-current-limit = <1500000>; - qcom,dc-current-limit = <1800000>; - qcom,fast-charge-safe-voltage = <4400000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,fast-charge-low-threshold-voltage = <3400000>; - qcom,auto-recharge-threshold-voltage = <4200000>; - qcom,minimum-input-voltage = <4300000>; - }; - - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = <PM8941_GPIO_S3>; - }; - - bt_reg_on_pin: bt-reg-on { - pins = "gpio16"; - function = "normal"; - - output-low; - power-source = <PM8941_GPIO_S3>; - }; - - wlan_sleep_clk_pin: wl-sleep-clk { - pins = "gpio17"; - function = "func2"; - - output-high; - power-source = <PM8941_GPIO_S3>; - }; - - wlan_regulator_pin: wl-reg-active { - pins = "gpio18"; - function = "normal"; - - bias-disable; - power-source = <PM8941_GPIO_S3>; - }; - - lcd_dcdc_en_pin_a: lcd-dcdc-en-active { - pins = "gpio20"; - function = "normal"; - - bias-disable; - power-source = <PM8941_GPIO_S3>; - input-disable; - output-low; - }; - - }; - - coincell@2800 { - status = "okay"; - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts deleted file mode 100644 index a62e5c25b23c..000000000000 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ /dev/null @@ -1,484 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> - -/ { - model = "Sony Xperia Z1"; - compatible = "sony,xperia-honami", "qcom,msm8974"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_VOLUMEDOWN>; - }; - - camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_CAMERA>; - }; - - camera-focus { - label = "camera_focus"; - gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_CAMERA_FOCUS>; - }; - - volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = <KEY_VOLUMEUP>; - }; - }; - - memory@0 { - reg = <0 0x40000000>, <0x40000000 0x40000000>; - device_type = "memory"; - }; - - smd { - rpm { - rpm_requests { - pm8841-regulators { - s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - - pm8941-regulators { - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - - regulator-always-on; - regulator-boot-on; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-allow-set-load; - regulator-boot-on; - regulator-system-load = <200000>; - }; - - l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-boot-on; - }; - - l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - - regulator-boot-on; - }; - }; - }; - }; - }; -}; - -&soc { - usb@f9a55000 { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - ulpi { - phy@a { - status = "okay"; - - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - }; - }; - }; - - sdhci@f9824900 { - status = "okay"; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - bus-width = <8>; - non-removable; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; - }; - - sdhci@f98a4900 { - status = "okay"; - - bus-width = <4>; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; - }; - - serial@f991e000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_pin_a>; - }; - - i2c@f9924000 { - status = "okay"; - - clock-frequency = <355000>; - qcom,src-freq = <50000000>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - synaptics@2c { - compatible = "syna,rmi4-i2c"; - reg = <0x2c>; - - interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>; - - #address-cells = <1>; - #size-cells = <0>; - - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_pin>; - - syna,startup-delay-ms = <10>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - syna,sensor-type = <1>; - }; - }; - }; - - pinctrl@fd510000 { - blsp1_uart2_pin_a: blsp1-uart2-pin-active { - rx { - pins = "gpio5"; - function = "blsp_uart2"; - - drive-strength = <2>; - bias-pull-up; - }; - - tx { - pins = "gpio4"; - function = "blsp_uart2"; - - drive-strength = <4>; - bias-disable; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - }; - - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdhc2_cd_pin_a: sdhc2-cd-pin-active { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdhc2_pin_a: sdhc2-pin-active { - clk { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - ts_int_pin: touch-int { - pin { - pins = "gpio61"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - input-enable; - }; - }; - }; - - dma-controller@f9944000 { - qcom,controlled-remotely; - }; -}; - -&spmi_bus { - pm8941@0 { - charger@1000 { - qcom,fast-charge-safe-current = <1500000>; - qcom,fast-charge-current-limit = <1500000>; - qcom,dc-current-limit = <1800000>; - qcom,fast-charge-safe-voltage = <4400000>; - qcom,fast-charge-high-threshold-voltage = <4350000>; - qcom,fast-charge-low-threshold-voltage = <3400000>; - qcom,auto-recharge-threshold-voltage = <4200000>; - qcom,minimum-input-voltage = <4300000>; - }; - - gpios@c000 { - gpio_keys_pin_a: gpio-keys-active { - pins = "gpio2", "gpio3", "gpio4", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = <PM8941_GPIO_S3>; - }; - }; - - coincell@2800 { - status = "okay"; - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; - }; - }; - - pm8941@1 { - wled@d800 { - status = "okay"; - - qcom,cs-out; - qcom,current-limit = <20>; - qcom,current-boost-limit = <805>; - qcom,switching-freq = <1600>; - qcom,ovp = <29>; - qcom,num-strings = <2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts new file mode 100644 index 000000000000..68d5626bf491 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974-sony-xperia-rhine.dtsi" + +/ { + model = "Sony Xperia Z1 Compact"; + compatible = "sony,xperia-amami", "qcom,msm8974"; +}; + +&smbb { + qcom,fast-charge-safe-current = <1300000>; + qcom,fast-charge-current-limit = <1300000>; + qcom,dc-current-limit = <1300000>; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts new file mode 100644 index 000000000000..ea6a941d8f8c --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974-sony-xperia-rhine.dtsi" + +/ { + model = "Sony Xperia Z1"; + compatible = "sony,xperia-honami", "qcom,msm8974"; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi new file mode 100644 index 000000000000..5a70683d9103 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -0,0 +1,487 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +/ { + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + key-camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_CAMERA>; + }; + + key-camera-focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_CAMERA_FOCUS>; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@3e8e0000 { + compatible = "ramoops"; + reg = <0x3e8e0000 0x200000>; + + console-size = <0x100000>; + record-size = <0x10000>; + ftrace-size = <0x10000>; + pmsg-size = <0x80000>; + }; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + clock-frequency = <355000>; + + synaptics@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + + interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; + + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_pin>; + + syna,startup-delay-ms = <10>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + touchscreen-inverted-x; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp1_i2c6 { + status = "okay"; + clock-frequency = <355000>; + + nfc@28 { + compatible = "nxp,pn544-i2c"; + reg = <0x28>; + + interrupt-parent = <&tlmm>; + interrupts = <59 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&pm8941_gpios 23 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_dma { + qcom,controlled-remotely; +}; + +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <355000>; + + /* sii8334 MHL HDMI bridge */ +}; + +&otg { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "okay"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; +}; + +&pm8941_coincell { + status = "okay"; + qcom,rset-ohms = <2100>; + qcom,vset-millivolts = <3000>; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio2", "gpio3", "gpio4", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = <PM8941_GPIO_S3>; + }; +}; + +&pm8941_lpg { + status = "okay"; + + qcom,power-source = <1>; + + rgb-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_BLUE>; + }; + + led@6 { + reg = <6>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@7 { + reg = <7>; + color = <LED_COLOR_ID_RED>; + }; + }; +}; + +&pm8941_wled { + status = "okay"; + + qcom,cs-out; + qcom,current-limit = <20>; + qcom,current-boost-limit = <805>; + qcom,switching-freq = <1600>; + qcom,ovp = <29>; + qcom,num-strings = <2>; +}; + +&rpm_requests { + pm8841-regulators { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + }; + + pm8941-regulators { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s4: s4 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + + pm8941_lvs3: lvs3 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; +}; + +&smbb { + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <1500000>; + qcom,dc-current-limit = <1800000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,fast-charge-low-threshold-voltage = <3400000>; + qcom,auto-recharge-threshold-voltage = <4200000>; + qcom,minimum-input-voltage = <4300000>; +}; + +&tlmm { + ts_int_pin: touch-int { + pins = "gpio61"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_on: sdc-on { + clk { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + + cd { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 412d94736c35..7a9be0acf3f5 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -12,61 +12,19 @@ / { #address-cells = <1>; #size-cells = <1>; - model = "Qualcomm MSM8974"; - compatible = "qcom,msm8974"; interrupt-parent = <&intc>; - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mpss_region: mpss@8000000 { - reg = <0x08000000 0x5100000>; - no-map; - }; - - mba_region: mba@d100000 { - reg = <0x0d100000 0x100000>; - no-map; - }; - - wcnss_region: wcnss@d200000 { - reg = <0x0d200000 0xa00000>; - no-map; - }; - - adsp_region: adsp@dc00000 { - reg = <0x0dc00000 0x1900000>; - no-map; - }; - - venus@f500000 { - reg = <0x0f500000 0x500000>; - no-map; - }; - - smem_region: smem@fa00000 { - reg = <0xfa00000 0x200000>; - no-map; - }; - - tz@fc00000 { - reg = <0x0fc00000 0x160000>; - no-map; - }; - - rfsa@fd60000 { - reg = <0x0fd60000 0x20000>; - no-map; + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; }; - rmtfs@fd80000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0fd80000 0x180000>; - no-map; - - qcom,client-id = <1>; + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; }; }; @@ -136,238 +94,75 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-msm8974", "qcom,scm"; + clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; + memory { device_type = "memory"; reg = <0x0 0x0>; }; - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 6>; - - trips { - cpu_alert1: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 7>; - - trips { - cpu_alert2: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit2: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 8>; - - trips { - cpu_alert3: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit3: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - q6-dsp-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + pmu { + compatible = "qcom,krait-pmu"; + interrupts = <GIC_PPI 7 0xf04>; + }; - thermal-sensors = <&tsens 1>; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; - trips { - q6_dsp_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; + mpss_region: mpss@8000000 { + reg = <0x08000000 0x5100000>; + no-map; }; - modemtx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 2>; - - trips { - modemtx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; + mba_region: mba@d100000 { + reg = <0x0d100000 0x100000>; + no-map; }; - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 3>; - - trips { - video_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; + wcnss_region: wcnss@d200000 { + reg = <0x0d200000 0xa00000>; + no-map; }; - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 4>; - - trips { - wlan_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; + adsp_region: adsp@dc00000 { + reg = <0x0dc00000 0x1900000>; + no-map; }; - gpu-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 9>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; + venus_region: memory@f500000 { + reg = <0x0f500000 0x500000>; + no-map; }; - gpu-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 10>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; + smem_region: smem@fa00000 { + reg = <0xfa00000 0x200000>; + no-map; }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <GIC_PPI 7 0xf04>; - }; - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; + tz_region: memory@fc00000 { + reg = <0x0fc00000 0x160000>; + no-map; }; - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; + rfsa_mem: memory@fd60000 { + reg = <0x0fd60000 0x20000>; + no-map; }; - }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 2 0xf08>, - <GIC_PPI 3 0xf08>, - <GIC_PPI 4 0xf08>, - <GIC_PPI 1 0xf08>; - clock-frequency = <19200000>; - }; - - adsp-pil { - compatible = "qcom,msm8974-adsp-pil"; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - cx-supply = <&pm8841_s2>; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&adsp_region>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - smd-edge { - interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 8>; - qcom,smd-edge = <1>; + rmtfs@fd80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0fd80000 0x180000>; + no-map; - label = "lpass"; + qcom,client-id = <1>; }; }; @@ -497,11 +292,23 @@ }; }; - firmware { - scm { - compatible = "qcom,scm"; - clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; - clock-names = "core", "bus", "iface"; + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm_requests { + compatible = "qcom,rpm-msm8974"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; + #clock-cells = <1>; + }; + }; }; }; @@ -524,31 +331,6 @@ reg = <0xf9011000 0x1000>; }; - qfprom: qfprom@fc4bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; - }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; - }; - }; - - tsens: thermal-sensor@fc4a9000 { - compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a9000 0x1000>, /* TM */ - <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - #qcom,sensors = <11>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - timer@f9020000 { #address-cells = <1>; #size-cells = <1>; @@ -654,47 +436,59 @@ reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; }; - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; + sdhc_1: mmc@f9824900 { + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc", "core"; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + bus-width = <8>; + non-removable; - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8974"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x4000>; + status = "disabled"; }; - tcsr: syscon@fd4a0000 { - compatible = "syscon"; - reg = <0xfd4a0000 0x10000>; - }; + sdhc_3: mmc@f9864900 { + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; + reg-names = "hc", "core"; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + bus-width = <4>; - tcsr_mutex_block: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; - }; + #address-cells = <1>; + #size-cells = <0>; - mmcc: clock-controller@fd8c0000 { - compatible = "qcom,mmcc-msm8974"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfd8c0000 0x6000>; + status = "disabled"; }; - tcsr_mutex: tcsr-mutex { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_block 0 0x80>; + sdhc_2: mmc@f98a4900 { + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc", "core"; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + bus-width = <4>; - #hwlock-cells = <1>; - }; + #address-cells = <1>; + #size-cells = <0>; - rpm_msg_ram: memory@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; + status = "disabled"; }; blsp1_uart1: serial@f991d000 { @@ -712,19 +506,90 @@ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart2_default>; + status = "disabled"; + }; + + blsp1_i2c1: i2c@f9923000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9923000 0x1000>; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c1_default>; + pinctrl-1 = <&blsp1_i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c2: i2c@f9924000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9924000 0x1000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c2_default>; + pinctrl-1 = <&blsp1_i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c3: i2c@f9925000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9925000 0x1000>; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c3_default>; + pinctrl-1 = <&blsp1_i2c3_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c6: i2c@f9928000 { status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9928000 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c6_default>; + pinctrl-1 = <&blsp1_i2c6_sleep>; + #address-cells = <1>; + #size-cells = <0>; }; - blsp2_uart7: serial@f995d000 { + blsp2_dma: dma-controller@f9944000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xf9944000 0x19000>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp2_uart1: serial@f995d000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995d000 0x1000>; - interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart1_default>; + pinctrl-1 = <&blsp2_uart1_sleep>; status = "disabled"; }; - blsp2_uart8: serial@f995e000 { + blsp2_uart2: serial@f995e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995e000 0x1000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; @@ -733,55 +598,59 @@ status = "disabled"; }; - blsp2_uart10: serial@f9960000 { + blsp2_uart4: serial@f9960000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf9960000 0x1000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_uart4_default>; status = "disabled"; }; - sdhci@f9824900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; + blsp2_i2c2: i2c@f9964000 { status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9964000 0x1000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c2_default>; + pinctrl-1 = <&blsp2_i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; }; - sdhci@f9864900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; + blsp2_i2c5: i2c@f9967000 { status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9967000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c5_default>; + pinctrl-1 = <&blsp2_i2c5_sleep>; + #address-cells = <1>; + #size-cells = <0>; }; - sdhci@f98a4900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; + blsp2_i2c6: i2c@f9968000 { status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9968000 0x1000>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c6_default>; + pinctrl-1 = <&blsp2_i2c6_sleep>; + #address-cells = <1>; + #size-cells = <0>; }; otg: usb@f9a55000 { @@ -835,55 +704,6 @@ clock-names = "core"; }; - remoteproc@fc880000 { - compatible = "qcom,msm8974-mss-pil"; - reg = <0xfc880000 0x100>, <0xfc820000 0x020>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, - <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "bus", "mem", "xo"; - - resets = <&gcc GCC_MSS_RESTART>; - reset-names = "mss_restart"; - - cx-supply = <&pm8841_s2>; - mss-supply = <&pm8841_s3>; - mx-supply = <&pm8841_s1>; - pll-supply = <&pm8941_l12>; - - qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - mba { - memory-region = <&mba_region>; - }; - - mpss { - memory-region = <&mpss_region>; - }; - - smd-edge { - interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 12>; - qcom,smd-edge = <0>; - - label = "modem"; - }; - }; - pronto: remoteproc@fb21b000 { compatible = "qcom,pronto-v2-pil", "qcom,pronto"; reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; @@ -898,8 +718,6 @@ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - vddpx-supply = <&pm8941_s3>; - qcom,smem-states = <&wcnss_smp2p_out 0>; qcom,smem-state-names = "stop"; @@ -910,11 +728,6 @@ clocks = <&rpmcc RPM_SMD_CXO_A2>; clock-names = "xo"; - - vddxo-supply = <&pm8941_l6>; - vddrfa-supply = <&pm8941_l11>; - vddpa-supply = <&pm8941_l19>; - vdddig-supply = <&pm8941_s3>; }; smd-edge { @@ -942,139 +755,37 @@ interrupt-names = "tx", "rx"; qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; - qcom,smem-state-names = "tx-enable", "tx-rings-empty"; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; }; }; }; }; - msmgpio: pinctrl@fd510000 { - compatible = "qcom,msm8974-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - gpio-ranges = <&msmgpio 0 0 146>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - }; - - i2c@f9923000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9923000 0x1000>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@f9924000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9924000 0x1000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp_i2c3: i2c@f9925000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9925000 0x1000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp_i2c6: i2c@f9928000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9928000 0x1000>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp_i2c8: i2c@f9964000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9964000 0x1000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp_i2c11: i2c@f9967000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9967000 0x1000>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; - dma-names = "tx", "rx"; - }; - - blsp_i2c12: i2c@f9968000 { - status = "disabled"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9968000 0x1000>; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spmi_bus: spmi@fc4cf000 { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - interrupt-names = "periph_irq"; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - blsp2_dma: dma-controller@f9944000 { - compatible = "qcom,bam-v1.4.0"; - reg = <0xf9944000 0x19000>; - interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; + sram@fc190000 { + compatible = "qcom,msm8974-rpm-stats"; + reg = <0xfc190000 0x10000>; }; - etr@fc322000 { + etf@fc307000 { compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0xfc322000 0x1000>; + reg = <0xfc307000 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + in-ports { port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; + etf_in: endpoint { + remote-endpoint = <&merger_out>; }; }; }; @@ -1096,59 +807,39 @@ }; }; - replicator@fc31c000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0xfc31c000 0x1000>; + funnel@fc31a000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0xfc31a000 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; - out-ports { + in-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; + /* + * Not described input ports: + * 0 - not-connected + * 1 - connected trought funnel to Multimedia CPU + * 2 - connected to Wireless CPU + * 3 - not-connected + * 4 - not-connected + * 6 - not-connected + * 7 - connected to STM + */ + port@5 { + reg = <5>; + funnel1_in5: endpoint { + remote-endpoint = <&kpss_out>; }; }; }; - }; - - etf@fc307000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0xfc307000 0x1000>; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; out-ports { port { - etf_out: endpoint { - remote-endpoint = <&replicator_in>; - }; - }; - }; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&merger_out>; + funnel1_out: endpoint { + remote-endpoint = <&merger_in1>; }; }; }; @@ -1188,85 +879,51 @@ }; }; - funnel@fc31a000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0xfc31a000 0x1000>; + replicator@fc31c000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0xfc31c000 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; - in-ports { + out-ports { #address-cells = <1>; #size-cells = <0>; - /* - * Not described input ports: - * 0 - not-connected - * 1 - connected trought funnel to Multimedia CPU - * 2 - connected to Wireless CPU - * 3 - not-connected - * 4 - not-connected - * 6 - not-connected - * 7 - connected to STM - */ - port@5 { - reg = <5>; - funnel1_in5: endpoint { - remote-endpoint = <&kpss_out>; + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&tpiu_in>; }; }; }; - out-ports { + in-ports { port { - funnel1_out: endpoint { - remote-endpoint = <&merger_in1>; + replicator_in: endpoint { + remote-endpoint = <&etf_out>; }; }; }; }; - funnel@fc345000 { /* KPSS funnel only 4 inputs are used */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0xfc345000 0x1000>; + etr@fc322000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0xfc322000 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - kpss_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - port@1 { - reg = <1>; - kpss_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - port@2 { - reg = <2>; - kpss_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - port@3 { - reg = <3>; - kpss_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { port { - kpss_out: endpoint { - remote-endpoint = <&funnel1_in5>; + etr_in: endpoint { + remote-endpoint = <&replicator_out0>; }; }; }; @@ -1344,25 +1001,66 @@ }; }; - ocmem@fdd00000 { - compatible = "qcom,msm8974-ocmem"; - reg = <0xfdd00000 0x2000>, - <0xfec00000 0x180000>; - reg-names = "ctrl", - "mem"; - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, - <&mmcc OCMEMCX_OCMEMNOC_CLK>; - clock-names = "core", - "iface"; + /* KPSS funnel, only 4 inputs are used */ + funnel@fc345000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0xfc345000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; - gmu_sram: gmu-sram@0 { - reg = <0x0 0x100000>; + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + kpss_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + port@1 { + reg = <1>; + kpss_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + port@2 { + reg = <2>; + kpss_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + port@3 { + reg = <3>; + kpss_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + kpss_out: endpoint { + remote-endpoint = <&funnel1_in5>; + }; + }; }; }; + gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-msm8974"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xfc400000 0x4000>; + }; + + rpm_msg_ram: memory@fc428000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0xfc428000 0x4000>; + }; + bimc: interconnect@fc380000 { reg = <0xfc380000 0x6a000>; compatible = "qcom,msm8974-bimc"; @@ -1417,94 +1115,418 @@ <&rpmcc RPM_SMD_CNOC_A_CLK>; }; - gpu: adreno@fdb00000 { + tsens: thermal-sensor@fc4a9000 { + compatible = "qcom,msm8974-tsens"; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #qcom,sensors = <11>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + + qfprom: qfprom@fc4bc000 { + compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + tsens_calib: calib@d0 { + reg = <0xd0 0x18>; + }; + tsens_backup: backup@440 { + reg = <0x440 0x10>; + }; + }; + + spmi_bus: spmi@fc4cf000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + bam_dmux_dma: dma-controller@fc834000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xfc834000 0x7000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + }; + + remoteproc_mss: remoteproc@fc880000 { + compatible = "qcom,msm8974-mss-pil"; + reg = <0xfc880000 0x100>, <0xfc820000 0x020>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "bus", "mem", "xo"; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + status = "disabled"; - compatible = "qcom,adreno-330.1", - "qcom,adreno"; - reg = <0xfdb00000 0x10000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "kgsl_3d0_irq"; - clock-names = "core", - "iface", - "mem_iface"; - clocks = <&mmcc OXILI_GFX3D_CLK>, - <&mmcc OXILICX_AHB_CLK>, - <&mmcc OXILICX_AXI_CLK>; - sram = <&gmu_sram>; - power-domains = <&mmcc OXILICX_GDSC>; - operating-points-v2 = <&gpu_opp_table>; + mba { + memory-region = <&mba_region>; + }; - interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, - <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; - interconnect-names = "gfx-mem", - "ocmem"; + mpss { + memory-region = <&mpss_region>; + }; - // iommus = <&gpu_iommu 0>; + bam_dmux: bam-dmux { + compatible = "qcom,bam-dmux"; - gpu_opp_table: opp_table { - compatible = "operating-points-v2"; + interrupt-parent = <&modem_smsm>; + interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pc", "pc-ack"; - opp-320000000 { - opp-hz = /bits/ 64 <320000000>; + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pc", "pc-ack"; + + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; + dma-names = "tx", "rx"; + }; + + smd-edge { + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 12>; + qcom,smd-edge = <0>; + + label = "modem"; + }; + }; + + tcsr_mutex_block: syscon@fd484000 { + compatible = "syscon"; + reg = <0xfd484000 0x2000>; + }; + + tcsr: syscon@fd4a0000 { + compatible = "syscon"; + reg = <0xfd4a0000 0x10000>; + }; + + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8974-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + sdc1_off: sdc1-off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; }; - opp-27000000 { - opp-hz = /bits/ 64 <27000000>; + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2-off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + cd { + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + }; + }; + + blsp1_uart2_default: blsp1-uart2-default { + rx { + pins = "gpio5"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-pull-up; + }; + + tx { + pins = "gpio4"; + function = "blsp_uart2"; + drive-strength = <4>; + bias-disable; + }; + }; + + blsp2_uart1_default: blsp2-uart1-default { + tx-rts { + pins = "gpio41", "gpio44"; + function = "blsp_uart7"; + drive-strength = <2>; + bias-disable; + }; + + rx-cts { + pins = "gpio42", "gpio43"; + function = "blsp_uart7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp2_uart1_sleep: blsp2-uart1-sleep { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_uart4_default: blsp2-uart4-default { + tx-rts { + pins = "gpio53", "gpio56"; + function = "blsp_uart10"; + drive-strength = <2>; + bias-disable; + }; + + rx-cts { + pins = "gpio54", "gpio55"; + function = "blsp_uart10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_i2c1_default: blsp1-i2c1-default { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c1_sleep: blsp1-i2c1-sleep { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp1_i2c2_default: blsp1-i2c2-default { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp1_i2c3_default: blsp1-i2c3-default { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-pull-up; + }; + + /* BLSP1_I2C4 info is missing */ + + /* BLSP1_I2C5 info is missing */ + + blsp1_i2c6_default: blsp1-i2c6-default { + pins = "gpio29", "gpio30"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c6_sleep: blsp1-i2c6-sleep { + pins = "gpio29", "gpio30"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-pull-up; + }; + /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ + + /* BLSP2_I2C1 info is missing */ + + blsp2_i2c2_default: blsp2-i2c2-default { + pins = "gpio47", "gpio48"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep { + pins = "gpio47", "gpio48"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-pull-up; + }; + + /* BLSP2_I2C3 info is missing */ + + /* BLSP2_I2C4 info is missing */ + + blsp2_i2c5_default: blsp2-i2c5-default { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c5_sleep: blsp2-i2c5-sleep { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp2_i2c6_default: blsp2-i2c6-default { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c6_sleep: blsp2-i2c6-sleep { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + drive-strength = <2>; + bias-pull-up; + }; + + spi8_default: spi8_default { + mosi { + pins = "gpio45"; + function = "blsp_spi8"; + }; + miso { + pins = "gpio46"; + function = "blsp_spi8"; + }; + cs { + pins = "gpio47"; + function = "blsp_spi8"; + }; + clk { + pins = "gpio48"; + function = "blsp_spi8"; }; }; }; - mdss: mdss@fd900000 { - status = "disabled"; + mmcc: clock-controller@fd8c0000 { + compatible = "qcom,mmcc-msm8974"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xfd8c0000 0x6000>; + }; + mdss: mdss@fd900000 { compatible = "qcom,mdss"; - reg = <0xfd900000 0x100>, - <0xfd924000 0x1000>; - reg-names = "mdss_phys", - "vbif_phys"; + reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; + reg-names = "mdss_phys", "vbif_phys"; power-domains = <&mmcc MDSS_GDSC>; clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "vsync"; + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "vsync"; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; + status = "disabled"; + #address-cells = <1>; #size-cells = <1>; ranges; mdp: mdp@fd900000 { - status = "disabled"; - compatible = "qcom,mdp5"; reg = <0xfd900100 0x22000>; reg-names = "mdp_phys"; interrupt-parent = <&mdss>; - interrupts = <0 0>; + interrupts = <0>; clocks = <&mmcc MDSS_AHB_CLK>, <&mmcc MDSS_AXI_CLK>, <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "core", - "vsync"; + clock-names = "iface", "bus", "core", "vsync"; interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; interconnect-names = "mdp0-mem"; @@ -1523,38 +1545,39 @@ }; dsi0: dsi@fd922800 { - status = "disabled"; - compatible = "qcom,mdss-dsi-ctrl"; reg = <0xfd922800 0x1f8>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; - assigned-clocks = <&mmcc BYTE0_CLK_SRC>, - <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi_phy0 0>, - <&dsi_phy0 1>; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_BYTE0_CLK>, - <&mmcc MDSS_PCLK0_CLK>, - <&mmcc MDSS_ESC0_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>; + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; clock-names = "mdp_core", - "iface", - "bus", - "byte", - "pixel", - "core", - "core_mmss"; - - phys = <&dsi_phy0>; + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; + + phys = <&dsi0_phy>; phy-names = "dsi-phy"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1574,29 +1597,119 @@ }; }; - dsi_phy0: dsi-phy@fd922a00 { - status = "disabled"; - + dsi0_phy: dsi-phy@fd922a00 { compatible = "qcom,dsi-phy-28nm-hpm"; reg = <0xfd922a00 0xd4>, <0xfd922b00 0x280>, <0xfd922d80 0x30>; reg-names = "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; + "dsi_phy", + "dsi_phy_regulator"; #clock-cells = <1>; #phy-cells = <0>; - qcom,dsi-phy-index = <0>; clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + gpu: adreno@fdb00000 { + compatible = "qcom,adreno-330.1", "qcom,adreno"; + reg = <0xfdb00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&mmcc OXILI_GFX3D_CLK>, + <&mmcc OXILICX_AHB_CLK>, + <&mmcc OXILICX_AXI_CLK>; + clock-names = "core", "iface", "mem_iface"; + + sram = <&gmu_sram>; + power-domains = <&mmcc OXILICX_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, + <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; + interconnect-names = "gfx-mem", "ocmem"; + + // iommus = <&gpu_iommu 0>; + + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-27000000 { + opp-hz = /bits/ 64 <27000000>; + }; + }; + }; + + sram@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x180000>; + reg-names = "ctrl", "mem"; + ranges = <0 0xfec00000 0x180000>; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x100000>; }; }; - imem@fe805000 { + remoteproc_adsp: remoteproc@fe200000 { + compatible = "qcom,msm8974-adsp-pil"; + reg = <0xfe200000 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&adsp_region>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + status = "disabled"; - compatible = "syscon", "simple-mfd"; + + smd-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 8>; + qcom,smd-edge = <1>; + label = "lpass"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + imem: sram@fe805000 { + compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; reg = <0xfe805000 0x1000>; reboot-mode { @@ -1606,76 +1719,194 @@ }; }; - smd { - compatible = "qcom,smd"; + tcsr_mutex: tcsr-mutex { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x80>; - rpm { - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; + #hwlock-cells = <1>; + }; - rpm_requests { - compatible = "qcom,rpm-msm8974"; - qcom,smd-channels = "rpm_requests"; + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; - #clock-cells = <1>; + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + q6-dsp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + q6_dsp_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modemtx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + modemtx_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + video_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + + trips { + wlan_alert0: trip-point0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; }; + }; + }; + + gpu-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; - pm8841-regulators { - compatible = "qcom,rpm-pm8841-regulators"; - - pm8841_s1: s1 {}; - pm8841_s2: s2 {}; - pm8841_s3: s3 {}; - pm8841_s4: s4 {}; - pm8841_s5: s5 {}; - pm8841_s6: s6 {}; - pm8841_s7: s7 {}; - pm8841_s8: s8 {}; + thermal-sensors = <&tsens 9>; + + trips { + gpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; }; + }; + }; - pm8941-regulators { - compatible = "qcom,rpm-pm8941-regulators"; - - pm8941_s1: s1 {}; - pm8941_s2: s2 {}; - pm8941_s3: s3 {}; - - pm8941_l1: l1 {}; - pm8941_l2: l2 {}; - pm8941_l3: l3 {}; - pm8941_l4: l4 {}; - pm8941_l5: l5 {}; - pm8941_l6: l6 {}; - pm8941_l7: l7 {}; - pm8941_l8: l8 {}; - pm8941_l9: l9 {}; - pm8941_l10: l10 {}; - pm8941_l11: l11 {}; - pm8941_l12: l12 {}; - pm8941_l13: l13 {}; - pm8941_l14: l14 {}; - pm8941_l15: l15 {}; - pm8941_l16: l16 {}; - pm8941_l17: l17 {}; - pm8941_l18: l18 {}; - pm8941_l19: l19 {}; - pm8941_l20: l20 {}; - pm8941_l21: l21 {}; - pm8941_l22: l22 {}; - pm8941_l23: l23 {}; - pm8941_l24: l24 {}; - - pm8941_lvs1: lvs1 {}; - pm8941_lvs2: lvs2 {}; - pm8941_lvs3: lvs3 {}; + gpu-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 10>; + + trips { + gpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; }; }; }; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 2 0xf08>, + <GIC_PPI 3 0xf08>, + <GIC_PPI 4 0xf08>, + <GIC_PPI 1 0xf08>; + clock-frequency = <19200000>; + }; + vreg_boost: vreg-boost { compatible = "regulator-fixed"; @@ -1692,6 +1923,7 @@ pinctrl-names = "default"; pinctrl-0 = <&boost_bypass_n_pin>; }; + vreg_vph_pwr: vreg-vph-pwr { compatible = "regulator-fixed"; regulator-name = "vph-pwr"; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts new file mode 100644 index 000000000000..ff6e0066768b --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts @@ -0,0 +1,464 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +/ { + model = "Fairphone 2"; + compatible = "fairphone,fp2", "qcom,msm8974"; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_CAMERA>; + wakeup-source; + debounce-interval = <15>; + }; + + key-volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + wakeup-source; + debounce-interval = <15>; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + wakeup-source; + debounce-interval = <15>; + }; + }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; + vcc-supply = <&pm8941_l18>; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + touchscreen@41 { + compatible = "ilitek,ili2120"; + reg = <0x41>; + interrupt-parent = <&tlmm>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&imem { + reboot-mode { + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; + }; +}; + +&otg { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "okay"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio1", "gpio2", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = <PM8941_GPIO_S3>; + }; +}; + +&pm8941_lpg { + status = "okay"; + + qcom,power-source = <1>; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@7 { + reg = <7>; + color = <LED_COLOR_ID_RED>; + }; + + led@6 { + reg = <6>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_BLUE>; + }; + }; +}; + +&pronto { + status = "okay"; + + vddmx-supply = <&pm8841_s1>; + vddcx-supply = <&pm8841_s2>; + vddpx-supply = <&pm8941_s3>; + + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; + + iris { + vddxo-supply = <&pm8941_l6>; + vddrfa-supply = <&pm8941_l11>; + vddpa-supply = <&pm8941_l19>; + vdddig-supply = <&pm8941_s3>; + }; + + smd-edge { + qcom,remote-pid = <4>; + label = "pronto"; + + wcnss { + status = "okay"; + }; + }; +}; + +&remoteproc_adsp { + status = "okay"; + cx-supply = <&pm8841_s2>; +}; + +&remoteproc_mss { + status = "okay"; + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; +}; + +&rpm_requests { + pm8841-regulators { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + }; + + pm8941-regulators { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3350000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; +}; + +&smbb { + usb-charge-current-limit = <1500000>; + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <1500000>; + qcom,fast-charge-safe-voltage = <4380000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,auto-recharge-threshold-voltage = <4240000>; + qcom,minimum-input-voltage = <4450000>; +}; + +&tlmm { + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_on: sdc2-on { + clk { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + wcnss_pin_a: wcnss-pin-active { + wlan { + pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "wlan"; + + drive-strength = <6>; + bias-pull-down; + }; + + bt { + pins = "gpio35", "gpio43", "gpio44"; + function = "bt"; + + drive-strength = <2>; + bias-pull-down; + }; + + fm { + pins = "gpio41", "gpio42"; + function = "fm"; + + drive-strength = <2>; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts new file mode 100644 index 000000000000..983e10c3d863 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts @@ -0,0 +1,815 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro.dtsi" +#include "qcom-pma8084.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Samsung Galaxy S5"; + compatible = "samsung,klte", "qcom,msm8974"; + + aliases { + serial0 = &blsp1_uart1; + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_3; /* SDC2 SD card slot */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-volume-down { + label = "volume_down"; + gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <15>; + }; + + key-home { + label = "home_key"; + gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_HOMEPAGE>; + wakeup-source; + debounce-interval = <15>; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + }; + }; + + i2c-gpio-touchkey { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + sda-gpios = <&tlmm 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_touchkey_pins>; + + touchkey@20 { + compatible = "cypress,tm2-touchkey"; + reg = <0x20>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_pin>; + + vcc-supply = <&max77826_ldo15>; + vdd-supply = <&pma8084_l19>; + + linux,keycodes = <KEY_APPSELECT KEY_BACK>; + }; + }; + + i2c-gpio-led { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + scl-gpios = <&tlmm 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_led_gpioex_pins>; + + i2c-gpio,delay-us = <2>; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + + gpio-controller; + #gpio-cells = <2>; + + vcc-supply = <&pma8084_s4>; + + pinctrl-names = "default"; + pinctrl-0 = <&gpioex_pin>; + + reset-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + }; + + led-controller@30 { + compatible = "panasonic,an30259a"; + reg = <0x30>; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + }; + + led@3 { + reg = <3>; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + }; + }; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_expander 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vreg_panel: panel-regulator { + compatible = "regulator-fixed"; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_en_pin>; + + regulator-name = "panel-vddr-reg"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + gpio = <&pma8084_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /delete-node/ vreg-boost; +}; + +&blsp1_i2c2 { + status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&max77826_ldo13>; + vio-supply = <&pma8084_lvs2>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_pin>; + + syna,startup-delay-ms = <100>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp1_i2c6 { + status = "okay"; + + pmic@60 { + reg = <0x60>; + compatible = "maxim,max77826"; + + regulators { + max77826_ldo1: LDO1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + max77826_ldo2: LDO2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + max77826_ldo3: LDO3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + max77826_ldo4: LDO4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo5: LDO5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo6: LDO6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo7: LDO7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo8: LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo9: LDO9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo10: LDO10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo11: LDO11 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo12: LDO12 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo13: LDO13 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo14: LDO14 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo15: LDO15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_buck: BUCK { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + max77826_buckboost: BUCKBOOST { + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_i2c6 { + status = "okay"; + + fuelgauge@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x56>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&fuelgauge_pin>; + }; +}; + +&blsp2_uart2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart2_pins_active>; + pinctrl-1 = <&blsp2_uart2_pins_sleep>; + + bluetooth { + compatible = "brcm,bcm43540-bt"; + max-speed = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_pins>; + device-wakeup-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&tlmm>; + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + }; +}; + +&dsi0 { + status = "okay"; + + vdda-supply = <&pma8084_l2>; + vdd-supply = <&pma8084_l22>; + vddio-supply = <&pma8084_l12>; + + panel: panel@0 { + reg = <0>; + compatible = "samsung,s6e3fa2"; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_te_pin &panel_rst_pin>; + + iovdd-supply = <&pma8084_lvs4>; + vddr-supply = <&vreg_panel>; + + reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>; + te-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + + vddio-supply = <&pma8084_l12>; +}; + +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&otg { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "okay"; + + v1p8-supply = <&pma8084_l6>; + v3p3-supply = <&pma8084_l24>; + + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; +}; + +&pma8084_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio2", "gpio3", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = <PMA8084_GPIO_S4>; + }; + + touchkey_pin: touchkey-int-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-enable; + power-source = <PMA8084_GPIO_S4>; + }; + + touch_pin: touchscreen-int-state { + pins = "gpio8"; + function = "normal"; + bias-disable; + input-enable; + power-source = <PMA8084_GPIO_S4>; + }; + + panel_en_pin: panel-en-state { + pins = "gpio14"; + function = "normal"; + bias-pull-up; + power-source = <PMA8084_GPIO_S4>; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + }; + + wlan_sleep_clk_pin: wlan-sleep-clk-state { + pins = "gpio16"; + function = "func2"; + + output-high; + power-source = <PMA8084_GPIO_S4>; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; + }; + + panel_rst_pin: panel-rst-state { + pins = "gpio17"; + function = "normal"; + bias-disable; + power-source = <PMA8084_GPIO_S4>; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + }; + + fuelgauge_pin: fuelgauge-int-state { + pins = "gpio21"; + function = "normal"; + bias-disable; + input-enable; + power-source = <PMA8084_GPIO_S4>; + }; +}; + +&remoteproc_adsp { + status = "okay"; + cx-supply = <&pma8084_s2>; +}; + +&remoteproc_mss { + status = "okay"; + cx-supply = <&pma8084_s2>; + mss-supply = <&pma8084_s6>; + mx-supply = <&pma8084_s1>; + pll-supply = <&pma8084_l12>; +}; + +&rpm_requests { + pma8084-regulators { + compatible = "qcom,rpm-pma8084-regulators"; + + pma8084_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + pma8084_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_s5: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pma8084_s6: s6 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l3: l3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pma8084_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pma8084_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l19: l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pma8084_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pma8084_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pma8084_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pma8084_l25: l25 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + }; + + pma8084_l26: l26 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l27: l27 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_lvs1: lvs1 {}; + pma8084_lvs2: lvs2 {}; + pma8084_lvs3: lvs3 {}; + pma8084_lvs4: lvs4 {}; + + pma8084_5vs1: 5vs1 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pma8084_l20>; + vqmmc-supply = <&pma8084_s4>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "okay"; + max-frequency = <100000000>; + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pma8084_s4>; + non-removable; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + + interrupt-parent = <&tlmm>; + interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>; + }; +}; + +&sdhc_3 { + status = "okay"; + max-frequency = <100000000>; + vmmc-supply = <&pma8084_l21>; + vqmmc-supply = <&pma8084_l13>; + + /* + * cd-gpio is intentionally disabled. If enabled, an SD card + * present during boot is not initialized correctly. Without + * cd-gpios the driver resorts to polling, so hotplug works. + */ + pinctrl-names = "default"; + pinctrl-0 = <&sdc3_on /* &sdhc3_cd_pin */>; + /* cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; */ +}; + +&tlmm { + /* This seems suspicious, but somebody with this device should look into it. */ + blsp2_uart2_pins_active: blsp2-uart2-pins-active { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "blsp_uart8"; + drive-strength = <8>; + bias-disable; + }; + + blsp2_uart2_pins_sleep: blsp2-uart2-pins-sleep { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + bt_pins: bt-pins { + hostwake { + pins = "gpio75"; + function = "gpio"; + drive-strength = <16>; + input-enable; + }; + + devwake { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + }; + }; + + sdc1_on: sdhc1-on { + clk { + pins = "sdc1_clk"; + drive-strength = <4>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <4>; + bias-pull-up; + }; + }; + + sdc3_on: sdc3-on { + pins = "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; + + sdhc3_cd_pin: sdc3-cd-on { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdc2_on: sdhc2-on { + clk { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + i2c_touchkey_pins: i2c-touchkey { + pins = "gpio95", "gpio96"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + i2c_led_gpioex_pins: i2c-led-gpioex { + pins = "gpio120", "gpio121"; + function = "gpio"; + input-enable; + bias-pull-down; + }; + + gpioex_pin: gpioex { + pins = "gpio145"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + wifi_pin: wifi { + pins = "gpio92"; + function = "gpio"; + input-enable; + bias-pull-down; + }; + + panel_te_pin: panel { + pins = "gpio12"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts new file mode 100644 index 000000000000..3f45f5c5d37b --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -0,0 +1,638 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +/ { + model = "Sony Xperia Z2 Tablet"; + compatible = "sony,xperia-castor", "qcom,msm8974"; + + aliases { + serial0 = &blsp1_uart2; + serial1 = &blsp2_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + key-camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_CAMERA>; + }; + + key-camera-focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_CAMERA_FOCUS>; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + vreg_bl_vddio: lcd-backlight-vddio { + compatible = "regulator-fixed"; + regulator-name = "vreg_bl_vddio"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + + gpio = <&tlmm 69 0>; + enable-active-high; + + vin-supply = <&pm8941_s3>; + startup-delay-us = <70000>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_backlight_en_pin_a>; + }; + + vreg_vsp: lcd-dcdc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_vsp"; + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; + + gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_dcdc_en_pin_a>; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_pin>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_i2c2 { + status = "okay"; + clock-frequency = <355000>; + + synaptics@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + + interrupt-parent = <&tlmm>; + interrupts = <86 IRQ_TYPE_EDGE_FALLING>; + + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_pin>; + + syna,startup-delay-ms = <10>; + + rmi-f01@1 { + reg = <0x1>; + syna,nosleep = <1>; + }; + + rmi-f11@11 { + reg = <0x11>; + syna,f11-flip-x = <1>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <355000>; + + lp8566_wled: backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + power-supply = <&vreg_bl_vddio>; + + bl-name = "backlight"; + dev-ctrl = /bits/ 8 <0x05>; + init-brt = /bits/ 8 <0x3f>; + rom_a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0xff>; + }; + rom_a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x3f>; + }; + rom_a2h { + rom-addr = /bits/ 8 <0xa2>; + rom-val = /bits/ 8 <0x20>; + }; + rom_a3h { + rom-addr = /bits/ 8 <0xa3>; + rom-val = /bits/ 8 <0x5e>; + }; + rom_a4h { + rom-addr = /bits/ 8 <0xa4>; + rom-val = /bits/ 8 <0x02>; + }; + rom_a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x04>; + }; + rom_a6h { + rom-addr = /bits/ 8 <0xa6>; + rom-val = /bits/ 8 <0x80>; + }; + rom_a7h { + rom-addr = /bits/ 8 <0xa7>; + rom-val = /bits/ 8 <0xf7>; + }; + rom_a9h { + rom-addr = /bits/ 8 <0xa9>; + rom-val = /bits/ 8 <0x80>; + }; + rom_aah { + rom-addr = /bits/ 8 <0xaa>; + rom-val = /bits/ 8 <0x0f>; + }; + rom_aeh { + rom-addr = /bits/ 8 <0xae>; + rom-val = /bits/ 8 <0x0f>; + }; + }; +}; + +&blsp2_uart1 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_pin>, <&bt_dev_wake_pin>, <&bt_reg_on_pin>; + + host-wakeup-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&pm8941_gpios 16 GPIO_ACTIVE_HIGH>; + }; +}; + +&otg { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "okay"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; +}; + +&pm8941_coincell { + status = "okay"; + + qcom,rset-ohms = <2100>; + qcom,vset-millivolts = <3000>; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio2", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = <PM8941_GPIO_S3>; + }; + + bt_reg_on_pin: bt-reg-on-state { + pins = "gpio16"; + function = "normal"; + + output-low; + power-source = <PM8941_GPIO_S3>; + }; + + wlan_sleep_clk_pin: wl-sleep-clk-state { + pins = "gpio17"; + function = "func2"; + + output-high; + power-source = <PM8941_GPIO_S3>; + }; + + wlan_regulator_pin: wl-reg-active-state { + pins = "gpio18"; + function = "normal"; + + bias-disable; + power-source = <PM8941_GPIO_S3>; + }; + + lcd_dcdc_en_pin_a: lcd-dcdc-en-active-state { + pins = "gpio20"; + function = "normal"; + + bias-disable; + power-source = <PM8941_GPIO_S3>; + input-disable; + output-low; + }; + +}; + +&pm8941_lpg { + status = "okay"; + + qcom,power-source = <1>; + + rgb-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_BLUE>; + }; + + led@6 { + reg = <6>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@7 { + reg = <7>; + color = <LED_COLOR_ID_RED>; + }; + }; +}; + +&rpm_requests { + pm8941-regulators { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <154000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s4: s4 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <500000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + + pm8941_lvs3: lvs3 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; +}; + +&sdhc_3 { + status = "okay"; + + max-frequency = <100000000>; + vmmc-supply = <&vreg_wlan>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc3_on>; + + #address-cells = <1>; + #size-cells = <0>; + + bcrmf@1 { + compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + brcm,drive-strength = <10>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin>; + }; +}; + +&smbb { + qcom,fast-charge-safe-current = <1500000>; + qcom,fast-charge-current-limit = <1500000>; + qcom,dc-current-limit = <1800000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,fast-charge-low-threshold-voltage = <3400000>; + qcom,auto-recharge-threshold-voltage = <4200000>; + qcom,minimum-input-voltage = <4300000>; +}; + +&tlmm { + lcd_backlight_en_pin_a: lcd-backlight-vddio { + pins = "gpio69"; + drive-strength = <10>; + output-low; + bias-disable; + }; + + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_on: sdc2-on { + clk { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + + cd { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + sdc3_on: sdc3-on { + clk { + pins = "gpio40"; + function = "sdc3"; + drive-strength = <10>; + bias-disable; + }; + + cmd { + pins = "gpio39"; + function = "sdc3"; + drive-strength = <10>; + bias-pull-up; + }; + + data { + pins = "gpio35", "gpio36", "gpio37", "gpio38"; + function = "sdc3"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + ts_int_pin: ts-int-pin { + pins = "gpio86"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + bt_host_wake_pin: bt-host-wake { + pins = "gpio95"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + bt_dev_wake_pin: bt-dev-wake { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom-msm8974pro.dtsi index b64c28036dd0..58df6e75ab6d 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974pro.dtsi @@ -1,23 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974.dtsi" -/ { - soc { - sdhci@f9824900 { - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>, - <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, - <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; - clock-names = "core", "iface", "xo", "cal", "sleep"; - }; +&gcc { + compatible = "qcom,gcc-msm8974pro"; +}; - clock-controller@fc400000 { - compatible = "qcom,gcc-msm8974pro"; - }; +&gpu { + compatible = "qcom,adreno-330.2", "qcom,adreno"; +}; - adreno@fdb00000 { - compatible = "qcom,adreno-330.2", - "qcom,adreno"; - }; - }; +&sdhc_1 { + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>, + <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, + <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; + clock-names = "iface", "core", "xo", "cal", "sleep"; }; diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom-pm8226.dtsi index dddb5150dfd7..9b7d9d04ded6 100644 --- a/arch/arm/boot/dts/qcom-pm8226.dtsi +++ b/arch/arm/boot/dts/qcom-pm8226.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/iio/qcom,spmi-vadc.h> &spmi_bus { pm8226_0: pm8226@0 { @@ -16,6 +17,79 @@ debounce = <15625>; bias-pull-up; }; + + smbb: charger@1000 { + compatible = "qcom,pm8226-charger"; + reg = <0x1000>; + interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "chg-done", + "chg-fast", + "chg-trkl", + "bat-temp-ok", + "bat-present", + "chg-gone", + "usb-valid", + "dc-valid"; + + chg_otg: otg-vbus { }; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pm8226_vadc: adc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@7 { + reg = <VADC_VSYS>; + qcom,pre-scaling = <1 3>; + label = "vph_pwr"; + }; + adc-chan@8 { + reg = <VADC_DIE_TEMP>; + label = "die_temp"; + }; + adc-chan@9 { + reg = <VADC_REF_625MV>; + label = "ref_625mv"; + }; + adc-chan@a { + reg = <VADC_REF_1250MV>; + label = "ref_1250mv"; + }; + adc-chan@e { + reg = <VADC_GND_REF>; + }; + adc-chan@f { + reg = <VADC_VDD_VADC>; + }; + }; + + pm8226_mpps: mpps@a000 { + compatible = "qcom,pm8226-mpp", "qcom,spmi-mpp"; + reg = <0xa000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8226_mpps 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pm8226_1: pm8226@1 { @@ -23,5 +97,15 @@ reg = <0x1 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm8226_spmi_regulators: pm8226-regulators { + compatible = "qcom,pm8226-regulators"; + }; + + pm8226_vib: vibrator@c000 { + compatible = "qcom,pm8916-vib"; + reg = <0xc000>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi index 2caf71eacb52..b5cdde034d18 100644 --- a/arch/arm/boot/dts/qcom-pm8841.dtsi +++ b/arch/arm/boot/dts/qcom-pm8841.dtsi @@ -24,6 +24,7 @@ compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index da00b8f5eecd..9cd49deb9fa7 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -68,7 +68,7 @@ interrupt-controller; #interrupt-cells = <2>; - boost_bypass_n_pin: boost-bypass { + boost_bypass_n_pin: boost-bypass-state { pins = "gpio21"; function = "normal"; }; @@ -93,7 +93,7 @@ #thermal-sensor-cells = <0>; }; - pm8941_vadc: vadc@3100 { + pm8941_vadc: adc@3100 { compatible = "qcom,spmi-vadc"; reg = <0x3100>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; @@ -131,7 +131,7 @@ qcom,external-resistor-micro-ohms = <10000>; }; - coincell@2800 { + pm8941_coincell: coincell@2800 { compatible = "qcom,pm8941-coincell"; reg = <0x2800>; status = "disabled"; @@ -144,6 +144,16 @@ #address-cells = <1>; #size-cells = <0>; + pm8941_lpg: pwm { + compatible = "qcom,pm8941-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pm8941_wled: wled@d800 { compatible = "qcom,pm8941-wled"; reg = <0xd800>; diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi index 7b8a8d9695da..e77602e9f95c 100644 --- a/arch/arm/boot/dts/qcom-pma8084.dtsi +++ b/arch/arm/boot/dts/qcom-pma8084.dtsi @@ -56,7 +56,7 @@ io-channel-names = "thermal"; }; - pma8084_vadc: vadc@3100 { + pma8084_vadc: adc@3100 { compatible = "qcom,spmi-vadc"; reg = <0x3100>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm/boot/dts/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom-pmx55.dtsi index 6571b88d018a..e1b869480bbd 100644 --- a/arch/arm/boot/dts/qcom-pmx55.dtsi +++ b/arch/arm/boot/dts/qcom-pmx55.dtsi @@ -16,7 +16,7 @@ #address-cells = <1>; #size-cells = <0>; - power-on@800 { + pon@800 { compatible = "qcom,pm8916-pon"; reg = <0x0800>; @@ -69,6 +69,7 @@ compatible = "qcom,pmx55-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pmx55_gpios 0 0 11>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom-pmx65.dtsi new file mode 100644 index 000000000000..abf229a8b75a --- /dev/null +++ b/arch/arm/boot/dts/qcom-pmx65.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + pmic@1 { + compatible = "qcom,pmx65", "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmx65_temp: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmx65_gpios: pinctrl@8800 { + compatible = "qcom,pmx65-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmx65_gpios 0 0 16>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 8ac0492c7659..c72540223fa9 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -206,7 +206,7 @@ blsp1_uart3: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x00831000 0x200>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc 30>, <&gcc 9>; clock-names = "core", "iface"; @@ -275,13 +275,6 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sdx55-ipa-virt"; - reg = <0x01e00000 0x100000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - qpic_bam: dma-controller@1b04000 { compatible = "qcom,bam-v1.7.0"; reg = <0x01b04000 0x1c000>; @@ -395,7 +388,7 @@ reg = <0x01fc0000 0x1000>; }; - sdhc_1: sdhci@8804000 { + sdhc_1: mmc@8804000 { compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, @@ -413,7 +406,7 @@ <0x40000000 0xf1d>, <0x40000f20 0xc8>, <0x40001000 0x1000>, - <0x40002000 0x10000>, + <0x40200000 0x100000>, <0x01c03000 0x3000>; reg-names = "parf", "dbi", "elbi", "atu", "addr_space", "mmio"; @@ -490,10 +483,13 @@ clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, <&gcc GCC_USB30_MASTER_CLK>, <&gcc GCC_USB30_MSTR_AXI_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, <&gcc GCC_USB30_MASTER_CLK>; @@ -536,7 +532,7 @@ reg = <0x0c264000 0x1000>; }; - spmi_bus: qcom,spmi@c440000 { + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0c440000 0x0000d00>, <0x0c600000 0x2000000>, @@ -565,8 +561,8 @@ #interrupt-cells = <2>; }; - imem@1468f000 { - compatible = "simple-mfd"; + sram@1468f000 { + compatible = "qcom,sdx55-imem", "syscon", "simple-mfd"; reg = <0x1468f000 0x1000>; #address-cells = <1>; @@ -770,7 +766,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 59457da8e5f1..85ea02d8362d 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -5,6 +5,10 @@ /dts-v1/; #include "qcom-sdx65.dtsi" +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <arm64/qcom/pmk8350.dtsi> +#include <arm64/qcom/pm8150b.dtsi> +#include "qcom-pmx65.dtsi" / { model = "Qualcomm Technologies, Inc. SDX65 MTP"; @@ -18,8 +22,270 @@ chosen { stdout-path = "serial0:115200n8"; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mpss_dsm: memory@8c400000 { + no-map; + reg = <0x8c400000 0x3200000>; + }; + + ipa_fw_mem: memory@8fced000 { + no-map; + reg = <0x8fced000 0x10000>; + }; + + mpss_adsp_mem: memory@90800000 { + no-map; + reg = <0x90800000 0x10000000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_bob_3p3: pmx65_bob { + compatible = "regulator-fixed"; + regulator-name = "vreg_bob_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + pmx65-rpmh-regulators { + compatible = "qcom,pmx65-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-supply = <&vreg_s2b_1p224>; + vdd-l2-l18-supply = <&vreg_s2b_1p224>; + vdd-l3-supply = <&vreg_s8b_0p824>; + vdd-l4-supply = <&vreg_s7b_0p936>; + vdd-l5-l6-l16-supply = <&vreg_s4b_1p824>; + vdd-l7-supply = <&vreg_s3b_0p776>; + vdd-l8-l9-supply = <&vreg_s8b_0p824>; + vdd-l10-supply = <&vreg_bob_3p3>; + vdd-l11-l13-supply = <&vreg_bob_3p3>; + vdd-l12-supply = <&vreg_s2b_1p224>; + vdd-l14-supply = <&vreg_s3b_0p776>; + vdd-l15-supply = <&vreg_s2b_1p224>; + vdd-l17-supply = <&vreg_s8b_0p824>; + vdd-l19-supply = <&vreg_s3b_0p776>; + vdd-l20-supply = <&vreg_s7b_0p936>; + vdd-l21-supply = <&vreg_s7b_0p936>; + + vreg_s2b_1p224: smps2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_s3b_0p776: smps3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_s4b_1p824: smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + }; + + vreg_s7b_0p936: smps7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_s8b_0p824: smps8 { + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1300000>; + }; + + vreg_l1b_1p2: ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo2 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo3 { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4b_0p88: ldo4 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_1p8: ldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo7 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo8 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo9 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10b_3p08: ldo10 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo13 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo14 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo15 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo16 { + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo17 { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo19 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo20 { + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + ldo21 { + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; }; &blsp1_uart3 { - status = "ok"; + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + /* ico and efs2 partitions are secured */ + secure-regions = /bits/ 64 <0x500000 0x500000 + 0xa00000 0xb00000>; + }; +}; + +&remoteproc_mpss { + status = "okay"; + memory-region = <&mpss_adsp_mem>; +}; + +&usb { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_hsphy { + status = "okay"; + vdda-pll-supply = <&vreg_l4b_0p88>; + vdda33-supply = <&vreg_l10b_3p08>; + vdda18-supply = <&vreg_l5b_1p8>; +}; + +&usb_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l4b_0p88>; + vdda-pll-supply = <&vreg_l1b_1p2>; }; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 796641d30e06..4cd405db5500 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/clock/qcom,gcc-sdx65.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / { @@ -36,6 +37,12 @@ clock-output-names = "sleep_clk"; #clock-cells = <0>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; }; cpus { @@ -47,9 +54,50 @@ compatible = "arm,cortex-a7"; reg = <0x0>; enable-method = "psci"; + clocks = <&apcs>; + power-domains = <&rpmhpd SDX65_CX_AO>; + power-domain-names = "rpmhpd"; + operating-points-v2 = <&cpu_opp_table>; }; }; + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sdx65", "qcom,scm"; + }; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sdx65-mc-virt"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -60,11 +108,89 @@ #size-cells = <1>; ranges; + tz_heap_mem: memory@8fcad000 { + no-map; + reg = <0x8fcad000 0x40000>; + }; + + secdata_mem: memory@8fcfd000 { + no-map; + reg = <0x8fcfd000 0x1000>; + }; + + hyp_mem: memory@8fd00000 { + no-map; + reg = <0x8fd00000 0x80000>; + }; + + access_control_mem: memory@8fd80000 { + no-map; + reg = <0x8fd80000 0x80000>; + }; + + aop_mem: memory@8fe00000 { + no-map; + reg = <0x8fe00000 0x20000>; + }; + + smem_mem: memory@8fe20000 { + compatible = "qcom,smem"; + reg = <0x8fe20000 0xc0000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + cmd_db: reserved-memory@8fee0000 { compatible = "qcom,cmd-db"; reg = <0x8fee0000 0x20000>; no-map; }; + + tz_mem: memory@8ff00000 { + no-map; + reg = <0x8ff00000 0x100000>; + }; + + tz_apps_mem: memory@90000000 { + no-map; + reg = <0x90000000 0x500000>; + }; + + llcc_tcm_mem: memory@15800000 { + no-map; + reg = <0x15800000 0x800000>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apcs 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; soc: soc { @@ -78,6 +204,7 @@ reg = <0x00100000 0x001f7400>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -91,6 +218,208 @@ status = "disabled"; }; + usb_hsphy: phy@ff4000 { + compatible = "qcom,usb-snps-hs-7nm-phy"; + reg = <0xff4000 0x120>; + #phy-cells = <0>; + status = "disabled"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_BCR>; + }; + + usb_qmpphy: phy@ff6000 { + compatible = "qcom,sdx65-qmp-usb3-uni-phy"; + reg = <0x00ff6000 0x1c8>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_EN>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB3PHY_PHY_BCR>, + <&gcc GCC_USB3_PHY_BCR>; + reset-names = "phy", "common"; + + usb_ssphy: phy@ff6200 { + reg = <0x00ff6e00 0x160>, + <0x00ff7000 0x1ec>, + <0x00ff6200 0x1e00>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sdx65-system-noc"; + reg = <0x01620000 0x31200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + qpic_bam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x01b04000 0x1c000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + status = "disabled"; + }; + + qpic_nand: nand-controller@1b30000 { + compatible = "qcom,sdx55-nand"; + reg = <0x01b30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x40000>; + #hwlock-cells = <1>; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sdx55-mpss-pas"; + reg = <0x04080000 0x4040>; + + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SDX65_CX>, + <&rpmhpd SDX65_MSS>; + power-domain-names = "cx", "mss"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; + label = "mpss"; + qcom,remote-pid = <1>; + mboxes = <&apcs 15>; + }; + }; + + sdhc_1: mmc@8804000 { + compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc"; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + mem_noc: interconnect@9680000 { + compatible = "qcom,sdx65-mem-noc"; + reg = <0x09680000 0x27200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + usb: usb@a6f8800 { + compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; + reg = <0x0a6f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_USB30_MSTR_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 18 IRQ_TYPE_EDGE_BOTH>, + <&pdc 19 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_GDSC>; + + resets = <&gcc GCC_USB30_BCR>; + + usb_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x1a0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_hsphy>, <&usb_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0x0c264000 0x1000>; + }; + + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0xd00>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,sdx65-tlmm"; reg = <0xf100000 0x300000>; @@ -112,6 +441,59 @@ interrupt-controller; }; + imem@1468f000 { + compatible = "simple-mfd"; + reg = <0x1468f000 0x1000>; + ranges = <0x0 0x1468f000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; + reg = <0x15000000 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + }; + intc: interrupt-controller@17800000 { compatible = "qcom,msm-qgic2"; interrupt-controller; @@ -121,6 +503,29 @@ <0x17802000 0x1000>; }; + a7pll: clock@17808000 { + compatible = "qcom,sdx55-a7pll"; + reg = <0x17808000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <0>; + }; + + apcs: mailbox@17810000 { + compatible = "qcom,sdx55-apcs-gcc", "syscon"; + reg = <0x17810000 0x2000>; + #mbox-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; + clock-names = "ref", "pll", "aux"; + #clock-cells = <0>; + }; + + watchdog@17817000 { + compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt"; + reg = <0x17817000 0x1000>; + clocks = <&sleep_clk>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>; @@ -202,12 +607,67 @@ <WAKE_TCS 2>, <CONTROL_TCS 1>; - rpmhcc: clock-controller@1 { + rpmhcc: clock-controller { compatible = "qcom,sdx65-rpmh-clk"; #clock-cells = <1>; clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sdx65-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + }; }; diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts index 9c0d9686fe01..69a5a44b8a2f 100644 --- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts +++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts @@ -71,10 +71,10 @@ leds { compatible = "gpio-leds"; - red { + led-red { gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>; }; - green { + led-green { gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index a01f3def1c69..0af63ddc4473 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -266,7 +266,7 @@ function = "lcd0"; }; - lcd0_mux { + lcd0-mux-hog { /* DBGMD/LCDC0/FSIA MUX */ gpio-hog; gpios = <176 0>; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts index 3c8a7c8b1fdd..4e58c54cde17 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -91,10 +91,10 @@ &gpio0 { /* Disable hogging GP0_18 to output LOW */ - /delete-node/ qspi_en; + /delete-node/ qspi-en-hog; /* Hog GP0_18 to output HIGH to enable VIN2 */ - vin2_en { + vin2-en-hog { gpio-hog; gpios = <18 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index a5a79cdbcd0e..64102b664055 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -226,7 +226,7 @@ }; &gpio0 { - touch-interrupt { + touch-interrupt-hog { gpio-hog; gpios = <24 GPIO_ACTIVE_LOW>; input; @@ -234,7 +234,7 @@ }; &gpio1 { - can-trx-en-gpio{ + can-trx-en-hog { gpio-hog; gpios = <28 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi index 5621c9ed698f..b281a4d164b0 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi @@ -37,7 +37,7 @@ &gpio0 { /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */ - qspi_en { + qspi-en-hog { gpio-hog; gpios = <18 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 420e0b3259d4..758a1bf02fae 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -633,7 +633,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7742", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -645,11 +645,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 3502b5dcc04f..20f1d98a048d 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -140,6 +140,7 @@ compatible = "renesas,r8a7743-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -583,7 +584,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7743", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -595,11 +596,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index f5d4b8b85b6d..96b2d5a4e8f6 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -140,6 +140,7 @@ compatible = "renesas,r8a7744-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -583,7 +584,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7744", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -595,11 +596,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index f877c51f769c..afc902e532d8 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -270,6 +270,7 @@ rwdt: watchdog@e6020000 { compatible = "renesas,r8a7745-wdt", "renesas,rcar-gen2-wdt"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; reg = <0 0xe6020000 0 0x0c>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; @@ -524,7 +525,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7745", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -536,11 +537,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index b024621c9981..644802285249 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -116,7 +116,7 @@ }; &gpio2 { - interrupt-fixup { + interrupt-fixup-hog { gpio-hog; gpios = <29 GPIO_ACTIVE_HIGH>; line-name = "hdmi-hpd-int"; diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 13ef1e9bf4d5..a5cf663a0118 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -91,6 +91,7 @@ compatible = "renesas,r8a77470-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -356,7 +357,7 @@ status = "disabled"; }; - usbphy0: usb-phy@e6590100 { + usbphy0: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a77470", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -368,7 +369,7 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; @@ -392,7 +393,7 @@ status = "disabled"; }; - usbphy1: usb-phy@e6598100 { + usbphy1: usb-phy-controller@e6598100 { compatible = "renesas,usb-phy-r8a77470", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6598100 0 0x100>; @@ -404,7 +405,7 @@ resets = <&cpg 706>; status = "disabled"; - usb1: usb-channel@0 { + usb1: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 57cd2fa72249..5ad5349a50dc 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -442,7 +442,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts index c802f9f13c18..fe14727eefe1 100644 --- a/arch/arm/boot/dts/r8a7790-stout.dts +++ b/arch/arm/boot/dts/r8a7790-stout.dts @@ -341,7 +341,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index ed6dd4fcc503..db171e3c62f2 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -274,6 +274,7 @@ compatible = "renesas,r8a7790-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -653,7 +654,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -665,11 +666,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 6e691b6cac05..26a40782cc89 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -805,7 +805,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index 38e2ab928707..ec0a20d5130d 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -390,7 +390,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 0ccc162d3c2c..d8f91d9f42ae 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -161,6 +161,7 @@ compatible = "renesas,r8a7791-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -607,7 +608,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7791", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -619,11 +620,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index 62aa9f61321b..c66de9dd12df 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -335,7 +335,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 9cdb73894ac2..a6d9367f8fa0 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -111,6 +111,7 @@ compatible = "renesas,r8a7792-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index c8978f4f62e9..79b537b24642 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -740,7 +740,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index dea4b1e108af..9ebe7bfaf0ed 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -146,6 +146,7 @@ compatible = "renesas,r8a7793-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 99d554fe3329..4d93319674c6 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -463,7 +463,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 92a76164432a..b7af1befa126 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -433,7 +433,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index eac9ed8df0be..7aa781ff3bff 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -128,6 +128,7 @@ compatible = "renesas,r8a7794-wdt", "renesas,rcar-gen2-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -505,7 +506,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7794", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -517,11 +518,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi deleted file mode 100644 index 79fce67ebb1c..000000000000 --- a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for the AA104XD12 panel connected to Renesas R-Car boards - * - * Copyright (C) 2014 Renesas Electronics Corp. - */ - -/ { - panel { - compatible = "mitsubishi,aa104xd12", "panel-lvds"; - - width-mm = <210>; - height-mm = <158>; - data-mapping = "jeida-18"; - - panel-timing { - /* 1024x768 @65Hz */ - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hsync-len = <136>; - hfront-porch = <20>; - hback-porch = <160>; - vfront-porch = <3>; - vback-porch = <29>; - vsync-len = <6>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_connector>; - }; - }; - }; -}; - -&lvds_connector { - remote-endpoint = <&panel_in>; -}; diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts index 4e57ae2688fc..c18bbd7141c4 100644 --- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts @@ -8,6 +8,9 @@ /dts-v1/; +#include <dt-bindings/pinctrl/rzn1-pinctrl.h> +#include <dt-bindings/net/pcs-rzn1-miic.h> + #include "r9a06g032.dtsi" / { @@ -23,6 +26,155 @@ }; }; +&can0 { + pinctrl-0 = <&pins_can0>; + pinctrl-names = "default"; + + /* Assuming CN10/CN11 are wired for CAN1 */ + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&pins_can1>; + pinctrl-names = "default"; + + /* Please only enable can0 or can1, depending on CN10/CN11 */ + /* status = "okay"; */ +}; + +ð_miic { + status = "okay"; + renesas,miic-switch-portin = <MIIC_GMAC2_PORT>; +}; + +&gmac2 { + status = "okay"; + phy-mode = "gmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&mii_conv4 { + renesas,miic-input = <MIIC_SWITCH_PORTB>; + status = "okay"; +}; + +&mii_conv5 { + renesas,miic-input = <MIIC_SWITCH_PORTA>; + status = "okay"; +}; + +&pinctrl{ + pins_can0: pins_can0 { + pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>, /* CAN0_TXD */ + <RZN1_PINMUX(163, RZN1_FUNC_CAN)>; /* CAN0_RXD */ + drive-strength = <6>; + }; + + pins_can1: pins_can1 { + pinmux = <RZN1_PINMUX(109, RZN1_FUNC_CAN)>, /* CAN1_TXD */ + <RZN1_PINMUX(110, RZN1_FUNC_CAN)>; /* CAN1_RXD */ + drive-strength = <6>; + }; + + pins_eth3: pins_eth3 { + pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>; + drive-strength = <6>; + bias-disable; + }; + + pins_eth4: pins_eth4 { + pinmux = <RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>; + drive-strength = <6>; + bias-disable; + }; + + pins_mdio1: pins_mdio1 { + pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>, + <RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>; + }; +}; + +&rtc0 { + status = "okay"; +}; + +&switch { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>; + + dsa,member = <0 0>; + + mdio { + clock-frequency = <2500000>; + + #address-cells = <1>; + #size-cells = <0>; + + switch0phy4: ethernet-phy@4 { + reg = <4>; + micrel,led-mode = <1>; + }; + + switch0phy5: ethernet-phy@5 { + reg = <5>; + micrel,led-mode = <1>; + }; + }; +}; + +&switch_port0 { + label = "lan0"; + phy-mode = "mii"; + phy-handle = <&switch0phy5>; + status = "okay"; +}; + +&switch_port1 { + label = "lan1"; + phy-mode = "mii"; + phy-handle = <&switch0phy4>; + status = "okay"; +}; + +&switch_port4 { + status = "okay"; +}; + &uart0 { status = "okay"; }; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index c47896e4ab58..563024c9a4ae 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -66,15 +66,96 @@ interrupt-parent = <&gic>; ranges; + rtc0: rtc@40006000 { + compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; + reg = <0x40006000 0x1000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "alarm", "timer", "pps"; + clocks = <&sysctrl R9A06G032_HCLK_RTC>; + clock-names = "hclk"; + power-domains = <&sysctrl>; + status = "disabled"; + }; + + wdt0: watchdog@40008000 { + compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; + reg = <0x40008000 0x1000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + status = "disabled"; + }; + + wdt1: watchdog@40009000 { + compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; + reg = <0x40009000 0x1000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + status = "disabled"; + }; + sysctrl: system-controller@4000c000 { compatible = "renesas,r9a06g032-sysctrl"; reg = <0x4000c000 0x1000>; status = "okay"; #clock-cells = <1>; + #power-domain-cells = <0>; clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>, <&ext_rgmii_ref>; clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + #address-cells = <1>; + #size-cells = <1>; + + dmamux: dma-router@a0 { + compatible = "renesas,rzn1-dmamux"; + reg = <0xa0 4>; + #dma-cells = <6>; + dma-requests = <32>; + dma-masters = <&dma0 &dma1>; + }; + }; + + pci_usb: pci@40030000 { + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; + device_type = "pci"; + clocks = <&sysctrl R9A06G032_HCLK_USBH>, + <&sysctrl R9A06G032_HCLK_USBPM>, + <&sysctrl R9A06G032_CLK_PCI_USB>; + clock-names = "hclkh", "hclkpm", "pciclk"; + power-domains = <&sysctrl>; + reg = <0x40030000 0xc00>, + <0x40020000 0x1100>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; + /* Should map all possible DDR as inbound ranges, but + * the IP only supports a 256MB, 512MB, or 1GB window. + * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) + */ + dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; }; uart0: serial@40060000 { @@ -118,6 +199,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -129,6 +212,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -140,6 +225,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -151,6 +238,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -162,6 +251,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -173,6 +264,154 @@ status = "okay"; }; + nand_controller: nand-controller@40102000 { + compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc"; + reg = <0x40102000 0x2000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; + clock-names = "hclk", "eclk"; + power-domains = <&sysctrl>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dma0: dma-controller@40104000 { + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; + reg = <0x40104000 0x1000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_DMA0>; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <1>; + #dma-cells = <3>; + block_size = <0xfff>; + data-width = <8>; + }; + + dma1: dma-controller@40105000 { + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; + reg = <0x40105000 0x1000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_DMA1>; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <1>; + #dma-cells = <3>; + block_size = <0xfff>; + data-width = <8>; + }; + + gmac2: ethernet@44002000 { + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; + reg = <0x44002000 0x2000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; + clock-names = "stmmaceth"; + power-domains = <&sysctrl>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + status = "disabled"; + }; + + eth_miic: eth-miic@44030000 { + compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44030000 0x10000>; + clocks = <&sysctrl R9A06G032_CLK_MII_REF>, + <&sysctrl R9A06G032_CLK_RGMII_REF>, + <&sysctrl R9A06G032_CLK_RMII_REF>, + <&sysctrl R9A06G032_HCLK_SWITCH_RG>; + clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; + power-domains = <&sysctrl>; + status = "disabled"; + + mii_conv1: mii-conv@1 { + reg = <1>; + status = "disabled"; + }; + + mii_conv2: mii-conv@2 { + reg = <2>; + status = "disabled"; + }; + + mii_conv3: mii-conv@3 { + reg = <3>; + status = "disabled"; + }; + + mii_conv4: mii-conv@4 { + reg = <4>; + status = "disabled"; + }; + + mii_conv5: mii-conv@5 { + reg = <5>; + status = "disabled"; + }; + }; + + switch: switch@44050000 { + compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; + reg = <0x44050000 0x10000>; + clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, + <&sysctrl R9A06G032_CLK_SWITCH>; + clock-names = "hclk", "clk"; + power-domains = <&sysctrl>; + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + switch_port0: port@0 { + reg = <0>; + pcs-handle = <&mii_conv5>; + status = "disabled"; + }; + + switch_port1: port@1 { + reg = <1>; + pcs-handle = <&mii_conv4>; + status = "disabled"; + }; + + switch_port2: port@2 { + reg = <2>; + pcs-handle = <&mii_conv3>; + status = "disabled"; + }; + + switch_port3: port@3 { + reg = <3>; + pcs-handle = <&mii_conv2>; + status = "disabled"; + }; + + switch_port4: port@4 { + reg = <4>; + ethernet = <&gmac2>; + label = "cpu"; + phy-mode = "internal"; + status = "disabled"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + gic: interrupt-controller@44101000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupt-controller; @@ -184,11 +423,30 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; + + can0: can@52104000 { + compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000"; + reg = <0x52104000 0x800>; + reg-io-width = <4>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_CAN0>; + power-domains = <&sysctrl>; + status = "disabled"; + }; + + can1: can@52105000 { + compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; + reg = <0x52105000 0x800>; + reg-io-width = <4>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_CAN1>; + power-domains = <&sysctrl>; + status = "disabled"; + }; }; timer { - compatible = "arm,cortex-a7-timer", - "arm,armv7-timer"; + compatible = "arm,armv7-timer"; interrupt-parent = <&gic>; arm,cpu-registers-not-fw-configured; always-on; @@ -198,4 +456,10 @@ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; + + usbphy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts index 2a7e6624efb9..9fd4d9db9f8f 100644 --- a/arch/arm/boot/dts/rk3036-evb.dts +++ b/arch/arm/boot/dts/rk3036-evb.dts @@ -15,16 +15,20 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>; phy = <&phy0>; - phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ phy-reset-duration = <10>; /* millisecond */ - + phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>; status = "okay"; - phy0: ethernet-phy@0 { - reg = <0>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index e817eba8c622..67e1e04139e7 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -80,16 +80,20 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>; phy = <&phy0>; - phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ phy-reset-duration = <10>; /* millisecond */ - + phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>; status = "okay"; - phy0: ethernet-phy@0 { - reg = <0>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index ba2b8891bbb7..78686fc72ce6 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -225,11 +225,9 @@ }; emac: ethernet@10200000 { - compatible = "rockchip,rk3036-emac", "snps,arc-emac"; + compatible = "rockchip,rk3036-emac"; reg = <0x10200000 0x4000>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; rockchip,grf = <&grf>; clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; clock-names = "hclk", "macref", "macclk"; @@ -330,6 +328,8 @@ cru: clock-controller@20000000 { compatible = "rockchip,rk3036-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; @@ -556,7 +556,7 @@ status = "disabled"; }; - pdma: pdma@20078000 { + pdma: dma-controller@20078000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x20078000 0x4000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -614,7 +614,7 @@ #interrupt-cells = <2>; }; - pcfg_pull_default: pcfg_pull_default { + pcfg_pull_default: pcfg-pull-default { bias-pull-pin-default; }; diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 390aa33cd55a..962b4d1291db 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -48,7 +48,7 @@ compatible = "gpio-keys"; autorepeat; - power { + key-power { gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ linux,code = <KEY_POWER>; label = "GPIO Key Power"; @@ -56,7 +56,7 @@ wakeup-source; debounce-interval = <100>; }; - volume-down { + key-volume-down { gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ linux,code = <KEY_VOLUMEDOWN>; label = "GPIO Key Vol-"; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index a66d915aa0f6..8beecd628282 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -150,18 +150,21 @@ #include "tps65910.dtsi" &emac { - status = "okay"; - phy = <&phy0>; phy-supply = <&vcc_rmii>; - pinctrl-names = "default"; pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>; + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>; + }; }; }; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index 667d57a4ff45..cfa318a506eb 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -160,6 +160,24 @@ status = "okay"; }; +&nfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + label = "rk-nand"; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-step-size = <1024>; + nand-ecc-strength = <40>; + nand-is-boot-medium; + rockchip,boot-blks = <8>; + rockchip,boot-ecc-strength = <24>; + }; +}; + &pinctrl { usb-host { host_drv: host-drv { diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 12b2e59aebc4..3eee42137b6d 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -32,7 +32,7 @@ keys: gpio-keys { compatible = "gpio-keys"; - power { + key-power { wakeup-source; gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; @@ -142,15 +142,20 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>; phy = <&phy0>; phy-supply = <&vcc_rmii>; + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>; status = "okay"; - phy0: ethernet-phy@0 { - reg = <0>; - reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index c25b9695db4b..de9915d946f7 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -202,8 +202,9 @@ cru: clock-controller@20000000 { compatible = "rockchip,rk3066a-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; - #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index 85d3fce0142f..9312be362a7a 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -7,6 +7,7 @@ /dts-v1/; #include <dt-bindings/i2c/i2c.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> #include "rk3188.dtsi" / { @@ -36,7 +37,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key &usb_int>; - power { + key-power { gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; @@ -45,7 +46,7 @@ wakeup-source; }; - wake_on_usb: wake-on-usb { + wake_on_usb: key-wake-on-usb { label = "Wake-on-USB"; gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; @@ -485,7 +486,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio3>; - interrupts = <RK_PD2 GPIO_ACTIVE_HIGH>; + interrupts = <RK_PD2 IRQ_TYPE_NONE>; interrupt-names = "host-wake"; brcm,drive-strength = <5>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts index 39c60426c9c9..0a1ae689b162 100644 --- a/arch/arm/boot/dts/rk3188-px3-evb.dts +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -29,7 +29,7 @@ compatible = "gpio-keys"; autorepeat; - power { + key-power { gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; @@ -212,7 +212,7 @@ regulator-name = "wl_18"; }; - lcd_33: SWITCH_REG1 { + lcd_33: SWITCH_REG { regulator-name = "lcd_33"; }; }; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 36c0945f43b2..e7cf18823558 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -24,7 +24,7 @@ compatible = "gpio-keys"; autorepeat; - power { + key-power { gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; @@ -126,18 +126,21 @@ }; &emac { - status = "okay"; - + phy = <&phy0>; + phy-supply = <&vcc_rmii>; pinctrl-names = "default"; pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; + status = "okay"; - phy = <&phy0>; - phy-supply = <&vcc_rmii>; + mdio { + #address-cells = <1>; + #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio3>; - interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>; + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>; + }; }; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index a94321e90014..cdd4a0bd5133 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -195,8 +195,9 @@ cru: clock-controller@20000000 { compatible = "rockchip,rk3188-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; - #clock-cells = <1>; #reset-cells = <1>; }; diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index 797476e8bef1..5c3d08e3eea3 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -107,7 +107,7 @@ regulator-boot-on; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; autorepeat; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 8eed9e3a92e9..ffc16d6b97e1 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -484,6 +484,8 @@ cru: clock-controller@110e0000 { compatible = "rockchip,rk3228-cru"; reg = <0x110e0000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; @@ -501,7 +503,7 @@ <75000000>; }; - pdma: pdma@110f0000 { + pdma: dma-controller@110f0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x110f0000 0x4000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -718,8 +720,8 @@ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; assigned-clocks = <&cru SCLK_HDMI_PHY>; assigned-clock-parents = <&hdmi_phy>; - clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; - clock-names = "isfr", "iahb", "cec"; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "cec"; pinctrl-names = "default"; pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; resets = <&cru SRST_HDMI_P>; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index c4ca73b40d4a..399d6b9c5fd4 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -118,7 +118,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - power { + key-power { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index 9a4a9749c405..a5a0826341e6 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -27,7 +27,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { wakeup-source; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Power"; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 7fb582302b32..052afe5543e2 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -49,7 +49,7 @@ keys: gpio-keys { compatible = "gpio-keys"; - power { + key-power { wakeup-source; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Power"; diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts index 1e33859de484..1a5156951492 100644 --- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts +++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts @@ -20,14 +20,14 @@ pinctrl-names = "default"; pinctrl-0 = <&user_button_pins>; - button@0 { + button-0 { label = "home"; linux,code = <KEY_HOME>; gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; wakeup-source; }; - button@1 { + button-1 { label = "menu"; linux,code = <KEY_MENU>; gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 8c7376d64bc4..fd90f3b8fc32 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -30,7 +30,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - power { + key-power { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index 55467bc30fa6..633e5a032463 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -31,7 +31,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - power { + key-power { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index c4d1d142d8c6..80e0f07c8e87 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -28,7 +28,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Power"; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi index 9c1e38c54eae..09618bb7d872 100644 --- a/arch/arm/boot/dts/rk3288-tinker.dtsi +++ b/arch/arm/boot/dts/rk3288-tinker.dtsi @@ -26,14 +26,12 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - button@0 { + button { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; diff --git a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi index a10d25ac8f7b..f9dde0eef527 100644 --- a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi @@ -13,10 +13,10 @@ <&bt_dev_wake>; compatible = "brcm,bcm43540-bt"; - host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - max-speed = <3000000>; - brcm,bt-pcm-int-params = [01 02 00 01 01]; + host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + brcm,bt-pcm-int-params = [01 02 00 01 01]; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index 05112c25176d..700bb548d6b2 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -32,7 +32,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ap_lid_int_l>; - lid { + switch-lid { label = "Lid"; gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; wakeup-source; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index 82fc6fba9999..dcdcc55c4098 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -21,14 +21,14 @@ pinctrl-names = "default"; pinctrl-0 = <&volum_down_l &volum_up_l>; - volum_down { + key-volum-down { label = "Volum_down"; gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <100>; }; - volum_up { + key-volum-up { label = "Volum_up"; gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts index 4e9fdb0f722d..e2a4e6232eb5 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts @@ -45,7 +45,7 @@ &lid_switch { pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; - power { + key-power { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 54a6838d73f5..e406c8c7c7e5 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -29,7 +29,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key_l>; - power { + key-power { label = "Power"; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index aaaa61875701..487b0e03d4b4 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -862,6 +862,8 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3288-cru"; reg = <0x0 0xff760000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; @@ -971,7 +973,7 @@ status = "disabled"; }; - crypto: cypto-controller@ff8a0000 { + crypto: crypto@ff8a0000 { compatible = "rockchip,rk3288-crypto"; reg = <0x0 0xff8a0000 0x0 0x4000>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; @@ -980,7 +982,6 @@ clock-names = "aclk", "hclk", "sclk", "apb_pclk"; resets = <&cru SRST_CRYPTO>; reset-names = "crypto-rst"; - status = "okay"; }; iep_mmu: iommu@ff900800 { diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 616a828e0c6e..bf285091a9eb 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -186,8 +186,6 @@ compatible = "snps,arc-emac"; reg = <0x10204000 0x3c>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; rockchip,grf = <&grf>; diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts index f62c9f7af79d..2d9994379eb2 100644 --- a/arch/arm/boot/dts/rv1108-elgin-r1.dts +++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts @@ -72,6 +72,7 @@ interrupt-parent = <&gpio0>; interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; rockchip,system-power-controller; + #clock-cells = <0>; vcc1-supply = <&vcc_sys>; vcc2-supply = <&vcc_sys>; @@ -82,7 +83,7 @@ regulators { vdd_core: DCDC_REG1 { - regulator-name= "vdd_core"; + regulator-name = "vdd_core"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -94,7 +95,7 @@ }; vdd_buck2: DCDC_REG2 { - regulator-name= "vdd_buck2"; + regulator-name = "vdd_buck2"; regulator-min-microvolt = <2200000>; regulator-max-microvolt = <2200000>; regulator-always-on; @@ -105,7 +106,7 @@ }; vcc_ddr: DCDC_REG3 { - regulator-name= "vcc_ddr"; + regulator-name = "vcc_ddr"; regulator-always-on; regulator-boot-on; regulator-state-mem { @@ -114,7 +115,7 @@ }; vcc_io: DCDC_REG4 { - regulator-name= "vcc_io"; + regulator-name = "vcc_io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -126,7 +127,7 @@ }; vdd_10: LDO_REG1 { - regulator-name= "vdd_10"; + regulator-name = "vdd_10"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; @@ -137,7 +138,7 @@ }; vcc_18: LDO_REG2 { - regulator-name= "vcc_18"; + regulator-name = "vcc_18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -148,7 +149,7 @@ }; vdd10_pmu: LDO_REG3 { - regulator-name= "vdd10_pmu"; + regulator-name = "vdd10_pmu"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts index fe5fc9bf75c9..ef150f4ee99d 100644 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -85,6 +85,7 @@ interrupt-parent = <&gpio0>; interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; rockchip,system-power-controller; + #clock-cells = <0>; vcc1-supply = <&vcc_sys>; vcc2-supply = <&vcc_sys>; @@ -95,7 +96,7 @@ regulators { vdd_core: DCDC_REG1 { - regulator-name= "vdd_core"; + regulator-name = "vdd_core"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -107,7 +108,7 @@ }; vdd_cam: DCDC_REG2 { - regulator-name= "vdd_cam"; + regulator-name = "vdd_cam"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <2000000>; regulator-state-mem { @@ -116,7 +117,7 @@ }; vcc_ddr: DCDC_REG3 { - regulator-name= "vcc_ddr"; + regulator-name = "vcc_ddr"; regulator-always-on; regulator-boot-on; regulator-state-mem { @@ -125,7 +126,7 @@ }; vcc_io: DCDC_REG4 { - regulator-name= "vcc_io"; + regulator-name = "vcc_io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -137,7 +138,7 @@ }; vdd_10: LDO_REG1 { - regulator-name= "vdd_10"; + regulator-name = "vdd_10"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; @@ -148,7 +149,7 @@ }; vcc_18: LDO_REG2 { - regulator-name= "vcc_18"; + regulator-name = "vcc_18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -159,7 +160,7 @@ }; vdd10_pmu: LDO_REG3 { - regulator-name= "vdd10_pmu"; + regulator-name = "vdd10_pmu"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 448254906452..abf3006f0a84 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -85,24 +85,6 @@ #clock-cells = <0>; }; - amba: bus { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@102a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x102a0000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - bus_intmem: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x2000>; @@ -259,6 +241,17 @@ status = "disabled"; }; + pdma: dma-controller@102a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x102a0000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + grf: syscon@10300000 { compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; reg = <0x10300000 0x1000>; @@ -456,6 +449,8 @@ cru: clock-controller@20200000 { compatible = "rockchip,rv1108-cru"; reg = <0x20200000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; @@ -753,7 +748,7 @@ gmac { rmii_pins: rmii-pins { - rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, + rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, <1 RK_PC3 2 &pcfg_pull_none>, <1 RK_PC4 2 &pcfg_pull_none>, <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>, diff --git a/arch/arm/boot/dts/s3c2410-pinctrl.h b/arch/arm/boot/dts/s3c2410-pinctrl.h new file mode 100644 index 000000000000..76b6171ae149 --- /dev/null +++ b/arch/arm/boot/dts/s3c2410-pinctrl.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung S3C2410 DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ + +#define S3C2410_PIN_FUNC_INPUT 0 +#define S3C2410_PIN_FUNC_OUTPUT 1 +#define S3C2410_PIN_FUNC_2 2 +#define S3C2410_PIN_FUNC_3 3 + +#endif /* __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi index 92439ee5d7de..3268366bd8bc 100644 --- a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi @@ -5,73 +5,73 @@ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> */ -#include <dt-bindings/pinctrl/samsung.h> +#include "s3c2410-pinctrl.h" &pinctrl_0 { /* * Pin banks */ - gpa: gpa { + gpa: gpa-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpc: gpc { + gpc: gpc-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpd: gpd { + gpd: gpd-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpe: gpe { + gpe: gpe-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpf: gpf { + gpf: gpf-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpg: gpg { + gpg: gpg-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gph: gph { + gph: gph-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpj: gpj { + gpj: gpj-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpk: gpk { + gpk: gpk-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpl: gpl { + gpl: gpl-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpm: gpm { + gpm: gpm-gpio-bank { gpio-controller; #gpio-cells = <2>; }; @@ -80,93 +80,93 @@ * Pin groups */ - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gph-0", "gph-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gph-8", "gph-9"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gph-2", "gph-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gph-10", "gph-11"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gph-4", "gph-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - extuart_clk: extuart-clk { + extuart_clk: extuart-clk-pins { samsung,pins = "gph-12"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpe-14", "gpe-15"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpe-11", "gpe-12", "gpe-13"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpe-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpe-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - sd0_bus1: sd0-bus1 { + sd0_bus1: sd0-bus1-pins { samsung,pins = "gpe-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - sd0_bus4: sd0-bus4 { + sd0_bus4: sd0-bus4-pins { samsung,pins = "gpe-8", "gpe-9", "gpe-10"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpl-8"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpl-9"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - sd1_bus1: sd1-bus1 { + sd1_bus1: sd1-bus1-pins { samsung,pins = "gpl-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; - sd1_bus4: sd1-bus4 { + sd1_bus4: sd1-bus4-pins { samsung,pins = "gpl-1", "gpl-2", "gpl-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; }; diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi index 4f084f4fe44f..4660751cb207 100644 --- a/arch/arm/boot/dts/s3c2416.dtsi +++ b/arch/arm/boot/dts/s3c2416.dtsi @@ -45,7 +45,7 @@ status = "disabled"; }; - sdhci_1: sdhci@4ac00000 { + sdhci_1: mmc@4ac00000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x4AC00000 0x100>; interrupts = <0 0 21 3>; @@ -56,7 +56,7 @@ status = "disabled"; }; - sdhci_0: sdhci@4a800000 { + sdhci_0: mmc@4a800000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x4A800000 0x100>; interrupts = <0 0 20 3>; diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index 285555b9ed94..17097da36f5e 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -193,12 +193,12 @@ }; &pinctrl0 { - gpio_leds: gpio-leds { + gpio_leds: gpio-leds-pins { samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - gpio_keys: gpio-keys { + gpio_keys: gpio-keys-pins { samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", "gpn-4", "gpn-5", "gpl-11", "gpl-12"; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi index 8e9594d64b57..f53959b7d031 100644 --- a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi @@ -9,118 +9,118 @@ * listed as device tree nodes in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "s3c64xx-pinctrl.h" &pinctrl0 { /* * Pin banks */ - gpa: gpa { + gpa: gpa-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpc: gpc { + gpc: gpc-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpd: gpd { + gpd: gpd-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpe: gpe { + gpe: gpe-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpf: gpf { + gpf: gpf-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpg: gpg { + gpg: gpg-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gph: gph { + gph: gph-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpi: gpi { + gpi: gpi-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpj: gpj { + gpj: gpj-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpk: gpk { + gpk: gpk-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpl: gpl { + gpl: gpl-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpm: gpm { + gpm: gpm-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpn: gpn { + gpn: gpn-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpo: gpo { + gpo: gpo-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpp: gpp { + gpp: gpp-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpq: gpq { + gpq: gpq-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -131,552 +131,552 @@ * Pin groups */ - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa-0", "gpa-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa-2", "gpa-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa-4", "gpa-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa-6", "gpa-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - ext_dma_0: ext-dma-0 { + ext_dma_0: ext-dma-0-pins { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - ext_dma_1: ext-dma-1 { + ext_dma_1: ext-dma-1-pins { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - irda_data_0: irda-data-0 { + irda_data_0: irda-data-0-pins { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - irda_data_1: irda-data-1 { + irda_data_1: irda-data-1-pins { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - irda_sdbw: irda-sdbw { + irda_sdbw: irda-sdbw-pins { samsung,pins = "gpb-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpb-5", "gpb-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { /* S3C6410-only */ samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_6>; + samsung,pin-function = <S3C64XX_PIN_FUNC_6>; samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpc-0", "gpc-1", "gpc-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; - spi0_cs: spi0-cs { + spi0_cs: spi0-cs-pins { samsung,pins = "gpc-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpc-4", "gpc-5", "gpc-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; - spi1_cs: spi1-cs { + spi1_cs: spi1-cs-pins { samsung,pins = "gpc-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpg-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpg-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd0_bus1: sd0-bus1 { + sd0_bus1: sd0-bus1-pins { samsung,pins = "gpg-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd0_bus4: sd0-bus4 { + sd0_bus4: sd0-bus4-pins { samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpg-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gph-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gph-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd1_bus1: sd1-bus1 { + sd1_bus1: sd1-bus1-pins { samsung,pins = "gph-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd1_bus4: sd1-bus4 { + sd1_bus4: sd1-bus4-pins { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd1_bus8: sd1-bus8 { + sd1_bus8: sd1-bus8-pins { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpg-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpc-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd2_bus1: sd2-bus1 { + sd2_bus1: sd2-bus1-pins { samsung,pins = "gph-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - sd2_bus4: sd2-bus4 { + sd2_bus4: sd2-bus4-pins { samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - i2s0_cdclk: i2s0-cdclk { + i2s0_cdclk: i2s0-cdclk-pins { samsung,pins = "gpd-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - i2s1_cdclk: i2s1-cdclk { + i2s1_cdclk: i2s1-cdclk-pins { samsung,pins = "gpe-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { /* S3C6410-only */ samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", "gph-8", "gph-9"; - samsung,pin-function = <EXYNOS_PIN_FUNC_5>; + samsung,pin-function = <S3C64XX_PIN_FUNC_5>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - i2s2_cdclk: i2s2-cdclk { + i2s2_cdclk: i2s2-cdclk-pins { /* S3C6410-only */ samsung,pins = "gph-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_5>; + samsung,pin-function = <S3C64XX_PIN_FUNC_5>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - pcm0_bus: pcm0-bus { + pcm0_bus: pcm0-bus-pins { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - pcm0_extclk: pcm0-extclk { + pcm0_extclk: pcm0-extclk-pins { samsung,pins = "gpd-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - pcm1_extclk: pcm1-extclk { + pcm1_extclk: pcm1-extclk-pins { samsung,pins = "gpe-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - ac97_bus_0: ac97-bus-0 { + ac97_bus_0: ac97-bus-0-pins { samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - ac97_bus_1: ac97-bus-1 { + ac97_bus_1: ac97-bus-1-pins { samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - cam_port: cam-port { + cam_port: cam-port-pins { samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", "gpf-5", "gpf-6", "gpf-7", "gpf-8", "gpf-9", "gpf-10", "gpf-11", "gpf-12"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - cam_rst: cam-rst { + cam_rst: cam-rst-pins { samsung,pins = "gpf-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - cam_field: cam-field { + cam_field: cam-field-pins { /* S3C6410-only */ samsung,pins = "gpb-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - pwm_extclk: pwm-extclk { + pwm_extclk: pwm-extclk-pins { samsung,pins = "gpf-13"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpf-14"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpf-15"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - clkout0: clkout-0 { + clkout0: clkout-0-pins { samsung,pins = "gpf-14"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col0_0: keypad-col0-0 { + keypad_col0_0: keypad-col0-0-pins { samsung,pins = "gph-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col1_0: keypad-col1-0 { + keypad_col1_0: keypad-col1-0-pins { samsung,pins = "gph-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col2_0: keypad-col2-0 { + keypad_col2_0: keypad-col2-0-pins { samsung,pins = "gph-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col3_0: keypad-col3-0 { + keypad_col3_0: keypad-col3-0-pins { samsung,pins = "gph-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col4_0: keypad-col4-0 { + keypad_col4_0: keypad-col4-0-pins { samsung,pins = "gph-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col5_0: keypad-col5-0 { + keypad_col5_0: keypad-col5-0-pins { samsung,pins = "gph-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col6_0: keypad-col6-0 { + keypad_col6_0: keypad-col6-0-pins { samsung,pins = "gph-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col7_0: keypad-col7-0 { + keypad_col7_0: keypad-col7-0-pins { samsung,pins = "gph-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col0_1: keypad-col0-1 { + keypad_col0_1: keypad-col0-1-pins { samsung,pins = "gpl-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col1_1: keypad-col1-1 { + keypad_col1_1: keypad-col1-1-pins { samsung,pins = "gpl-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col2_1: keypad-col2-1 { + keypad_col2_1: keypad-col2-1-pins { samsung,pins = "gpl-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col3_1: keypad-col3-1 { + keypad_col3_1: keypad-col3-1-pins { samsung,pins = "gpl-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col4_1: keypad-col4-1 { + keypad_col4_1: keypad-col4-1-pins { samsung,pins = "gpl-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col5_1: keypad-col5-1 { + keypad_col5_1: keypad-col5-1-pins { samsung,pins = "gpl-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col6_1: keypad-col6-1 { + keypad_col6_1: keypad-col6-1-pins { samsung,pins = "gpl-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_col7_1: keypad-col7-1 { + keypad_col7_1: keypad-col7-1-pins { samsung,pins = "gpl-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row0_0: keypad-row0-0 { + keypad_row0_0: keypad-row0-0-pins { samsung,pins = "gpk-8"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row1_0: keypad-row1-0 { + keypad_row1_0: keypad-row1-0-pins { samsung,pins = "gpk-9"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row2_0: keypad-row2-0 { + keypad_row2_0: keypad-row2-0-pins { samsung,pins = "gpk-10"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row3_0: keypad-row3-0 { + keypad_row3_0: keypad-row3-0-pins { samsung,pins = "gpk-11"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row4_0: keypad-row4-0 { + keypad_row4_0: keypad-row4-0-pins { samsung,pins = "gpk-12"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row5_0: keypad-row5-0 { + keypad_row5_0: keypad-row5-0-pins { samsung,pins = "gpk-13"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row6_0: keypad-row6-0 { + keypad_row6_0: keypad-row6-0-pins { samsung,pins = "gpk-14"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row7_0: keypad-row7-0 { + keypad_row7_0: keypad-row7-0-pins { samsung,pins = "gpk-15"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row0_1: keypad-row0-1 { + keypad_row0_1: keypad-row0-1-pins { samsung,pins = "gpn-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row1_1: keypad-row1-1 { + keypad_row1_1: keypad-row1-1-pins { samsung,pins = "gpn-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row2_1: keypad-row2-1 { + keypad_row2_1: keypad-row2-1-pins { samsung,pins = "gpn-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row3_1: keypad-row3-1 { + keypad_row3_1: keypad-row3-1-pins { samsung,pins = "gpn-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row4_1: keypad-row4-1 { + keypad_row4_1: keypad-row4-1-pins { samsung,pins = "gpn-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row5_1: keypad-row5-1 { + keypad_row5_1: keypad-row5-1-pins { samsung,pins = "gpn-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row6_1: keypad-row6-1 { + keypad_row6_1: keypad-row6-1-pins { samsung,pins = "gpn-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - keypad_row7_1: keypad-row7-1 { + keypad_row7_1: keypad-row7-1-pins { samsung,pins = "gpn-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - lcd_ctrl: lcd-ctrl { + lcd_ctrl: lcd-ctrl-pins { samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - lcd_data16: lcd-data-width16 { + lcd_data16: lcd-data-width16-pins { samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6", "gpi-7", "gpi-10", "gpi-11", "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - lcd_data18: lcd-data-width18 { + lcd_data18: lcd-data-width18-pins { samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6", "gpi-7", "gpi-10", "gpi-11", "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-2", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - lcd_data24: lcd-data-width24 { + lcd_data24: lcd-data-width24-pins { samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6", "gpi-7", "gpi-8", "gpi-9", "gpi-10", "gpi-11", "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-0", "gpj-1", "gpj-2", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; - hsi_bus: hsi-bus { + hsi_bus: hsi-bus-pins { samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; }; diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.h b/arch/arm/boot/dts/s3c64xx-pinctrl.h new file mode 100644 index 000000000000..645c591db357 --- /dev/null +++ b/arch/arm/boot/dts/s3c64xx-pinctrl.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung S3C64xx DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ + +#define S3C64XX_PIN_PULL_NONE 0 +#define S3C64XX_PIN_PULL_DOWN 1 +#define S3C64XX_PIN_PULL_UP 2 + +#define S3C64XX_PIN_FUNC_INPUT 0 +#define S3C64XX_PIN_FUNC_OUTPUT 1 +#define S3C64XX_PIN_FUNC_2 2 +#define S3C64XX_PIN_FUNC_3 3 +#define S3C64XX_PIN_FUNC_4 4 +#define S3C64XX_PIN_FUNC_5 5 +#define S3C64XX_PIN_FUNC_6 6 +#define S3C64XX_PIN_FUNC_EINT 7 + +#endif /* __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi index cb11a87dbc42..c03df6355500 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -59,7 +59,7 @@ #interrupt-cells = <1>; }; - sdhci0: sdhci@7c200000 { + sdhci0: mmc@7c200000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x7c200000 0x100>; interrupt-parent = <&vic1>; @@ -70,7 +70,7 @@ status = "disabled"; }; - sdhci1: sdhci@7c300000 { + sdhci1: mmc@7c300000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x7c300000 0x100>; interrupt-parent = <&vic1>; @@ -81,7 +81,7 @@ status = "disabled"; }; - sdhci2: sdhci@7c400000 { + sdhci2: mmc@7c400000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x7c400000 0x100>; interrupt-parent = <&vic1>; @@ -178,20 +178,12 @@ interrupt-parent = <&vic1>; interrupts = <21>; - pctrl_int_map: pinctrl-interrupt-map { - interrupt-map = <0 &vic0 0>, - <1 &vic0 1>, - <2 &vic1 0>, - <3 &vic1 1>; - #address-cells = <0>; - #size-cells = <0>; - #interrupt-cells = <1>; - }; - wakeup-interrupt-controller { compatible = "samsung,s3c64xx-wakeup-eint"; - interrupts = <0>, <1>, <2>, <3>; - interrupt-parent = <&pctrl_int_map>; + interrupts-extended = <&vic0 0>, + <&vic0 1>, + <&vic1 0>, + <&vic1 1>; }; }; }; diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index 6423348034b6..0f5c6cd0f3a1 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -29,8 +29,7 @@ memory@30000000 { device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x18000000>; + reg = <0x30000000 0x05000000>, <0x40000000 0x18000000>; }; pmic_ap_clk: clock-0 { @@ -391,9 +390,9 @@ }; &pinctrl0 { - t_flash_detect: t-flash-detect { + t_flash_detect: t-flash-detect-pins { samsung,pins = "gph3-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; }; diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 160f8cd9a68d..964c5fe51755 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -24,9 +24,9 @@ memory@30000000 { device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x10000000 - 0x50000000 0x08000000>; + reg = <0x30000000 0x05000000>, + <0x40000000 0x10000000>, + <0x50000000 0x08000000>; }; reserved-memory { @@ -564,7 +564,6 @@ reset-gpios = <&mp05 5 GPIO_ACTIVE_LOW>; vdd3-supply = <&ldo7_reg>; vci-supply = <&ldo17_reg>; - spi-cs-high; spi-max-frequency = <1200000>; pinctrl-names = "default"; @@ -636,7 +635,7 @@ }; &i2s0 { - dmas = <&pdma0 9>, <&pdma0 10>, <&pdma0 11>; + dmas = <&pdma0 10>, <&pdma0 9>, <&pdma0 11>; status = "okay"; }; @@ -645,185 +644,185 @@ }; &pinctrl0 { - bt_reset: bt-reset { + bt_reset: bt-reset-pins { samsung,pins = "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - wlan_bt_en: wlan-bt-en { + wlan_bt_en: wlan-bt-en-pins { samsung,pins = "gpb-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; samsung,pin-val = <1>; }; - codec_ldo: codec-ldo { + codec_ldo: codec-ldo-pins { samsung,pins = "gpf3-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; prox_i2c_pins: gp2a-i2c-pins { samsung,pins = "gpg0-2", "gpg2-2"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - wlan_gpio_rst: wlan-gpio-rst { + wlan_gpio_rst: wlan-gpio-rst-pins { samsung,pins = "gpg1-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; - bt_wake: bt-wake { + bt_wake: bt-wake-pins { samsung,pins = "gpg3-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; - gp2a_irq: gp2a-irq { + gp2a_irq: gp2a-irq-pins { samsung,pins = "gph0-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; pmic_dvs_pins: pmic-dvs-pins { samsung,pins = "gph0-3", "gph0-4", "gph0-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; samsung,pin-val = <0>; }; - pmic_irq: pmic-irq { + pmic_irq: pmic-irq-pins { samsung,pins = "gph0-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - wifi_host_wake: wifi-host-wake { + wifi_host_wake: wifi-host-wake-pins { samsung,pins = "gph2-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - bt_host_wake: bt-host-wake { + bt_host_wake: bt-host-wake-pins { samsung,pins = "gph2-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - musb_irq: musq-irq { + musb_irq: musq-irq-pins { samsung,pins = "gph2-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - tf_detect: tf-detect { + tf_detect: tf-detect-pins { samsung,pins = "gph3-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - wifi_wake: wifi-wake { + wifi_wake: wifi-wake-pins { samsung,pins = "gph3-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; magnetometer_i2c_pins: yas529-i2c-pins { samsung,pins = "gpj0-0", "gpj0-1"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - ts_irq: ts-irq { + ts_irq: ts-irq-pins { samsung,pins = "gpj0-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - vibrator_ena: vibrator-ena { + vibrator_ena: vibrator-ena-pins { samsung,pins = "gpj1-1"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - gp2a_power: gp2a-power { + gp2a_power: gp2a-power-pins { samsung,pins = "gpj1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; touchkey_i2c_pins: touchkey-i2c-pins { samsung,pins = "gpj3-0", "gpj3-1"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - touchkey_vdd_ena: touchkey-vdd-ena { + touchkey_vdd_ena: touchkey-vdd-ena-pins { samsung,pins = "gpj3-2"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; musb_i2c_pins: musb-i2c-pins { samsung,pins = "gpj3-4", "gpj3-5"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; accel_i2c_pins: accel-i2c-pins { samsung,pins = "gpj3-6", "gpj3-7"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; pmic_i2c_pins: pmic-i2c-pins { samsung,pins = "gpj4-0", "gpj4-3"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - touchkey_irq: touchkey-irq { + touchkey_irq: touchkey-irq-pins { samsung,pins = "gpj4-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; lcd_spi_pins: spi-lcd-pins { samsung,pins = "mp01-1", "mp04-1", "mp04-3"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; fg_i2c_pins: fg-i2c-pins { samsung,pins = "mp05-0", "mp05-1"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; sound_i2c_pins: sound-i2c-pins { samsung,pins = "mp05-2", "mp05-3"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - panel_rst: panel-rst { + panel_rst: panel-rst-pins { samsung,pins = "mp05-5"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; }; @@ -895,7 +894,7 @@ device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>; interrupt-parent = <&gph2>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; + interrupt-names = "host-wakeup"; }; }; diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts index 7427c84f1126..eaa7c4f0e257 100644 --- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -17,20 +17,20 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; gpios = <&gph2 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - vol-down { + key-vol-down { label = "volume_down"; gpios = <&gph3 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; }; - vol-up { + key-vol-up { label = "volume_up"; gpios = <&gph3 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -126,39 +126,39 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep_cfg>; - headset_det: headset-det { + headset_det: headset-det-pins { samsung,pins = "gph0-6", "gph3-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; - fg_irq: fg-irq { + fg_irq: fg-irq-pins { samsung,pins = "gph3-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - headset_micbias_ena: headset-micbias-ena { + headset_micbias_ena: headset-micbias-ena-pins { samsung,pins = "gpj2-5"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - earpath_sel: earpath-sel { + earpath_sel: earpath-sel-pins { samsung,pins = "gpj2-6"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - main_micbias_ena: main-micbias-ena { + main_micbias_ena: main-micbias-ena-pins { samsung,pins = "gpj4-2"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; /* Based on vendor kernel v2.6.35.7 */ - sleep_cfg: sleep-cfg { + sleep_cfg: sleep-state { PIN_SLP(gpa0-0, PREV, NONE); PIN_SLP(gpa0-1, PREV, NONE); PIN_SLP(gpa0-2, PREV, NONE); diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts index eeec2bdece11..532d3f5bceb1 100644 --- a/arch/arm/boot/dts/s5pv210-galaxys.dts +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -24,26 +24,26 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; gpios = <&gph2 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - vol-down { + key-vol-down { label = "volume_down"; gpios = <&gph3 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; }; - vol-up { + key-vol-up { label = "volume_up"; gpios = <&gph3 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; }; - home { + key-home { label = "home"; gpios = <&gph3 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; @@ -152,51 +152,51 @@ fm_i2c_pins: fm-i2c-pins { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - headset_det: headset-det { + headset_det: headset-det-pins { samsung,pins = "gph0-6", "gph3-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; - fm_irq: fm-irq { + fm_irq: fm-irq-pins { samsung,pins = "gpj2-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - fm_rst: fm-rst { + fm_rst: fm-rst-pins { samsung,pins = "gpj2-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - earpath_sel: earpath-sel { + earpath_sel: earpath-sel-pins { samsung,pins = "gpj2-6"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - massmemory_en: massmemory-en { + massmemory_en: massmemory-en-pins { samsung,pins = "gpj2-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - micbias_reg_ena: micbias-reg-ena { + micbias_reg_ena: micbias-reg-ena-pins { samsung,pins = "gpj4-2"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; /* Based on CyanogenMod 3.0.101 kernel */ - sleep_cfg: sleep-cfg { + sleep_cfg: sleep-state { PIN_SLP(gpa0-0, PREV, NONE); PIN_SLP(gpa0-1, PREV, NONE); PIN_SLP(gpa0-2, PREV, NONE); diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index c6f39147cb96..d32f42dd1bf5 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -30,9 +30,9 @@ memory@30000000 { device_type = "memory"; - reg = <0x30000000 0x05000000 - 0x40000000 0x10000000 - 0x50000000 0x08000000>; + reg = <0x30000000 0x05000000>, + <0x40000000 0x10000000>, + <0x50000000 0x08000000>; }; pmic_ap_clk: clock-0 { diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index b8c5172c31dd..6d6daef9fb7a 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -16,17 +16,17 @@ * nodes can be added to this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "s5pv210-pinctrl.h" #define PIN_SLP(_pin, _mode, _pull) \ _pin { \ samsung,pins = #_pin; \ - samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ - samsung,pin-pud-pdn = <S3C64XX_PIN_PULL_ ##_pull>; \ + samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \ + samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \ } &pinctrl0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -34,7 +34,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -42,7 +42,7 @@ #interrupt-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -50,7 +50,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -58,7 +58,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -66,7 +66,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -74,7 +74,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -82,7 +82,7 @@ #interrupt-cells = <2>; }; - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -90,7 +90,7 @@ #interrupt-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -98,7 +98,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -106,7 +106,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -114,7 +114,7 @@ #interrupt-cells = <2>; }; - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -122,7 +122,7 @@ #interrupt-cells = <2>; }; - gpf3: gpf3 { + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -130,7 +130,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -138,7 +138,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -146,7 +146,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -154,7 +154,7 @@ #interrupt-cells = <2>; }; - gpg3: gpg3 { + gpg3: gpg3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -162,7 +162,7 @@ #interrupt-cells = <2>; }; - gpj0: gpj0 { + gpj0: gpj0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -170,7 +170,7 @@ #interrupt-cells = <2>; }; - gpj1: gpj1 { + gpj1: gpj1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -178,7 +178,7 @@ #interrupt-cells = <2>; }; - gpj2: gpj2 { + gpj2: gpj2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -186,7 +186,7 @@ #interrupt-cells = <2>; }; - gpj3: gpj3 { + gpj3: gpj3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -194,7 +194,7 @@ #interrupt-cells = <2>; }; - gpj4: gpj4 { + gpj4: gpj4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -202,47 +202,47 @@ #interrupt-cells = <2>; }; - gpi: gpi { + gpi: gpi-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp01: mp01 { + mp01: mp01-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp02: mp02 { + mp02: mp02-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp03: mp03 { + mp03: mp03-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp04: mp04 { + mp04: mp04-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp05: mp05 { + mp05: mp05-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp06: mp06 { + mp06: mp06-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp07: mp07 { + mp07: mp07-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gph0: gph0 { + gph0: gph0-gpio-bank { gpio-controller; interrupt-controller; interrupt-parent = <&vic0>; @@ -252,7 +252,7 @@ #interrupt-cells = <2>; }; - gph1: gph1 { + gph1: gph1-gpio-bank { gpio-controller; interrupt-controller; interrupt-parent = <&vic0>; @@ -262,7 +262,7 @@ #interrupt-cells = <2>; }; - gph2: gph2 { + gph2: gph2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -270,7 +270,7 @@ #interrupt-cells = <2>; }; - gph3: gph3 { + gph3: gph3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -278,572 +278,572 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - uart_audio: uart-audio { + uart_audio: uart-audio-pins { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_4>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_4>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - ac97_bus: ac97-bus { + ac97_bus: ac97-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_4>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - pcm2_bus: pcm2-bus { + pcm2_bus: pcm2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - spdif_bus: spdif-bus { + spdif_bus: spdif-bus-pins { samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_4>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_5>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_5>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpd1-4", "gpd1-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpd0-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpd0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpd0-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpd0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_row0: keypad-row-0 { + keypad_row0: keypad-row-0-pins { samsung,pins = "gph3-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_row1: keypad-row-1 { + keypad_row1: keypad-row-1-pins { samsung,pins = "gph3-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_row2: keypad-row-2 { + keypad_row2: keypad-row-2-pins { samsung,pins = "gph3-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_row3: keypad-row-3 { + keypad_row3: keypad-row-3-pins { samsung,pins = "gph3-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_row4: keypad-row-4 { + keypad_row4: keypad-row-4-pins { samsung,pins = "gph3-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_row5: keypad-row-5 { + keypad_row5: keypad-row-5-pins { samsung,pins = "gph3-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_row6: keypad-row-6 { + keypad_row6: keypad-row-6-pins { samsung,pins = "gph3-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_row7: keypad-row-7 { + keypad_row7: keypad-row-7-pins { samsung,pins = "gph3-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_col0: keypad-col-0 { + keypad_col0: keypad-col-0-pins { samsung,pins = "gph2-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_col1: keypad-col-1 { + keypad_col1: keypad-col-1-pins { samsung,pins = "gph2-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_col2: keypad-col-2 { + keypad_col2: keypad-col-2-pins { samsung,pins = "gph2-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_col3: keypad-col-3 { + keypad_col3: keypad-col-3-pins { samsung,pins = "gph2-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_col4: keypad-col-4 { + keypad_col4: keypad-col-4-pins { samsung,pins = "gph2-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_col5: keypad-col-5 { + keypad_col5: keypad-col-5-pins { samsung,pins = "gph2-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_col6: keypad-col-6 { + keypad_col6: keypad-col-6-pins { samsung,pins = "gph2-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - keypad_col7: keypad-col-7 { + keypad_col7: keypad-col-7-pins { samsung,pins = "gph2-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpg0-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpg0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpg0-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpg0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpg1-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpg1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpg1-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpg1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpg2-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpg2-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpg2-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpg2-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd2_bus8: sd2-bus-width8 { + sd2_bus8: sd2-bus-width8-pins { samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd3_clk: sd3-clk { + sd3_clk: sd3-clk-pins { samsung,pins = "gpg3-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd3_cmd: sd3-cmd { + sd3_cmd: sd3-cmd-pins { samsung,pins = "gpg3-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd3_cd: sd3-cd { + sd3_cd: sd3-cd-pins { samsung,pins = "gpg3-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd3_bus1: sd3-bus-width1 { + sd3_bus1: sd3-bus-width1-pins { samsung,pins = "gpg3-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - sd3_bus4: sd3-bus-width4 { + sd3_bus4: sd3-bus-width4-pins { samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - eint0: ext-int0 { + eint0: ext-int0-pins { samsung,pins = "gph0-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - eint8: ext-int8 { + eint8: ext-int8-pins { samsung,pins = "gph1-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - eint15: ext-int15 { + eint15: ext-int15-pins { samsung,pins = "gph1-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - eint16: ext-int16 { + eint16: ext-int16-pins { samsung,pins = "gph2-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - eint31: ext-int31 { + eint31: ext-int31-pins { samsung,pins = "gph3-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - cam_port_a_io: cam-port-a-io { + cam_port_a_io: cam-port-a-io-pins { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - cam_port_a_clk_active: cam-port-a-clk-active { + cam_port_a_clk_active: cam-port-a-clk-active-pins { samsung,pins = "gpe1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - cam_port_a_clk_idle: cam-port-a-clk-idle { + cam_port_a_clk_idle: cam-port-a-clk-idle-pins { samsung,pins = "gpe1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - cam_port_b_io: cam-port-b-io { + cam_port_b_io: cam-port-b-io-pins { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - cam_port_b_clk_active: cam-port-b-clk-active { + cam_port_b_clk_active: cam-port-b-clk-active-pins { samsung,pins = "gpj1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; - cam_port_b_clk_idle: cam-port-b-clk-idle { + cam_port_b_clk_idle: cam-port-b-clk-idle-pins { samsung,pins = "gpj1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - lcd_ctrl: lcd-ctrl { + lcd_ctrl: lcd-ctrl-pins { samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - lcd_sync: lcd-sync { + lcd_sync: lcd-sync-pins { samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - lcd_clk: lcd-clk { + lcd_clk: lcd-clk-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - lcd_data24: lcd-data-width24 { + lcd_data24: lcd-data-width24-pins { samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; }; diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.h b/arch/arm/boot/dts/s5pv210-pinctrl.h new file mode 100644 index 000000000000..29bdf376d8f1 --- /dev/null +++ b/arch/arm/boot/dts/s5pv210-pinctrl.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung S5PV210 DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ + +#define S5PV210_PIN_PULL_NONE 0 +#define S5PV210_PIN_PULL_DOWN 1 +#define S5PV210_PIN_PULL_UP 2 + +/* Pin function in power down mode */ +#define S5PV210_PIN_PDN_OUT0 0 +#define S5PV210_PIN_PDN_OUT1 1 +#define S5PV210_PIN_PDN_INPUT 2 +#define S5PV210_PIN_PDN_PREV 3 + +#define S5PV210_PIN_DRV_LV1 0 +#define S5PV210_PIN_DRV_LV2 2 +#define S5PV210_PIN_DRV_LV3 1 +#define S5PV210_PIN_DRV_LV4 3 + +#define S5PV210_PIN_FUNC_INPUT 0 +#define S5PV210_PIN_FUNC_OUTPUT 1 +#define S5PV210_PIN_FUNC_2 2 +#define S5PV210_PIN_FUNC_3 3 +#define S5PV210_PIN_FUNC_4 4 +#define S5PV210_PIN_FUNC_5 5 +#define S5PV210_PIN_FUNC_6 6 +#define S5PV210_PIN_FUNC_EINT 0xf +#define S5PV210_PIN_FUNC_F S5PV210_PIN_FUNC_EINT + +#endif /* __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 353ba7b09a0c..12e90a1cc6a1 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -117,7 +117,7 @@ }; }; - pdma0: dma@e0900000 { + pdma0: dma-controller@e0900000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xe0900000 0x1000>; interrupt-parent = <&vic0>; @@ -125,11 +125,9 @@ clocks = <&clocks CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; - pdma1: dma@e0a00000 { + pdma1: dma-controller@e0a00000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xe0a00000 0x1000>; interrupt-parent = <&vic0>; @@ -137,8 +135,6 @@ clocks = <&clocks CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; adc: adc@e1700000 { @@ -239,8 +235,8 @@ reg = <0xeee30000 0x1000>; interrupt-parent = <&vic2>; interrupts = <16>; - dma-names = "rx", "tx", "tx-sec"; - dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>; + dma-names = "tx", "rx", "tx-sec"; + dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 11>; clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; @@ -259,8 +255,8 @@ reg = <0xe2100000 0x1000>; interrupt-parent = <&vic2>; interrupts = <17>; - dma-names = "rx", "tx"; - dmas = <&pdma1 12>, <&pdma1 13>; + dma-names = "tx", "rx"; + dmas = <&pdma1 13>, <&pdma1 12>; clock-names = "iis", "i2s_opclk0"; clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>; pinctrl-names = "default"; @@ -274,8 +270,8 @@ reg = <0xe2a00000 0x1000>; interrupt-parent = <&vic2>; interrupts = <18>; - dma-names = "rx", "tx"; - dmas = <&pdma1 14>, <&pdma1 15>; + dma-names = "tx", "rx"; + dmas = <&pdma1 15>, <&pdma1 14>; clock-names = "iis", "i2s_opclk0"; clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>; pinctrl-names = "default"; @@ -361,7 +357,7 @@ status = "disabled"; }; - sdhci0: sdhci@eb000000 { + sdhci0: mmc@eb000000 { compatible = "samsung,s3c6410-sdhci"; reg = <0xeb000000 0x100000>; interrupt-parent = <&vic1>; @@ -372,7 +368,7 @@ status = "disabled"; }; - sdhci1: sdhci@eb100000 { + sdhci1: mmc@eb100000 { compatible = "samsung,s3c6410-sdhci"; reg = <0xeb100000 0x100000>; interrupt-parent = <&vic1>; @@ -383,7 +379,7 @@ status = "disabled"; }; - sdhci2: sdhci@eb200000 { + sdhci2: mmc@eb200000 { compatible = "samsung,s3c6410-sdhci"; reg = <0xeb200000 0x100000>; interrupt-parent = <&vic1>; @@ -394,7 +390,7 @@ status = "disabled"; }; - sdhci3: sdhci@eb300000 { + sdhci3: mmc@eb300000 { compatible = "samsung,s3c6410-sdhci"; reg = <0xeb300000 0x100000>; interrupt-parent = <&vic3>; @@ -427,38 +423,28 @@ status = "disabled"; }; - ehci: ehci@ec200000 { + ehci: usb@ec200000 { compatible = "samsung,exynos4210-ehci"; reg = <0xec200000 0x100>; interrupts = <23>; interrupt-parent = <&vic1>; clocks = <&clocks CLK_USB_HOST>; clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; + phys = <&usbphy 1>; + phy-names = "host"; status = "disabled"; - - port@0 { - reg = <0>; - phys = <&usbphy 1>; - }; }; - ohci: ohci@ec300000 { + ohci: usb@ec300000 { compatible = "samsung,exynos4210-ohci"; reg = <0xec300000 0x100>; interrupts = <23>; interrupt-parent = <&vic1>; clocks = <&clocks CLK_USB_HOST>; clock-names = "usbhost"; - #address-cells = <1>; - #size-cells = <0>; + phys = <&usbphy 1>; + phy-names = "host"; status = "disabled"; - - port@0 { - reg = <0>; - phys = <&usbphy 1>; - }; }; mfc: codec@f1700000 { @@ -528,7 +514,7 @@ clock-names = "sclk_fimg2d", "fimg2d"; }; - mdma1: mdma@fa200000 { + mdma1: dma-controller@fa200000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xfa200000 0x1000>; interrupt-parent = <&vic0>; @@ -536,8 +522,6 @@ clocks = <&clocks CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; }; rotator: rotator@fa300000 { diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index ec45ced3cde6..8f5477e307dd 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> #include <dt-bindings/mfd/atmel-flexcom.h> / { @@ -270,7 +271,7 @@ clock-names = "pclk", "gclk"; }; - sha: sha@f002c000 { + sha: crypto@f002c000 { compatible = "atmel,at91sam9g46-sha"; reg = <0xf002c000 0x100>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; @@ -280,7 +281,6 @@ dma-names = "tx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "sha_clk"; - status = "okay"; }; trng: trng@f0030000 { @@ -288,10 +288,9 @@ reg = <0xf0030000 0x100>; interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; - status = "okay"; }; - aes: aes@f0034000 { + aes: crypto@f0034000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xf0034000 0x100>; interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; @@ -304,10 +303,9 @@ dma-names = "tx", "rx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; clock-names = "aes_clk"; - status = "okay"; }; - tdes: tdes@f0038000 { + tdes: crypto@f0038000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xf0038000 0x100>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; @@ -320,7 +318,6 @@ dma-names = "tx", "rx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; clock-names = "tdes_clk"; - status = "okay"; }; classd: classd@f003c000 { @@ -468,7 +465,7 @@ interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; #pwm-cells = <3>; - status="disabled"; + status = "disabled"; }; hlcdc: hlcdc@f8038000 { @@ -587,6 +584,7 @@ dbgu: serial@fffff200 { compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | @@ -671,7 +669,7 @@ clock-names = "td_slck", "md_slck", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "microchip,sam9x60-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k 0>; @@ -688,7 +686,7 @@ status = "disabled"; }; - rtt: rtt@fffffe20 { + rtt: rtc@fffffe20 { compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; reg = <0xfffffe20 0x20>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 09c741e8ecb8..14c35c12a115 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/dma/at91.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> #include <dt-bindings/iio/adc/at91-sama5d2_adc.h> / { @@ -99,6 +100,16 @@ ranges = <0 0x00200000 0x20000>; }; + resistive_touch: resistive-touch { + compatible = "resistive-adc-touch"; + io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, + <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, + <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; + io-channel-names = "x", "y", "pressure"; + touchscreen-min-pressure = <50000>; + status = "disabled"; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -306,7 +317,7 @@ status = "disabled"; }; - sha@f0028000 { + sha: crypto@f0028000 { compatible = "atmel,at91sam9g46-sha"; reg = <0xf0028000 0x100>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; @@ -316,10 +327,9 @@ dma-names = "tx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "sha_clk"; - status = "okay"; }; - aes@f002c000 { + aes: crypto@f002c000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xf002c000 0x100>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; @@ -332,7 +342,6 @@ dma-names = "tx", "rx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "aes_clk"; - status = "okay"; }; spi0: spi@f8000000 { @@ -376,8 +385,6 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ - #address-cells = <1>; - #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; clock-names = "hclk", "pclk"; status = "disabled"; @@ -415,7 +422,7 @@ pmecc: ecc-engine@f8014070 { compatible = "atmel,sama5d2-pmecc"; reg = <0xf8014070 0x490>, - <0xf8014500 0x100>; + <0xf8014500 0x200>; }; }; @@ -435,6 +442,7 @@ uart0: serial@f801c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | @@ -451,6 +459,7 @@ uart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | @@ -467,6 +476,7 @@ uart2: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | @@ -524,6 +534,7 @@ uart5: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; clock-names = "usart"; @@ -594,6 +605,7 @@ uart6: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; clock-names = "usart"; @@ -662,7 +674,7 @@ ranges = <0 0xf8044000 0x1420>; }; - reset_controller: rstc@f8048000 { + reset_controller: reset-controller@f8048000 { compatible = "atmel,sama5d3-rstc"; reg = <0xf8048000 0x10>; clocks = <&clk32k>; @@ -763,6 +775,7 @@ uart3: serial@fc008000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc008000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | @@ -779,6 +792,7 @@ uart4: serial@fc00c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc00c000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(43))>, @@ -804,6 +818,7 @@ uart7: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "usart"; @@ -874,6 +889,7 @@ uart8: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "usart"; @@ -945,6 +961,7 @@ uart9: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "usart"; @@ -1052,16 +1069,6 @@ status = "disabled"; }; - resistive_touch: resistive-touch { - compatible = "resistive-adc-touch"; - io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, - <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, - <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; - io-channel-names = "x", "y", "pressure"; - touchscreen-min-pressure = <50000>; - status = "disabled"; - }; - pioA: pinctrl@fc038000 { compatible = "atmel,sama5d2-pinctrl"; reg = <0xfc038000 0x600>; @@ -1084,7 +1091,7 @@ #gpio-cells = <2>; }; - tdes@fc044000 { + tdes: crypto@fc044000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xfc044000 0x100>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; @@ -1097,7 +1104,6 @@ dma-names = "tx", "rx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; clock-names = "tdes_clk"; - status = "okay"; }; classd: classd@fc048000 { @@ -1127,7 +1133,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; clock-names = "pclk", "gclk"; assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; - assigned-parrents = <&pmc PMC_TYPE_GCK 55>; + assigned-clock-parents = <&pmc PMC_TYPE_GCK 55>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index d1841bffe3c5..bde8e92d60bb 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -194,6 +195,7 @@ usart0: serial@f001c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf001c000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; @@ -208,6 +210,7 @@ usart1: serial@f0020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0020000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; @@ -222,6 +225,7 @@ uart0: serial@f0024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0024000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; @@ -356,6 +360,7 @@ usart2: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; @@ -370,6 +375,7 @@ usart3: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; @@ -381,7 +387,7 @@ status = "disabled"; }; - sha@f8034000 { + sha: crypto@f8034000 { compatible = "atmel,at91sam9g46-sha"; reg = <0xf8034000 0x100>; interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; @@ -391,7 +397,7 @@ clock-names = "sha_clk"; }; - aes@f8038000 { + aes: crypto@f8038000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xf8038000 0x100>; interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; @@ -402,7 +408,7 @@ clock-names = "aes_clk"; }; - tdes@f803c000 { + tdes: crypto@f803c000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xf803c000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; @@ -464,6 +470,7 @@ dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; @@ -1003,7 +1010,7 @@ clock-names = "slow_clk", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi index a3eaba995cf4..44d1173f2ffb 100644 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { aliases { @@ -39,6 +40,7 @@ uart0: serial@f0024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0024000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; @@ -50,6 +52,7 @@ uart1: serial@f8028000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8028000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index a499de8a7a64..3652c9e24124 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -26,7 +26,7 @@ spi0: spi@f0004000 { dmas = <0>, <0>; /* Do not use DMA for spi0 */ - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi index fa9e5e2a745d..5d9e97fecf83 100644 --- a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi @@ -25,7 +25,7 @@ spi0: spi@f0004000 { dmas = <0>, <0>; /* Do not use DMA for spi0 */ - m25p80@0 { + flash@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index f6e3e6f57252..af62157ae214 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/at91.h> #include <dt-bindings/dma/at91.h> +#include <dt-bindings/mfd/at91-usart.h> #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> @@ -278,6 +279,7 @@ uart0: serial@f8004000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8004000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -437,6 +439,7 @@ usart0: serial@f802c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf802c000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -455,6 +458,7 @@ usart1: serial@f8030000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8030000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -490,6 +494,7 @@ uart1: serial@fc004000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc004000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -508,6 +513,7 @@ usart2: serial@fc008000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc008000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -526,6 +532,7 @@ usart3: serial@fc00c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc00c000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -544,6 +551,7 @@ usart4: serial@fc010000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc010000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -673,7 +681,7 @@ status = "disabled"; }; - aes@fc044000 { + aes: crypto@fc044000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xfc044000 0x100>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; @@ -684,10 +692,9 @@ dma-names = "tx", "rx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "aes_clk"; - status = "okay"; }; - tdes@fc04c000 { + tdes: crpyto@fc04c000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xfc04c000 0x100>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; @@ -698,10 +705,9 @@ dma-names = "tx", "rx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "tdes_clk"; - status = "okay"; }; - sha@fc050000 { + sha: crypto@fc050000 { compatible = "atmel,at91sam9g46-sha"; reg = <0xfc050000 0x100>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; @@ -710,7 +716,6 @@ dma-names = "tx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "sha_clk"; - status = "okay"; }; hsmc: smc@fc05c000 { @@ -729,7 +734,7 @@ }; }; - reset_controller: rstc@fc068600 { + reset_controller: reset-controller@fc068600 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfc068600 0x10>; clocks = <&clk32k>; @@ -773,6 +778,7 @@ dbgu: serial@fc069000 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfc069000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index eddcfbf4d223..7bd8ae8e8d38 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -14,6 +14,7 @@ #include <dt-bindings/clock/at91.h> #include <dt-bindings/dma/at91.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/at91-usart.h> / { model = "Microchip SAMA7G5 family SoC"; @@ -30,6 +31,44 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; + clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-90000000 { + opp-hz = /bits/ 64 <90000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + opp-suspend; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1150000 1125000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-1000000002 { + opp-hz = /bits/ 64 <1000000002>; + opp-microvolt = <1250000 1225000 1300000>; + clock-latency-ns = <320000>; }; }; @@ -75,6 +114,45 @@ #size-cells = <1>; ranges; + nfc_sram: sram@600000 { + compatible = "mmio-sram"; + no-memory-wc; + reg = <0x00600000 0x2400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00600000 0x2400>; + }; + + nfc_io: nfc-io@10000000 { + compatible = "atmel,sama5d3-nfc-io", "syscon"; + reg = <0x10000000 0x8000000>; + }; + + ebi: ebi@40000000 { + compatible = "atmel,sama5d3-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + reg = <0x40000000 0x20000000>; + ranges = <0x0 0x0 0x40000000 0x8000000 + 0x1 0x0 0x48000000 0x8000000 + 0x2 0x0 0x50000000 0x8000000 + 0x3 0x0 0x58000000 0x8000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,sama5d3-nand-controller"; + atmel,nfc-sram = <&nfc_sram>; + atmel,nfc-io = <&nfc_io>; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + securam: securam@e0000000 { compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; reg = <0xe0000000 0x4000>; @@ -83,7 +161,6 @@ #size-cells = <1>; ranges = <0 0xe0000000 0x4000>; no-memory-wc; - status = "okay"; }; secumod: secumod@e0004000 { @@ -122,6 +199,13 @@ clock-names = "td_slck", "md_slck", "main_xtal"; }; + reset_controller: reset-controller@e001d000 { + compatible = "microchip,sama7g5-rstc"; + reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + shdwc: shdwc@e001d010 { compatible = "microchip,sama7g5-shdwc", "syscon"; reg = <0xe001d010 0x10>; @@ -133,7 +217,7 @@ status = "disabled"; }; - rtt: rtt@e001d020 { + rtt: rtc@e001d020 { compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; reg = <0xe001d020 0x30>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -181,6 +265,22 @@ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; + hsmc: hsmc@e0808000 { + compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; + reg = <0xe0808000 0x1000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmecc: ecc-engine@e0808070 { + compatible = "atmel,sama5d2-pmecc"; + reg = <0xe0808070 0x490>, + <0xe0808500 0x200>; + }; + }; + qspi0: spi@e080c000 { compatible = "microchip,sama7g5-ospi"; reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; @@ -211,6 +311,102 @@ status = "disabled"; }; + can0: can@e0828000 { + compatible = "bosch,m_can"; + reg = <0xe0828000 0x100>, <0x100000 0x7800>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 61>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can1: can@e082c000 { + compatible = "bosch,m_can"; + reg = <0xe082c000 0x100>, <0x100000 0xbc00>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 62>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can2: can@e0830000 { + compatible = "bosch,m_can"; + reg = <0xe0830000 0x100>, <0x100000 0x10000>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 63>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can3: can@e0834000 { + compatible = "bosch,m_can"; + reg = <0xe0834000 0x100>, <0x110000 0x4400>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 64>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can4: can@e0838000 { + compatible = "bosch,m_can"; + reg = <0xe0838000 0x100>, <0x110000 0x8800>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 65>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can5: can@e083c000 { + compatible = "bosch,m_can"; + reg = <0xe083c000 0x100>, <0x110000 0xcc00>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 66>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; + status = "disabled"; + }; + adc: adc@e1000000 { compatible = "microchip,sama7g5-adc"; reg = <0xe1000000 0x200>; @@ -275,6 +471,30 @@ status = "disabled"; }; + pdmc0: sound@e1608000 { + compatible = "microchip,sama7g5-pdmc"; + reg = <0xe1608000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>; + dma-names = "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + pdmc1: sound@e160c000 { + compatible = "microchip,sama7g5-pdmc"; + reg = <0xe160c000 0x1000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>; + dma-names = "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + spdifrx: spdifrx@e1614000 { #sound-dai-cells = <0>; compatible = "microchip,sama7g5-spdifrx"; @@ -322,6 +542,19 @@ status = "disabled"; }; + eic: interrupt-controller@e1628000 { + compatible = "microchip,sama7g5-eic"; + reg = <0xe1628000 0xec>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "pclk"; + status = "disabled"; + }; + pit64b0: timer@e1800000 { compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; reg = <0xe1800000 0x4000>; @@ -338,6 +571,27 @@ clock-names = "pclk", "gclk"; }; + aes: crypto@e1810000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xe1810000 0x100>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; + clock-names = "aes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + }; + + sha: crypto@e1814000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xe1814000 0x100>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; + clock-names = "sha_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; + dma-names = "tx"; + }; + flx0: flexcom@e1818000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe1818000 0x200>; @@ -350,6 +604,7 @@ uart0: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; clock-names = "usart"; @@ -379,11 +634,9 @@ #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, - <&dma0 AT91_XDMAC_DT_PERID(8)>; - dma-names = "rx", "tx"; - atmel,use-dma-rx; - atmel,use-dma-tx; + dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, + <&dma0 AT91_XDMAC_DT_PERID(7)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -400,6 +653,7 @@ uart3: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "usart"; @@ -420,6 +674,17 @@ status = "disabled"; }; + tdes: crypto@e2014000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xe2014000 0x100>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; + clock-names = "tdes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, + <&dma0 AT91_XDMAC_DT_PERID(53)>; + dma-names = "tx", "rx"; + }; + flx4: flexcom@e2018000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe2018000 0x200>; @@ -432,6 +697,7 @@ uart4: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; clock-names = "usart"; @@ -457,6 +723,7 @@ uart7: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; clock-names = "usart"; @@ -555,11 +822,9 @@ #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>, - <&dma0 AT91_XDMAC_DT_PERID(22)>; - dma-names = "rx", "tx"; - atmel,use-dma-rx; - atmel,use-dma-tx; + dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -581,11 +846,9 @@ #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>, - <&dma0 AT91_XDMAC_DT_PERID(24)>; - dma-names = "rx", "tx"; - atmel,use-dma-rx; - atmel,use-dma-tx; + dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -608,9 +871,9 @@ #address-cells = <1>; #size-cells = <0>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, - <&dma0 AT91_XDMAC_DT_PERID(28)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, + <&dma0 AT91_XDMAC_DT_PERID(27)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -618,13 +881,11 @@ uddrc: uddrc@e3800000 { compatible = "microchip,sama7g5-uddrc"; reg = <0xe3800000 0x4000>; - status = "okay"; }; ddr3phy: ddr3phy@e3804000 { compatible = "microchip,sama7g5-ddr3phy"; reg = <0xe3804000 0x1000>; - status = "okay"; }; gic: interrupt-controller@e8c11000 { @@ -632,7 +893,6 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - interrupt-parent; reg = <0xe8c11000 0x1000>, <0xe8c12000 0x2000>; }; diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts index a61a078ea042..69381819e07b 100644 --- a/arch/arm/boot/dts/sd5203.dts +++ b/arch/arm/boot/dts/sd5203.dts @@ -15,7 +15,7 @@ #size-cells = <1>; chosen { - bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; + bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; }; aliases { diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 7c1d6423d7f8..2459f3cd7dd9 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -46,7 +46,7 @@ <0xff113000 0x1000>; }; - intc: intc@fffed000 { + intc: interrupt-controller@fffed000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -80,8 +80,6 @@ <0 110 4>, <0 111 4>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&l4_main_clk>; clock-names = "apb_pclk"; resets = <&rst DMA_RESET>; @@ -563,6 +561,12 @@ interrupts = <0 175 4>; }; + socfpga_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <0 0 0 0 16 0 0>; + }; + gmac0: ethernet@ff700000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; altr,sysmgr-syscon = <&sysmgr 0x60 0>; @@ -578,6 +582,7 @@ snps,perfect-filter-entries = <128>; tx-fifo-depth = <4096>; rx-fifo-depth = <4096>; + snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -596,6 +601,7 @@ snps,perfect-filter-entries = <128>; tx-fifo-depth = <4096>; rx-fifo-depth = <4096>; + snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 3ba431dfa8c9..4370e3cbbb4b 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -38,7 +38,7 @@ <0xff113000 0x1000>; }; - intc: intc@ffffd000 { + intc: interrupt-controller@ffffd000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -73,8 +73,6 @@ <0 90 IRQ_TYPE_LEVEL_HIGH>, <0 91 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&l4_main_clk>; clock-names = "apb_pclk"; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; @@ -738,6 +736,16 @@ <37 IRQ_TYPE_LEVEL_HIGH>; }; + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; + dma-ecc@ff8c8000 { compatible = "altr,socfpga-dma-ecc"; reg = <0xff8c8000 0x400>; diff --git a/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts new file mode 100644 index 000000000000..422d00cd4c74 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +/dts-v1/; +#include "socfpga_arria10_mercury_aa1.dtsi" + +/ { + model = "Google Chameleon V3"; + compatible = "google,chameleon-v3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + serial0 = &uart0; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; +}; + +&gmac0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + ssm2603: audio-codec@1a { + compatible = "adi,ssm2603"; + reg = <0x1a>; + }; +}; + +&i2c1 { + status = "okay"; + + u80: gpio@21 { + compatible = "nxp,pca9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SOM_AUD_MUTE", + "DP1_OUT_CEC_EN", + "DP2_OUT_CEC_EN", + "DP1_SOM_PS8469_CAD", + "DPD_SOM_PS8469_CAD", + "DP_OUT_PWR_EN", + "STM32_RST_L", + "STM32_BOOT0", + + "FPGA_PROT", + "STM32_FPGA_COMM0", + "TP119", + "TP120", + "TP121", + "TP122", + "TP123", + "TP124"; + }; +}; + +&mmc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi index 2a3364b26361..ad7cd14de6b6 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi @@ -1,18 +1,18 @@ // SPDX-License-Identifier: GPL-2.0 -/dts-v1/; +/* + * Copyright 2022 Google LLC + */ #include "socfpga_arria10.dtsi" / { model = "Enclustra Mercury AA1"; - compatible = "altr,socfpga-arria10", "altr,socfpga"; + compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga"; aliases { ethernet0 = &gmac0; serial1 = &uart1; - i2c0 = &i2c0; - i2c1 = &i2c1; }; memory@0 { @@ -26,24 +26,11 @@ }; }; -&eccmgr { - sdmmca-ecc@ff8c2c00 { - compatible = "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c2c00 0x400>; - altr,ecc-parent = <&mmc>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - &gmac0 { phy-mode = "rgmii"; phy-addr = <0xffffffff>; /* probe for phy addr */ max-frame-size = <3800>; - status = "okay"; phy-handle = <&phy3>; @@ -69,22 +56,13 @@ }; }; -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - &i2c1 { - status = "okay"; + atsha204a: crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; + isl12022: isl12022@6f { - status = "okay"; compatible = "isil,isl12022"; reg = <0x6f>; }; @@ -92,7 +70,6 @@ /* Following mappings are taken from arria10 socdk dts */ &mmc { - status = "okay"; cap-sd-highspeed; broken-cd; bus-width = <4>; @@ -101,12 +78,3 @@ &osc1 { clock-frequency = <33330000>; }; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 7edebe20e859..ec7365444a3b 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -6,7 +6,7 @@ / { model = "Altera SOCFPGA Arria 10"; - compatible = "altr,socfpga-arria10", "altr,socfpga"; + compatible = "altr,socfpga-arria10-socdk", "altr,socfpga-arria10", "altr,socfpga"; aliases { ethernet0 = &gmac0; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts index 2a745522404d..11ccdc6c2dc6 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts @@ -9,7 +9,7 @@ &qspi { status = "okay"; - flash0: n25q00@0 { + flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,mt25qu02g", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index 1b02d46496a8..7f5458d8fccc 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -7,7 +7,7 @@ / { model = "Altera SOCFPGA Arria V SoC Development Kit"; - compatible = "altr,socfpga-arria5", "altr,socfpga"; + compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga"; chosen { bootargs = "earlyprintk"; @@ -50,7 +50,7 @@ }; }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts index f6561766d83f..76262f1e5e03 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts @@ -24,7 +24,7 @@ reg = <0x0 0x20000000>; /* 512MB */ }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts index 67076e1b1c7f..c8f051fb2bf6 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -24,7 +24,7 @@ ethernet0 = &gmac1; }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 51bb436784e2..b2241205c7a9 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -50,7 +50,7 @@ }; }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; @@ -121,7 +121,7 @@ &qspi { status = "okay"; - flash0: n25q00@0 { + flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,mt25qu02g", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index cae9ddd5ed38..3dd99c7c95e0 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -111,7 +111,7 @@ }; }; - regulator_3_3v: vcc3p3-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "VCC3P3"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts index 3f7aa7bf0863..2564671fc1c6 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts @@ -26,7 +26,7 @@ ethernet0 = &gmac1; }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; @@ -113,7 +113,7 @@ &qspi { status = "okay"; - flash0: n25q512a@0 { + flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q512a", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index 25874e1b9c82..f24f17c2f5ee 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -221,7 +221,7 @@ &qspi { status = "okay"; - n25q128@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q128", "jedec,spi-nor"; @@ -238,7 +238,7 @@ cdns,tslch-ns = <4>; }; - n25q00@1 { + flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,mt25qu02g", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts index 4cbadcb41084..05408df38203 100644 --- a/arch/arm/boot/dts/spear1310-evb.dts +++ b/arch/arm/boot/dts/spear1310-evb.dts @@ -170,7 +170,7 @@ smi: flash@ea000000 { status = "okay"; - clock-rate=<50000000>; + clock-rate = <50000000>; flash@e6000000 { #address-cells = <1>; @@ -379,7 +379,7 @@ }; }; - m25p80@1 { + flash@1 { compatible = "st,m25p80"; reg = <1>; spi-max-frequency = <12000000>; diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts index fd194ebeedc9..7700f2afc128 100644 --- a/arch/arm/boot/dts/spear1340-evb.dts +++ b/arch/arm/boot/dts/spear1340-evb.dts @@ -168,7 +168,7 @@ smi: flash@ea000000 { status = "okay"; - clock-rate=<50000000>; + clock-rate = <50000000>; flash@e6000000 { #address-cells = <1>; @@ -439,7 +439,7 @@ cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>, <&gpiopinctrl 85 0>; - m25p80@0 { + flash@0 { compatible = "m25p80"; reg = <0>; spi-max-frequency = <12000000>; diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi index 827e887afbda..818886e11713 100644 --- a/arch/arm/boot/dts/spear1340.dtsi +++ b/arch/arm/boot/dts/spear1340.dtsi @@ -88,7 +88,7 @@ }; pwm: pwm@e0180000 { - compatible ="st,spear13xx-pwm"; + compatible = "st,spear13xx-pwm"; reg = <0xe0180000 0x1000>; #pwm-cells = <2>; status = "disabled"; @@ -134,9 +134,9 @@ reg = <0xb4100000 0x1000>; interrupts = <0 105 0x4>; status = "disabled"; - dmas = <&dwdma0 12 0 1>, - <&dwdma0 13 1 0>; - dma-names = "tx", "rx"; + dmas = <&dwdma0 13 0 1>, + <&dwdma0 12 1 0>; + dma-names = "rx", "tx"; }; thermal@e07008c4 { diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index c87b881b2c8b..913553367687 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -284,9 +284,9 @@ #size-cells = <0>; interrupts = <0 31 0x4>; status = "disabled"; - dmas = <&dwdma0 4 0 0>, - <&dwdma0 5 0 0>; - dma-names = "tx", "rx"; + dmas = <&dwdma0 5 0 0>, + <&dwdma0 4 0 0>; + dma-names = "rx", "tx"; }; rtc@e0580000 { diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts index 2beb30ca2cba..303ef29fb805 100644 --- a/arch/arm/boot/dts/spear300-evb.dts +++ b/arch/arm/boot/dts/spear300-evb.dts @@ -80,7 +80,7 @@ smi: flash@fc000000 { status = "okay"; - clock-rate=<50000000>; + clock-rate = <50000000>; flash@f8000000 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts index 1c41e4a40334..ea0b53036f7b 100644 --- a/arch/arm/boot/dts/spear310-evb.dts +++ b/arch/arm/boot/dts/spear310-evb.dts @@ -94,7 +94,7 @@ smi: flash@fc000000 { status = "okay"; - clock-rate=<50000000>; + clock-rate = <50000000>; flash@f8000000 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts index c322407a0ade..3c026d021c92 100644 --- a/arch/arm/boot/dts/spear320-evb.dts +++ b/arch/arm/boot/dts/spear320-evb.dts @@ -95,7 +95,7 @@ smi: flash@fc000000 { status = "okay"; - clock-rate=<50000000>; + clock-rate = <50000000>; flash@f8000000 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/spear320-hmi.dts index 367ba48aac3e..34503ac9c51c 100644 --- a/arch/arm/boot/dts/spear320-hmi.dts +++ b/arch/arm/boot/dts/spear320-hmi.dts @@ -167,7 +167,7 @@ smi: flash@fc000000 { status = "okay"; - clock-rate=<50000000>; + clock-rate = <50000000>; flash@f8000000 { #address-cells = <1>; @@ -235,7 +235,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x41>; - irq-over-gpio; irq-gpios = <&gpiopinctrl 29 0x4>; id = <0>; blocks = <0x5>; diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi index 47ac4474ed96..b12474446a48 100644 --- a/arch/arm/boot/dts/spear320.dtsi +++ b/arch/arm/boot/dts/spear320.dtsi @@ -78,7 +78,7 @@ }; pwm: pwm@a8000000 { - compatible ="st,spear-pwm"; + compatible = "st,spear-pwm"; reg = <0xa8000000 0x1000>; #pwm-cells = <2>; status = "disabled"; diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi index 2cf19386a525..dd30d08ccb9b 100644 --- a/arch/arm/boot/dts/ste-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-ab8500.dtsi @@ -28,26 +28,28 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; ab8500_clock: clock-controller { compatible = "stericsson,ab8500-clk"; #clock-cells = <1>; }; - ab8500_gpio: ab8500-gpiocontroller { + ab8500_gpio: gpio { compatible = "stericsson,ab8500-gpio"; gpio-controller; #gpio-cells = <2>; }; - ab8500-rtc { + rtc { compatible = "stericsson,ab8500-rtc"; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; - gpadc: ab8500-gpadc { + gpadc: adc { compatible = "stericsson,ab8500-gpadc"; interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, <39 IRQ_TYPE_LEVEL_HIGH>; @@ -120,13 +122,10 @@ }; }; - ab8500_temp { + thermal { compatible = "stericsson,abx500-temp"; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ABX500_TEMP_WARM"; - io-channels = <&gpadc 0x06>, - <&gpadc 0x07>; - io-channel-names = "aux1", "aux2"; }; ab8500_fg { @@ -196,7 +195,7 @@ "CH_WD_EXP", "VBUS_CH_DROP_END"; monitored-battery = <&battery>; - vddadc-supply = <&ab8500_ldo_tvout_reg>; + vddadc-supply = <&ab8500_ldo_tvout_reg>; io-channels = <&gpadc 0x03>, <&gpadc 0x0a>, <&gpadc 0x09>, @@ -208,11 +207,11 @@ }; ab8500_chargalg { - compatible = "stericsson,ab8500-chargalg"; - monitored-battery = <&battery>; + compatible = "stericsson,ab8500-chargalg"; + monitored-battery = <&battery>; }; - ab8500_usb: ab8500_usb { + ab8500_usb: phy { compatible = "stericsson,ab8500-usb"; interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, <96 IRQ_TYPE_LEVEL_HIGH>, @@ -236,7 +235,7 @@ #phy-cells = <0>; }; - ab8500-ponkey { + key { compatible = "stericsson,ab8500-poweron-key"; interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, <7 IRQ_TYPE_LEVEL_HIGH>; @@ -247,29 +246,31 @@ compatible = "stericsson,ab8500-sysctrl"; }; - ab8500-pwm-1 { + pwm@1 { compatible = "stericsson,ab8500-pwm"; + reg = <1>; clocks = <&ab8500_clock AB8500_SYSCLK_INT>; clock-names = "intclk"; + #pwm-cells = <1>; }; - ab8500-pwm-2 { + pwm@2 { compatible = "stericsson,ab8500-pwm"; + reg = <2>; clocks = <&ab8500_clock AB8500_SYSCLK_INT>; clock-names = "intclk"; + #pwm-cells = <1>; }; - ab8500-pwm-3 { + pwm@3 { compatible = "stericsson,ab8500-pwm"; + reg = <3>; clocks = <&ab8500_clock AB8500_SYSCLK_INT>; clock-names = "intclk"; + #pwm-cells = <1>; }; - ab8500-debugfs { - compatible = "stericsson,ab8500-debug"; - }; - - codec: ab8500-codec { + codec: codec { compatible = "stericsson,ab8500-codec"; V-AUD-supply = <&ab8500_ldo_audio_reg>; @@ -283,7 +284,7 @@ stericsson,earpeice-cmv = <950>; /* Units in mV. */ }; - ext_regulators: ab8500-ext-regulators { + ext_regulators: regulator-external { compatible = "stericsson,ab8500-ext-regulator"; ab8500_ext1_reg: ab8500_ext1 { @@ -307,7 +308,7 @@ }; }; - ab8500-regulators { + regulator { compatible = "stericsson,ab8500-regulator"; vin-supply = <&ab8500_ext3_reg>; diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/ste-ab8505.dtsi index e98335e9d1cb..131c82508e82 100644 --- a/arch/arm/boot/dts/ste-ab8505.dtsi +++ b/arch/arm/boot/dts/ste-ab8505.dtsi @@ -25,26 +25,28 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; ab8500_clock: clock-controller { compatible = "stericsson,ab8500-clk"; #clock-cells = <1>; }; - ab8505_gpio: ab8505-gpiocontroller { + ab8505_gpio: gpio { compatible = "stericsson,ab8505-gpio"; gpio-controller; #gpio-cells = <2>; }; - ab8500-rtc { + rtc { compatible = "stericsson,ab8500-rtc"; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; - gpadc: ab8500-gpadc { + gpadc: adc { compatible = "stericsson,ab8500-gpadc"; interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "SW_CONV_END"; @@ -92,8 +94,13 @@ }; }; + thermal { + compatible = "stericsson,abx500-temp"; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ABX500_TEMP_WARM"; + }; + ab8500_fg { - status = "disabled"; compatible = "stericsson,ab8500-fg"; interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, <8 IRQ_TYPE_LEVEL_HIGH>, @@ -111,7 +118,6 @@ }; ab8500_btemp { - status = "disabled"; compatible = "stericsson,ab8500-btemp"; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, <80 IRQ_TYPE_LEVEL_HIGH>, @@ -131,7 +137,6 @@ }; ab8500_charger { - status = "disabled"; compatible = "stericsson,ab8500-charger"; interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, <11 IRQ_TYPE_LEVEL_HIGH>, @@ -170,12 +175,11 @@ }; ab8500_chargalg { - status = "disabled"; compatible = "stericsson,ab8500-chargalg"; monitored-battery = <&battery>; }; - ab8500_usb: ab8500_usb { + ab8500_usb: phy { compatible = "stericsson,ab8500-usb"; interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, <96 IRQ_TYPE_LEVEL_HIGH>, @@ -199,7 +203,7 @@ #phy-cells = <0>; }; - ab8500-ponkey { + key { compatible = "stericsson,ab8500-poweron-key"; interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, <7 IRQ_TYPE_LEVEL_HIGH>; @@ -210,17 +214,15 @@ compatible = "stericsson,ab8500-sysctrl"; }; - ab8500-pwm { + pwm@1 { compatible = "stericsson,ab8500-pwm"; + reg = <1>; clocks = <&ab8500_clock AB8500_SYSCLK_INT>; clock-names = "intclk"; + #pwm-cells = <1>; }; - ab8500-debugfs { - compatible = "stericsson,ab8500-debug"; - }; - - codec: ab8500-codec { + codec: codec { compatible = "stericsson,ab8500-codec"; V-AUD-supply = <&ab8500_ldo_audio_reg>; @@ -233,7 +235,7 @@ stericsson,earpeice-cmv = <950>; /* Units in mV. */ }; - ab8505-regulators { + regulator { compatible = "stericsson,ab8505-regulator"; ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index dc0bcc7020f1..9afe8301bd47 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -661,7 +661,6 @@ #address-cells = <1>; #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; @@ -679,7 +678,6 @@ #address-cells = <1>; #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; @@ -698,7 +696,6 @@ #address-cells = <1>; #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; @@ -717,7 +714,6 @@ #address-cells = <1>; #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; @@ -736,7 +732,6 @@ #address-cells = <1>; #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; @@ -755,7 +750,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ <&dma 8 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -772,7 +767,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ <&dma 9 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -790,7 +785,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ <&dma 0 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -807,7 +802,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ <&dma 35 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -824,7 +819,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ <&dma 33 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; @@ -841,7 +836,7 @@ #size-cells = <0>; /* Same clock wired to kernel and pclk */ clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ <&dma 40 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi index 3ccb7b5c7162..9fa024900d53 100644 --- a/arch/arm/boot/dts/ste-href-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi @@ -9,7 +9,7 @@ soc { prcmu@80157000 { ab8500 { - ab8500-gpiocontroller { + gpio { /* Hog a few default settings */ pinctrl-names = "default"; pinctrl-0 = <&gpio2_default_mode>, diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 718752a0248e..8f1bb78fc1e4 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -16,7 +16,32 @@ battery: battery { compatible = "simple-battery"; battery-type = "lithium-ion-polymer"; - thermistor-on-batctrl; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "murata,ncp18wb473"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; }; soc { @@ -219,16 +244,16 @@ prcmu@80157000 { ab8500 { - ab8500-gpiocontroller { + gpio { }; - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8500-regulators { + regulator { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; }; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index 8f504edefd3f..e66fa59c2de6 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -353,11 +353,11 @@ * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) */ hrefv60_cfg1 { - pins ="GPIO65_F1"; + pins = "GPIO65_F1"; ste,config = <&gpio_out_hi>; }; hrefv60_cfg2 { - pins ="GPIO66_G3"; + pins = "GPIO66_G3"; ste,config = <&gpio_out_lo>; }; }; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index fb719c8a8eb2..e2f0cdacba7d 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -20,7 +20,32 @@ battery: battery { compatible = "simple-battery"; battery-type = "lithium-ion-polymer"; - thermistor-on-batctrl; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "murata,ncp18wb473"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; }; en_3v3_reg: en_3v3 { @@ -384,7 +409,7 @@ prcmu@80157000 { ab8500 { - ab8500-gpiocontroller { + gpio { /* * AB8500 GPIOs are numbered starting from 1, so the first * index 0 is what in the datasheet is called "GPIO1", and @@ -406,13 +431,13 @@ "PM_GPIO42"; /* AB8500 GPIO42 */ }; - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ext_regulators: ab8500-ext-regulators { + ext_regulators: regulator-external { ab8500_ext1_reg: ab8500_ext1 { regulator-name = "ab8500-ext-supply1"; }; @@ -426,7 +451,7 @@ }; }; - ab8500-regulators { + regulator { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; }; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts new file mode 100644 index 000000000000..27a3ab7e25e1 --- /dev/null +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts @@ -0,0 +1,793 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Devicetree for the Samsung Galaxy Exhibit SGH-T599 also known as Codina-TMO, + * the "TMO" shall be read "T-Mobile" as this phone was produced exlusively + * for T-Mobile in the United States. + * + * This phone is closely related to the Codina, but has: + * - No CPU speed cap, full ~1GHz rate + * - Different power management IC, AB8505 + * - As AB8505 has a micro USB phy, no TI TSU6111 + * - Different power routing such as the removal of the external LDO for the + * touchscreen in favor of using the AB8505 + * - Using a regulator for the key backlight LED + * - Using the Samsung S6D27A1 panel by default + * - The panel is using one of the ordinary AB8505 regulators for 1.8V + * - WiFi/Bluetooth combi chip upgraded to BCM4334 + * - GPIO for backlight control moved from 68 to 69 + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-ab8505.dtsi" +#include "ste-dbx5x0-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "Samsung Galaxy Exhibit (SGH-T599)"; + compatible = "samsung,codina-tmo", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + battery: battery { + compatible = "samsung,eb425161lu"; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + + /* TI TXS0206 level translator for 2.9 V */ + sd_level_translator: regulator-gpio { + compatible = "regulator-fixed"; + + /* GPIO87 EN */ + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-name = "sd-level-translator"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + + startup-delay-us = <200>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_level_translator_default>; + }; + + /* External LDO MIC5366-3.3YMT for eMMC */ + ldo_3v3_reg: regulator-gpio-ldo-3v3 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VMEM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_ldo_en_default_mode>; + }; + + /* + * External Ricoh RP152L010B-TR LCD LDO regulator for the display. + * LCD_PWR_EN controls both the 3.0V output. + */ + lcd_3v0_reg: regulator-gpio-lcd-3v0 { + compatible = "regulator-fixed"; + /* Supplied in turn by VBAT */ + regulator-name = "VREG_LCD_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* GPIO219 controls this regulator */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr_en_default_mode>; + }; + + /* + * This regulator is a GPIO line that drives the Broadcom WLAN + * line WL_REG_ON high and enables the internal regulators + * inside the chip. Unfortunatley it is erroneously named + * WLAN_RST_N on the schematic but it is not a reset line. + * + * The voltage specified here is only used to determine the OCR mask, + * the for the SDIO connector, the chip is actually connected + * directly to VBAT. + */ + wl_reg: regulator-gpio-wlan { + compatible = "regulator-fixed"; + regulator-name = "WL_REG_ON"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + startup-delay-us = <100000>; + /* GPIO215 (WLAN_RST_N to WL_REG_ON) */ + gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_ldo_en_default>; + }; + + vibrator { + compatible = "gpio-vibrator"; + /* GPIO195 "MOT_EN" */ + enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_default>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default_mode>; + + button-home { + linux,code = <KEY_HOME>; + label = "HOME"; + /* GPIO91 */ + gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + }; + button-volup { + linux,code = <KEY_VOLUMEUP>; + label = "VOL+"; + /* GPIO67 */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + button-voldown { + linux,code = <KEY_VOLUMEDOWN>; + label = "VOL-"; + /* GPIO92 */ + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + }; + + led-touchkeys { + compatible = "regulator-led"; + vled-supply = <&ab8500_ldo_aux4_reg>; // 3.3V + default-state = "on"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = <LED_COLOR_ID_WHITE>; + }; + + ktd253: backlight { + compatible = "kinetic,ktd253"; + /* GPIO69 is used on Codina R0.4 and Codina TMO */ + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + /* Default to 13/32 brightness */ + default-brightness = <13>; + pinctrl-names = "default"; + pinctrl-0 = <&ktd253_backlight_default_mode>; + }; + + /* Richtek RT8515GQW Flash LED Driver IC */ + flash { + compatible = "richtek,rt8515"; + /* GPIO 140 */ + enf-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + /* GPIO 141 */ + ent-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + /* + * RFS is 16 kOhm and RTS is 100 kOhm giving + * the flash max current 343mA and torch max + * current 55 mA. + */ + richtek,rfs-ohms = <16000>; + richtek,rts-ohms = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_flash_default_mode>; + + led { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + flash-max-timeout-us = <250000>; + flash-max-microamp = <343750>; + led-max-microamp = <55000>; + }; + }; + + /* Bit-banged I2C on GPIO143 and GPIO144 also called "SUBPMU I2C" */ + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + /* TODO: this should also be used by the SM5103 Camera power management unit */ + }; + + /* Bit-banged I2C on GPIO151 and GPIO152 also called "COMP I2C" */ + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + clock-frequency = <400000>; + + avdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + dvdd-supply = <&ab8500_ldo_aux8_reg>; // 1.8V + }; + }; + + spi-gpio-0 { + compatible = "spi-gpio"; + /* Clock on GPIO220, pin SCL */ + sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; + /* MOSI on GPIO224, pin SDI "slave data in" */ + mosi-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + /* MISO on GPIO225, pin SDO "slave data out" */ + miso-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + /* Chip select on GPIO201 */ + cs-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6d27a1"; + spi-max-frequency = <1200000>; + /* TYPE 3: inverse clock polarity and phase */ + spi-cpha; + spi-cpol; + + reg = <0>; + vci-supply = <&lcd_3v0_reg>; + vccio-supply = <&ab8500_ldo_aux6_reg>; + + /* Reset on GPIO139 */ + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + /* LCD_VGH/LCD_DETECT, ESD IRQ on GPIO93 */ + interrupt-parent = <&gpio2>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_mode>; + backlight = <&ktd253>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + + soc { + /* External Micro SD slot */ + mmc@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + st,sig-pin-fbclk; + full-pwr-cycle; + /* MMC is powered by AUX3 1.2V .. 2.91V */ + vmmc-supply = <&ab8500_ldo_aux3_reg>; + /* 2.9 V level translator is using AUX3 at 2.9 V as well */ + vqmmc-supply = <&sd_level_translator>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_2_default>; + pinctrl-1 = <&mc0_a_2_sleep>; + cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217 + status = "okay"; + }; + + /* WLAN SDIO channel */ + mmc@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_2_default>; + pinctrl-1 = <&mc1_a_2_sleep>; + /* + * GPIO-controlled voltage enablement: this drives + * the WL_REG_ON line high when we use this device. + * Represented as regulator to fill OCR mask. + */ + vmmc-supply = <&wl_reg>; + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + /* GPIO216 WL_HOST_WAKE */ + interrupt-parent = <&gpio6>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_mode>; + }; + }; + + /* eMMC */ + mmc@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + non-removable; + cap-mmc-highspeed; + mmc-ddr-1_8v; + no-sdio; + no-sd; + vmmc-supply = <&ldo_3v3_reg>; + pinctrl-names = "default", "sleep"; + /* + * GPIO130 will be set to input no pull-up resulting in a resistor + * pulling the reset high and taking the memory out of reset. + */ + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + status = "okay"; + }; + + /* GBF (Bluetooth) UART */ + uart@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + + bluetooth { + /* BCM4334B0 actually */ + compatible = "brcm,bcm4330-bt"; + /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ + shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + /* BT_WAKE on GPIO199 */ + device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + /* BT_HOST_WAKE on GPIO97 */ + /* FIXME: convert to interrupt */ + host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + /* BT_RST_N on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_mode>; + }; + }; + + /* GPS UART */ + uart@80121000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + /* CTS/RTS is not used, CTS is repurposed as GPIO */ + pinctrl-0 = <&u1rxtx_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep>; + /* FIXME: add a device for the GPS here */ + }; + + /* Debugging console UART connected to AB8505 */ + uart@80007000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + }; + + prcmu@80157000 { + ab8505 { + phy { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + + /* This is mostly identical to the Codina v0.4 regulators */ + regulator { + ab8500_ldo_aux1 { + regulator-name = "v-sensors-vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux2 { + regulator-name = "v-aux2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux3 { + regulator-name = "v-mmc-sd"; + }; + + ab8500_ldo_aux4 { + regulator-name = "v-aux4"; + /* + * Providing some span here makes the touchkey + * LEDs actually dimmable. + */ + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux5 { + regulator-name = "v-aux5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux6 { + /* 1.8 V to the display */ + regulator-name = "v-aux6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux8 { + regulator-name = "v-sensors-vio"; + }; + }; + }; + }; + + /* I2C0 also known as "AGC I2C" */ + i2c@80004000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@39 { + /* Codina has the Amstaos TMD2672 */ + compatible = "amstaos,tmd2672"; + clock-frequency = <400000>; + reg = <0x39>; + + /* IRQ on GPIO146 "PS_INT" */ + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&ab8500_ldo_aux8_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&tmd2672_codina_default>; + }; + }; + + /* I2C2 on GPIO10 and GPIO11 also called "SENSORS I2C" */ + i2c@80128000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + + /* Bosch BMA254 accelerometer */ + accelerometer@18 { + compatible = "bosch,bma254"; + reg = <0x18>; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + vddio-supply = <&ab8500_ldo_aux8_reg>; // 1.8V + vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V + }; + }; + + /* I2C3 */ + i2c@80110000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + + /* TODO: write bindings and driver for this touchscreen */ + + /* Zinitix BT404 ISP part */ + isp@50 { + compatible = "zinitix,bt404-isp"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + + /* Zinitix BT404 touchscreen, also has the touchkeys for menu and back */ + touchscreen@20 { + compatible = "zinitix,bt404"; + reg = <0x20>; + /* GPIO218 (TSP_INT_1V8) */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + vcca-supply = <&ab8500_ldo_aux2_reg>; // 3.3V + vdd-supply = <&ab8500_ldo_aux5_reg>; // 1.8V + zinitix,mode = <2>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_default>; + }; + }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dpi_default_mode>; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&pinctrl { + /* + * This extends the MC0_A_2 default config to include + * the card detect GPIO217 line. + */ + sdi0 { + mc0_a_2_default { + default_cfg4 { + pins = "GPIO217_AH12"; /* card detect */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + sdi2 { + /* + * GPIO130 should be set in GPIO mode and + * pulled down. (Not connected.) + */ + mc2_a_1_default { + default_cfg2 { + pins = "GPIO130_C8"; /* FBCLK */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + /* GPIO that enables the 2.9V SD card level translator */ + sd-level-translator { + sd_level_translator_default: sd_level_translator_default { + /* level shifter on GPIO87 */ + codina_cfg1 { + pins = "GPIO87_B3"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the eMMC */ + emmc-ldo { + emmc_ldo_en_default_mode: emmc_ldo_default { + /* LDO enable on GPIO223 */ + codina_cfg1 { + pins = "GPIO223_AH9"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIOs for panel control */ + panel { + panel_default_mode: panel_default { + codina_cfg1 { + /* Reset line */ + pins = "GPIO139_C9"; + ste,config = <&gpio_out_lo>; + }; + codina_cfg2 { + /* ESD IRQ line "LCD detect" */ + pins = "GPIO93_B7"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the LCD display */ + lcd-ldo { + lcd_pwr_en_default_mode: lcd_pwr_en_default { + /* LCD_PWR_EN on GPIO219 */ + codina_cfg1 { + pins = "GPIO219_AG10"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the WLAN internal LDO regulators */ + wlan-ldo { + wlan_ldo_en_default: wlan_ldo_default { + /* GPIO215 named WLAN_RST_N */ + codina_cfg1 { + pins = "GPIO215_AH13"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Backlight GPIO */ + backlight { + ktd253_backlight_default_mode: backlight_default { + skomer_cfg1 { + pins = "GPIO69_E2"; /* LCD_BL_CTRL */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Flash and torch */ + flash { + gpio_flash_default_mode: flash_default { + codina_cfg1 { + pins = "GPIO140_B11", "GPIO141_C12"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO keys */ + gpio-keys { + gpio_keys_default_mode: gpio_keys_default { + skomer_cfg1 { + pins = "GPIO67_G2", /* VOL UP */ + "GPIO91_B6", /* HOME */ + "GPIO92_D6"; /* VOL DOWN */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + /* Interrupt line for the Zinitix BT404 touchscreen */ + tsp { + tsp_default: tsp_default { + codina_cfg1 { + pins = "GPIO218_AH11"; /* TSP_INT_1V8 */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* Interrupt line for light/proximity sensor TMD2672 */ + tmd2672 { + tmd2672_codina_default: tmd2672_codina { + codina_cfg1 { + pins = "GPIO146_D13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for subpmu */ + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + codina_cfg1 { + pins = "GPIO143_D12", "GPIO144_B13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for the NFC */ + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + codina_cfg1 { + pins = "GPIO151_D17", "GPIO152_D16"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based SPI bus for the display */ + spi-gpio-0 { + spi_gpio_0_default: spi_gpio_0_d { + codina_cfg1 { + pins = "GPIO220_AH10", "GPIO201_AF24", "GPIO224_AG9"; + ste,config = <&gpio_out_hi>; + }; + codina_cfg2 { + pins = "GPIO225_AG8"; + /* Needs pull down, no pull down resistor on board */ + ste,config = <&gpio_in_pd>; + }; + }; + spi_gpio_0_sleep: spi_gpio_0_s { + codina_cfg1 { + pins = "GPIO220_AH10", "GPIO201_AF24", + "GPIO224_AG9", "GPIO225_AG8"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + wlan { + wlan_default_mode: wlan_default { + /* GPIO216 for WL_HOST_WAKE */ + codina_cfg2 { + pins = "GPIO216_AG12"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + bluetooth { + bluetooth_default_mode: bluetooth_default { + /* GPIO199 BT_WAKE and GPIO222 BT_VREG_ON */ + codina_cfg1 { + pins = "GPIO199_AH23", "GPIO222_AJ9"; + ste,config = <&gpio_out_lo>; + }; + /* GPIO97 BT_HOST_WAKE */ + codina_cfg2 { + pins = "GPIO97_D9"; + ste,config = <&gpio_in_nopull>; + }; + /* GPIO209 BT_RST_N */ + codina_cfg3 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + vibrator { + vibrator_default: vibrator_default { + codina_cfg1 { + pins = "GPIO195_AG28"; /* MOT_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + mcde { + dpi_default_mode: dpi_default { + default_mux1 { + /* Mux in all the data lines */ + function = "lcd"; + groups = + /* Data lines D0-D7 GPIO70..GPIO77 */ + "lcd_d0_d7_a_1", + /* Data lines D8-D11 GPIO78..GPIO81 */ + "lcd_d8_d11_a_1", + /* Data lines D12-D15 GPIO82..GPIO85 */ + "lcd_d12_d15_a_1", + /* Data lines D16-D23 GPIO161..GPIO168 */ + "lcd_d16_d23_b_1"; + }; + default_mux2 { + function = "lcda"; + /* Clock line on GPIO150, DE, VSO, HSO on GPIO169..GPIO171 */ + groups = "lcdaclk_b_1", "lcda_b_1"; + }; + /* Input, no pull-up is the default state for pins used for an alt function */ + default_cfg1 { + pins = "GPIO150_C14", "GPIO169_D22", "GPIO170_C23", "GPIO171_D23"; + ste,config = <&in_nopull>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index fbd60065542d..b88f0c07873d 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -9,9 +9,13 @@ * the boot loader. * * The Samsung tree further talks about GT-I8160P and GT-I8160chn (China). - * The GT-I8160 plain is knonw as the "europe" variant. - * The GT-I8160P appears to not use the ST Microelectronics accelerometer. + * The GT-I8160 plain is known as the "europe" variant. + * The GT-I8160P is the CDMA version and it appears to not use the ST + * Microelectronics accelerometer and reportedly has NFC mounted. * The GT-I8160chn appears to be the same as the europe variant. + * + * There is also the Codina-TMO, Samsung SGH-T599, which has its own device + * tree. */ /dts-v1/; @@ -47,6 +51,32 @@ compatible = "samsung,eb425161lu"; }; + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + /* TI TXS0206 level translator for 2.9 V */ sd_level_translator: regulator-gpio { compatible = "regulator-fixed"; @@ -285,7 +315,22 @@ #address-cells = <1>; #size-cells = <0>; - /* TODO: add the NFC chip here */ + nfc@2b { + /* NXP NFC circuit PN544 C1 marked NXP 44501 */ + compatible = "nxp,pn544-i2c"; + /* IF0, IF1 high, gives I2C address 0x2B */ + reg = <0x2b>; + clock-frequency = <400000>; + /* NFC IRQ on GPIO32 */ + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + /* GPIO 31 */ + firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + /* GPIO88 */ + enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pn544_codina_default>; + }; }; spi-gpio-0 { @@ -443,10 +488,20 @@ uart@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; - /* CTS/RTS is not used, CTS is repurposed as GPIO */ - pinctrl-0 = <&u1rxtx_a_1_default>; - pinctrl-1 = <&u1rxtx_a_1_sleep>; - /* FIXME: add a device for the GPS here */ + pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + + gnss { + compatible = "brcm,bcm4751"; + /* GPS_RSTN on GPIO21 */ + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO86 */ + enable-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vddio-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&bcm4751_codina_default>; + }; }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ @@ -459,13 +514,17 @@ prcmu@80157000 { ab8500 { - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8500-regulators { + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ regulator-name = "V-SENSORS-VDD"; @@ -497,10 +556,9 @@ pinctrl-0 = <&i2c0_a_1_default>; pinctrl-1 = <&i2c0_a_1_sleep>; - /* TODO: write bindings and driver for this proximity sensor */ proximity@39 { - /* Codina has the Mouser TMD2672 */ - compatible = "mouser,tmd2672"; + /* Codina has the Amstaos TMD2672 */ + compatible = "amstaos,tmd2672"; clock-frequency = <400000>; reg = <0x39>; @@ -548,8 +606,8 @@ reg = <0x19>; vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V - mount-matrix = "0", "-1", "0", - "1", "0", "0", + mount-matrix = "0", "1", "0", + "-1", "0", "0", "0", "0", "1"; }; }; @@ -829,6 +887,34 @@ }; }; }; + nfc { + pn544_codina_default: pn544_codina { + /* Interrupt line */ + codina_cfg1 { + pins = "GPIO32_V2"; + ste,config = <&gpio_in_nopull>; + }; + /* Enable and firmware GPIOs */ + codina_cfg2 { + pins = "GPIO31_V3", "GPIO88_C4"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + bcm4751 { + bcm4751_codina_default: bcm4751_codina { + /* Reset line, start out asserted */ + codina_cfg1 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_lo>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + codina_cfg2 { + pins = "GPIO86_C6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; vibrator { vibrator_default: vibrator_default { codina_cfg1 { diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts index 1c0e5cfeddac..7231bc745200 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts @@ -24,6 +24,32 @@ compatible = "samsung,eb585157lu"; }; + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + /* TI TXS0206 level translator for 2.9 V */ sd_level_translator: regulator-gpio { compatible = "regulator-fixed"; @@ -432,13 +458,17 @@ prcmu@80157000 { ab8500 { - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8500-regulators { + ab8500_fg { + line-impedance-micro-ohms = <43000>; + }; + + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ regulator-name = "V-SENSORS-VDD"; @@ -505,8 +535,8 @@ accelerometer@18 { compatible = "bosch,bma222e"; reg = <0x18>; - mount-matrix = "0", "1", "0", - "-1", "0", "0", + mount-matrix = "0", "-1", "0", + "1", "0", "0", "0", "0", "1"; vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index fc4c5166d85b..9604695edf53 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -29,6 +29,32 @@ compatible = "samsung,eb-l1m7flu"; }; + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + i2c-gpio-0 { compatible = "i2c-gpio"; sda-gpios = <&gpio2 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -280,13 +306,17 @@ prcmu@80157000 { ab8505 { - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8505-regulators { + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + + regulator { ab8500_ldo_aux1 { regulator-name = "sensor_3v"; regulator-min-microvolt = <3000000>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index 5ddcbc1a855d..69387e8754a9 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -24,6 +24,32 @@ compatible = "samsung,eb535151vu"; }; + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + /* External LDO for eMMC LDO VMEM_3V3 controlled by GPIO6 */ ldo_3v3_reg: regulator-gpio-ldo-3v3 { compatible = "regulator-fixed"; @@ -467,7 +493,26 @@ /* CTS/RTS is not used, CTS is repurposed as GPIO */ pinctrl-0 = <&u1rxtx_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep>; - /* FIXME: add a device for the GPS here */ + + gnss { + /* + * The Low Noise Amplifier (LNA) power and enablement is controlled + * autonomously by the GSD4t. + * Janice has a SiRFstarIV-based GSD4t + * Golden has a SiRFstarV 5t-based CSRG05TA03-ICJE-R. + */ + compatible = "csr,gsd4t"; + /* GPS_RSTN on GPIO21 */ + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO96 */ + sirf,onoff-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&gsd4t_janice_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ @@ -480,13 +525,17 @@ prcmu@80157000 { ab8500 { - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8500-regulators { + ab8500_fg { + line-impedance-micro-ohms = <15000>; + }; + + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ regulator-name = "V-SENSORS-VDD"; @@ -592,9 +641,9 @@ accelerometer@8 { compatible = "bosch,bma222"; reg = <0x08>; - mount-matrix = "0", "1", "0", - "-1", "0", "0", - "0", "0", "-1"; + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V }; @@ -923,4 +972,23 @@ }; }; }; + gsd4t { + gsd4t_janice_default: gsd4t_janice { + /* Reset line, start out asserted */ + janice_cfg1 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_lo>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + janice_cfg2 { + pins = "GPIO96_D8"; + ste,config = <&gpio_out_lo>; + }; + /* Unused power enablement line, used in R0.0 and R0.1 boards */ + janice_cfg3 { + pins = "GPIO86_C6"; + ste,config = <&gpio_in_pd>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts index 9ec3f85b1a18..167846df3104 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts @@ -28,6 +28,32 @@ compatible = "samsung,eb425161la"; }; + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + /* TI TXS0206 level translator for 2.9 V */ sd_level_translator: regulator-gpio { compatible = "regulator-fixed"; @@ -301,13 +327,17 @@ prcmu@80157000 { ab8505 { - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8505-regulators { + ab8500_fg { + line-impedance-micro-ohms = <36000>; + }; + + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ regulator-name = "AUX1"; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index 580ca497f312..93e5f5ed888d 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -24,6 +24,32 @@ compatible = "samsung,eb485159lu"; }; + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + /* TI TXS0206 level translator for 2.9 V */ sd_level_translator: regulator-gpio { compatible = "regulator-fixed"; @@ -185,10 +211,6 @@ cap-sd-highspeed; cap-mmc-highspeed; /* All direction control is used */ - st,sig-dir-cmd; - st,sig-dir-dat0; - st,sig-dir-dat2; - st,sig-dir-dat31; st,sig-pin-fbclk; full-pwr-cycle; vmmc-supply = <&ab8500_ldo_aux3_reg>; @@ -267,12 +289,27 @@ }; }; - /* GPF UART */ + /* GPS UART */ uart@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + + gnss { + /* The CSRG05TA03-ICJE-R is a SirfStarV 5t chip */ + compatible = "csr,csrg05ta03-icje-r"; + /* GPS_RSTN on GPIO209 */ + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO86 */ + sirf,onoff-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&g05ta03_skomer_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; }; /* Debugging console UART connected to AB8505 USB */ @@ -285,13 +322,17 @@ prcmu@80157000 { ab8505 { - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8505-regulators { + ab8500_fg { + line-impedance-micro-ohms = <16000>; + }; + + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ regulator-name = "AUX1"; @@ -635,6 +676,20 @@ }; }; }; + g05ta03 { + g05ta03_skomer_default: g05ta03 { + /* Reset line, start out de-asserted */ + skomer_cfg1 { + pins = "GPIO209_AG15"; + ste,config = <&gpio_out_hi>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + skomer_cfg2 { + pins = "GPIO86_C6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; }; &ab8505_gpio { diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 9cce9541e26b..350bcfcf498b 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -29,7 +29,7 @@ */ clockgen-a9@92b0000 { compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; + reg = <0x92b0000 0x10000>; clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; @@ -37,32 +37,27 @@ clocks = <&clk_sysin>; }; - }; - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; + clk_m_a9: clk-m-a9 { + #clock-cells = <0>; + compatible = "st,stih407-clkgen-a9-mux"; + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -87,14 +82,6 @@ }; }; - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - }; - clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -113,6 +100,13 @@ clocks = <&clk_sysin>; }; + clk_s_c0_quadfs: clk-s-c0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-pll"; + + clocks = <&clk_sysin>; + }; + clk_s_c0_flexgen: clk-s-c0-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-c0"; @@ -142,18 +136,17 @@ }; }; - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs-d0"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; + clk_s_d0_quadfs: clk-s-d0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d0"; + + clocks = <&clk_sysin>; + }; + clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-d0"; @@ -166,18 +159,17 @@ }; }; - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs-d2"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; + clk_s_d2_quadfs: clk-s-d2-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d2"; + + clocks = <&clk_sysin>; + }; + clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-d2"; @@ -192,18 +184,17 @@ }; }; - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs-d3"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d3@9107000 { compatible = "st,clkgen-c32"; reg = <0x9107000 0x1000>; + clk_s_d3_quadfs: clk-s-d3-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d3"; + + clocks = <&clk_sysin>; + }; + clk_s_d3_flexgen: clk-s-d3-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-d3"; diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 21f3347a91d6..5ebb77947fd9 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -115,37 +115,140 @@ status = "okay"; }; - soc { + restart: restart-controller { + compatible = "st,stih407-restart"; + st,syscfg = <&syscfg_sbc_reg>; + status = "okay"; + }; + + powerdown: powerdown-controller { + compatible = "st,stih407-powerdown"; + #reset-cells = <1>; + }; + + softreset: softreset-controller { + compatible = "st,stih407-softreset"; + #reset-cells = <1>; + }; + + picophyreset: picophyreset-controller { + compatible = "st,stih407-picophyreset"; + #reset-cells = <1>; + }; + + irq-syscfg { + compatible = "st,stih407-irq-syscfg"; + st,syscfg = <&syscfg_core>; + st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, + <ST_IRQ_SYSCFG_PMU_1>; + st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, + <ST_IRQ_SYSCFG_DISABLED>; + }; + + usb2_picophy0: phy1 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0x100 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY2_RESET>; + reset-names = "global", "port"; + }; + + miphy28lp_phy: miphy28lp { + compatible = "st,miphy28lp-phy"; + st,syscfg = <&syscfg_core>; #address-cells = <1>; #size-cells = <1>; - interrupt-parent = <&intc>; ranges; - compatible = "simple-bus"; - restart: restart-controller@0 { - compatible = "st,stih407-restart"; - reg = <0 0>; - st,syscfg = <&syscfg_sbc_reg>; - status = "okay"; - }; + phy_port0: port@9b22000 { + reg = <0x9b22000 0xff>, + <0x9b09000 0xff>, + <0x9b04000 0xff>; + reg-names = "sata-up", + "pcie-up", + "pipew"; + + st,syscfg = <0x114 0x818 0xe0 0xec>; + #phy-cells = <1>; - powerdown: powerdown-controller@0 { - compatible = "st,stih407-powerdown"; - reg = <0 0>; - #reset-cells = <1>; + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY0_SOFTRESET>; }; - softreset: softreset-controller@0 { - compatible = "st,stih407-softreset"; - reg = <0 0>; - #reset-cells = <1>; + phy_port1: port@9b2a000 { + reg = <0x9b2a000 0xff>, + <0x9b19000 0xff>, + <0x9b14000 0xff>; + reg-names = "sata-up", + "pcie-up", + "pipew"; + + st,syscfg = <0x118 0x81c 0xe4 0xf0>; + + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY1_SOFTRESET>; }; - picophyreset: picophyreset-controller@0 { - compatible = "st,stih407-picophyreset"; - reg = <0 0>; - #reset-cells = <1>; + phy_port2: port@8f95000 { + reg = <0x8f95000 0xff>, + <0x8f90000 0xff>; + reg-names = "pipew", + "usb3-up"; + + st,syscfg = <0x11c 0x820>; + + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY2_SOFTRESET>; }; + }; + + st231_gp0: st231-gp0 { + compatible = "st,st231-rproc"; + memory-region = <&gp0_reserved>; + resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x22c>; + #mbox-cells = <1>; + mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; + mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; + }; + + st231_delta: st231-delta { + compatible = "st,st231-rproc"; + memory-region = <&delta_reserved>; + resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x224>; + #mbox-cells = <1>; + mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; + mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; + }; + + delta0 { + compatible = "st,st-delta"; + clock-names = "delta", + "delta-st231", + "delta-flash-promip"; + clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, + <&clk_s_c0_flexgen CLK_ST231_DMU>, + <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + compatible = "simple-bus"; syscfg_sbc: sbc-syscfg@9620000 { compatible = "st,stih407-sbc-syscfg", "syscon"; @@ -189,16 +292,6 @@ reg = <0x94b5100 0x1000>; }; - irq-syscfg@0 { - compatible = "st,stih407-irq-syscfg"; - reg = <0 0>; - st,syscfg = <&syscfg_core>; - st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, - <ST_IRQ_SYSCFG_PMU_1>; - st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, - <ST_IRQ_SYSCFG_DISABLED>; - }; - /* Display */ vtg_main: sti-vtg-main@8d02800 { compatible = "st,vtg"; @@ -389,70 +482,6 @@ status = "disabled"; }; - usb2_picophy0: phy1@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0x100 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY2_RESET>; - reset-names = "global", "port"; - }; - - miphy28lp_phy: miphy28lp@0 { - compatible = "st,miphy28lp-phy"; - st,syscfg = <&syscfg_core>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0 0>; - - phy_port0: port@9b22000 { - reg = <0x9b22000 0xff>, - <0x9b09000 0xff>, - <0x9b04000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x114 0x818 0xe0 0xec>; - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY0_SOFTRESET>; - }; - - phy_port1: port@9b2a000 { - reg = <0x9b2a000 0xff>, - <0x9b19000 0xff>, - <0x9b14000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x118 0x81c 0xe4 0xf0>; - - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY1_SOFTRESET>; - }; - - phy_port2: port@8f95000 { - reg = <0x8f95000 0xff>, - <0x8f90000 0xff>; - reg-names = "pipew", - "usb3-up"; - - st,syscfg = <0x11c 0x820>; - - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY2_SOFTRESET>; - }; - }; - spi@9840000 { compatible = "st,comms-ssc4-spi"; reg = <0x9840000 0x110>; @@ -681,78 +710,78 @@ st_dwc3: dwc3@8f94000 { - compatible = "st,stih407-dwc3"; - reg = <0x08f94000 0x1000>, <0x110 0x4>; - reg-names = "reg-glue", "syscfg-reg"; - st,syscfg = <&syscfg_core>; - resets = <&powerdown STIH407_USB3_POWERDOWN>, - <&softreset STIH407_MIPHY2_SOFTRESET>; - reset-names = "powerdown", "softreset"; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; + compatible = "st,stih407-dwc3"; + reg = <0x08f94000 0x1000>, <0x110 0x4>; + reg-names = "reg-glue", "syscfg-reg"; + st,syscfg = <&syscfg_core>; + resets = <&powerdown STIH407_USB3_POWERDOWN>, + <&softreset STIH407_MIPHY2_SOFTRESET>; + reset-names = "powerdown", "softreset"; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; ranges; status = "disabled"; - dwc3: dwc3@9900000 { - compatible = "snps,dwc3"; - reg = <0x09900000 0x100000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - phy-names = "usb2-phy", "usb3-phy"; - phys = <&usb2_picophy0>, - <&phy_port2 PHY_TYPE_USB3>; + dwc3: usb@9900000 { + compatible = "snps,dwc3"; + reg = <0x09900000 0x100000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + phy-names = "usb2-phy", "usb3-phy"; + phys = <&usb2_picophy0>, + <&phy_port2 PHY_TYPE_USB3>; snps,dis_u3_susphy_quirk; }; }; /* COMMS PWM Module */ pwm0: pwm@9810000 { - compatible = "st,sti-pwm"; - #pwm-cells = <2>; - reg = <0x9810000 0x68>; - interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_chan0_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; + compatible = "st,sti-pwm"; + #pwm-cells = <2>; + reg = <0x9810000 0x68>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_chan0_default>; + clock-names = "pwm"; + clocks = <&clk_sysin>; st,pwm-num-chan = <1>; - status = "disabled"; + status = "disabled"; }; /* SBC PWM Module */ pwm1: pwm@9510000 { - compatible = "st,sti-pwm"; - #pwm-cells = <2>; - reg = <0x9510000 0x68>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - &pinctrl_pwm1_chan1_default - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; + compatible = "st,sti-pwm"; + #pwm-cells = <2>; + reg = <0x9510000 0x68>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_chan0_default + &pinctrl_pwm1_chan1_default + &pinctrl_pwm1_chan2_default + &pinctrl_pwm1_chan3_default>; + clock-names = "pwm"; + clocks = <&clk_sysin>; st,pwm-num-chan = <4>; - status = "disabled"; + status = "disabled"; }; rng10: rng@8a89000 { - compatible = "st,rng"; - reg = <0x08a89000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; + compatible = "st,rng"; + reg = <0x08a89000 0x1000>; + clocks = <&clk_sysin>; + status = "okay"; }; rng11: rng@8a8a000 { - compatible = "st,rng"; - reg = <0x08a8a000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; + compatible = "st,rng"; + reg = <0x08a8a000 0x1000>; + clocks = <&clk_sysin>; + status = "okay"; }; ethernet0: dwmac@9630000 { @@ -783,64 +812,36 @@ }; mailbox0: mailbox@8f00000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f00000 0x1000>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - mbox-name = "a9"; - status = "okay"; + compatible = "st,stih407-mailbox"; + reg = <0x8f00000 0x1000>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + mbox-name = "a9"; + status = "okay"; }; mailbox1: mailbox@8f01000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f01000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_gp_1"; - status = "okay"; + compatible = "st,stih407-mailbox"; + reg = <0x8f01000 0x1000>; + #mbox-cells = <2>; + mbox-name = "st231_gp_1"; + status = "okay"; }; mailbox2: mailbox@8f02000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f02000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_gp_0"; - status = "okay"; + compatible = "st,stih407-mailbox"; + reg = <0x8f02000 0x1000>; + #mbox-cells = <2>; + mbox-name = "st231_gp_0"; + status = "okay"; }; mailbox3: mailbox@8f03000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f03000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_audio_video"; - status = "okay"; - }; - - st231_gp0: st231-gp0@0 { - compatible = "st,st231-rproc"; - reg = <0 0>; - memory-region = <&gp0_reserved>; - resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x22c>; - #mbox-cells = <1>; - mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; - mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; - }; - - st231_delta: st231-delta@0 { - compatible = "st,st231-rproc"; - reg = <0 0>; - memory-region = <&delta_reserved>; - resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x224>; - #mbox-cells = <1>; - mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; - mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; + compatible = "st,stih407-mailbox"; + reg = <0x8f03000 0x1000>; + #mbox-cells = <2>; + mbox-name = "st231_audio_video"; + status = "okay"; }; /* fdma audio */ @@ -912,7 +913,7 @@ dmas = <&fdma0 2 0 1>; dma-names = "tx"; - status = "disabled"; + status = "disabled"; }; sti_uni_player1: sti-uni-player@8d81000 { @@ -986,16 +987,5 @@ status = "disabled"; }; - - delta0@0 { - compatible = "st,st-delta"; - reg = <0 0>; - clock-names = "delta", - "delta-st231", - "delta-flash-promip"; - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; }; }; diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index 9e212b0af89d..aca43d2bdaad 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -13,7 +13,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0 0>; - assigned-clocks = <&clk_s_d2_quadfs 0>, + assigned-clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, <&clk_s_c0_pll1 0>, <&clk_s_c0_flexgen CLK_COMPO_DVP>, @@ -106,7 +106,7 @@ reg-names = "hdmi-reg"; #sound-dai-cells = <0>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irq"; + interrupt-names = "irq"; clock-names = "pix", "tmds", "phy", diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts index 9d3b118f5f0f..538ff98ca1b1 100644 --- a/arch/arm/boot/dts/stih410-b2120.dts +++ b/arch/arm/boot/dts/stih410-b2120.dts @@ -24,6 +24,14 @@ ethernet0 = ðernet0; }; + usb2_picophy1: phy2 { + status = "okay"; + }; + + usb2_picophy2: phy3 { + status = "okay"; + }; + soc { mmc0: sdhci@9060000 { @@ -33,14 +41,6 @@ sd-uhs-ddr50; }; - usb2_picophy1: phy2@0 { - status = "okay"; - }; - - usb2_picophy2: phy3@0 { - status = "okay"; - }; - ohci0: usb@9a03c00 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts index 9d579c16c295..26d93f26f6d0 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -75,6 +75,21 @@ }; }; + miphy28lp_phy: miphy28lp { + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + + usb2_picophy1: phy2 { + status = "okay"; + }; + + usb2_picophy2: phy3 { + status = "okay"; + }; + soc { /* Low speed expansion connector */ uart0: serial@9830000 { @@ -145,14 +160,6 @@ status = "okay"; }; - usb2_picophy1: phy2@0 { - status = "okay"; - }; - - usb2_picophy2: phy3@0 { - status = "okay"; - }; - ohci0: usb@9a03c00 { status = "okay"; }; @@ -196,13 +203,6 @@ status = "okay"; }; - miphy28lp_phy: miphy28lp@0 { - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - sata1: sata@9b28000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index 6b0e6d4477a3..abac98a1810b 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -32,7 +32,7 @@ */ clockgen-a9@92b0000 { compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; + reg = <0x92b0000 0x10000>; clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; @@ -40,29 +40,29 @@ clocks = <&clk_sysin>; }; - }; - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; /* - * ARM Peripheral clock for timers + * ARM CPU related clocks. */ - arm_periph_clk: clk-m-a9-periphs { + clk_m_a9: clk-m-a9 { #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -87,14 +87,6 @@ }; }; - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - }; - clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -113,6 +105,13 @@ clocks = <&clk_sysin>; }; + clk_s_c0_quadfs: clk-s-c0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-pll"; + + clocks = <&clk_sysin>; + }; + clk_s_c0_flexgen: clk-s-c0-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih410-c0"; @@ -142,18 +141,17 @@ }; }; - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs-d0"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; + clk_s_d0_quadfs: clk-s-d0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d0"; + + clocks = <&clk_sysin>; + }; + clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih410-d0"; @@ -166,18 +164,17 @@ }; }; - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs-d2"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; + clk_s_d2_quadfs: clk-s-d2-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d2"; + + clocks = <&clk_sysin>; + }; + clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-d2"; @@ -192,18 +189,17 @@ }; }; - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs-d3"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d3@9107000 { compatible = "st,clkgen-c32"; reg = <0x9107000 0x1000>; + clk_s_d3_quadfs: clk-s-d3-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d3"; + + clocks = <&clk_sysin>; + }; + clk_s_d3_flexgen: clk-s-d3-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-d3"; diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index 6d847019c554..a39dd5f7bcae 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -12,31 +12,29 @@ bdisp0 = &bdisp0; }; - soc { - usb2_picophy1: phy2@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xf8 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names = "global", "port"; - - status = "disabled"; - }; + usb2_picophy1: phy2 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0xf8 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY0_RESET>; + reset-names = "global", "port"; + + status = "disabled"; + }; - usb2_picophy2: phy3@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xfc 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names = "global", "port"; + usb2_picophy2: phy3 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0xfc 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY1_RESET>; + reset-names = "global", "port"; - status = "disabled"; - }; + status = "disabled"; + }; + soc { ohci0: usb@9a03c00 { compatible = "st,st-ohci-300x"; reg = <0x9a03c00 0x100>; @@ -107,7 +105,7 @@ #size-cells = <1>; reg = <0 0>; - assigned-clocks = <&clk_s_d2_quadfs 0>, + assigned-clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, <&clk_s_c0_pll1 0>, <&clk_s_c0_flexgen CLK_COMPO_DVP>, @@ -200,7 +198,7 @@ reg-names = "hdmi-reg"; #sound-dai-cells = <0>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irq"; + interrupt-names = "irq"; clock-names = "pix", "tmds", "phy", @@ -274,16 +272,6 @@ interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; }; - delta0@0 { - compatible = "st,st-delta"; - clock-names = "delta", - "delta-st231", - "delta-flash-promip"; - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; - sti-cec@94a087c { compatible = "st,stih-cec"; reg = <0x94a087c 0x64>; diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts index b66e2b29edea..d21bcc7c1271 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -37,6 +37,17 @@ }; }; + miphy28lp_phy: miphy28lp { + + phy_port0: port@9b22000 { + st,osc-rdy; + }; + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + soc { sbc_serial0: serial@9530000 { status = "okay"; @@ -84,17 +95,6 @@ non-removable; }; - miphy28lp_phy: miphy28lp@0 { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - st_dwc3: dwc3@8f94000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index e84c476b83ed..e1749e92a2e7 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -32,7 +32,7 @@ */ clockgen-a9@92b0000 { compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; + reg = <0x92b0000 0x10000>; clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; @@ -40,30 +40,29 @@ clocks = <&clk_sysin>; }; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; /* - * ARM Peripheral clock for timers + * ARM CPU related clocks. */ - arm_periph_clk: clk-m-a9-periphs { + clk_m_a9: clk-m-a9 { #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -88,14 +87,6 @@ }; }; - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - }; - clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -114,6 +105,13 @@ clocks = <&clk_sysin>; }; + clk_s_c0_quadfs: clk-s-c0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-pll"; + + clocks = <&clk_sysin>; + }; + clk_s_c0_flexgen: clk-s-c0-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih418-c0"; @@ -143,18 +141,17 @@ }; }; - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs-d0"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; + clk_s_d0_quadfs: clk-s-d0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d0"; + + clocks = <&clk_sysin>; + }; + clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih410-d0"; @@ -167,18 +164,17 @@ }; }; - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs-d2"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; + clk_s_d2_quadfs: clk-s-d2-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d2"; + + clocks = <&clk_sysin>; + }; + clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih418-d2"; @@ -193,18 +189,17 @@ }; }; - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs-d3"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d3@9107000 { compatible = "st,clkgen-c32"; reg = <0x9107000 0x1000>; + clk_s_d3_quadfs: clk-s-d3-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d3"; + + clocks = <&clk_sysin>; + }; + clk_s_d3_flexgen: clk-s-d3-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-d3"; diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi index 97eda4392fbe..b35b9b7a7ccc 100644 --- a/arch/arm/boot/dts/stih418.dtsi +++ b/arch/arm/boot/dts/stih418.dtsi @@ -26,31 +26,29 @@ }; }; + usb2_picophy1: phy2 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0xf8 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY0_RESET>; + reset-names = "global", "port"; + }; + + usb2_picophy2: phy3 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0xfc 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY1_RESET>; + reset-names = "global", "port"; + }; + soc { rng11: rng@8a8a000 { status = "disabled"; }; - usb2_picophy1: phy2@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xf8 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names = "global", "port"; - }; - - usb2_picophy2: phy3@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xfc 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names = "global", "port"; - }; - ohci0: usb@9a03c00 { compatible = "st,st-ohci-300x"; reg = <0x9a03c00 0x100>; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index d051f080e52e..2aa94605d3d4 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -71,6 +71,17 @@ }; }; + miphy28lp_phy: miphy28lp { + + phy_port0: port@9b22000 { + st,osc-rdy; + }; + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + soc { sbc_serial0: serial@9530000 { status = "okay"; @@ -128,17 +139,6 @@ st,i2c-min-sda-pulse-width-us = <5>; }; - miphy28lp_phy: miphy28lp@0 { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - st_dwc3: dwc3@8f94000 { status = "okay"; }; @@ -175,11 +175,11 @@ /* tsin0 is TSA on NIMA */ tsin0: port { - tsin-num = <0>; + tsin-num = <0>; serial-not-parallel; - i2c-bus = <&ssc2>; - reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>; - dvb-card = <STV0367_TDA18212_NIMA_1>; + i2c-bus = <&ssc2>; + reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>; + dvb-card = <STV0367_TDA18212_NIMA_1>; }; }; diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index cb46326a8c75..3de0e9dbe030 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -251,10 +251,10 @@ &mac { status = "okay"; - pinctrl-0 = <ðernet_mii>; - pinctrl-names = "default"; - phy-mode = "mii"; - phy-handle = <&phy1>; + pinctrl-0 = <ðernet_mii>; + pinctrl-names = "default"; + phy-mode = "mii"; + phy-handle = <&phy1>; mdio0 { #address-cells = <1>; #size-cells = <0>; @@ -308,6 +308,18 @@ }; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index 327613fd9666..a293e65141c6 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -194,6 +194,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 155d9ffacc83..500bcc302d42 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -45,7 +45,7 @@ / { soc { - pinctrl: pin-controller@40020000 { + pinctrl: pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 6435e099c632..3b81228d46a2 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -205,6 +205,18 @@ }; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 8748d5850298..c31ceb821231 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -93,14 +93,6 @@ }; }; - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; - status = "disabled"; - }; - timers2: timers@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -123,14 +115,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -153,14 +137,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -183,13 +159,6 @@ }; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; - }; - timers5: timers@40000c00 { #address-cells = <1>; #size-cells = <0>; @@ -212,14 +181,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -236,14 +197,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; @@ -759,6 +712,16 @@ status = "disabled"; }; + dma2d: dma2d@4002b000 { + compatible = "st,stm32-dma2d"; + reg = <0x4002b000 0xc00>; + interrupts = <90>; + resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>; + clock-names = "dma2d"; + status = "disabled"; + }; + usbotg_hs: usb@40040000 { compatible = "snps,dwc2"; reg = <0x40040000 0x40000>; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 30905ce672a0..5a0daf8e8b11 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -132,6 +132,10 @@ clock-frequency = <8000000>; }; +&dma2d { + status = "okay"; +}; + &dsi { #address-cells = <1>; #size-cells = <0>; @@ -224,6 +228,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart3 { pinctrl-0 = <&usart3_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi index 1cf8a23c2644..8f37aefa7315 100644 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -9,7 +9,7 @@ / { soc { - pinctrl: pin-controller@40020000 { + pinctrl: pinctrl@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts index 569d23cc61e5..c11616ed5fc6 100644 --- a/arch/arm/boot/dts/stm32f746-disco.dts +++ b/arch/arm/boot/dts/stm32f746-disco.dts @@ -109,6 +109,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_b>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 014b416f57e6..dc868e6da40e 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -75,14 +75,6 @@ }; soc { - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; - status = "disabled"; - }; - timers2: timers@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -105,14 +97,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -135,14 +119,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -165,13 +141,6 @@ }; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; - }; - timers5: timers@40000c00 { #address-cells = <1>; #size-cells = <0>; @@ -194,14 +163,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -218,14 +179,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts index be943b701980..b038d0ed39e8 100644 --- a/arch/arm/boot/dts/stm32f769-disco.dts +++ b/arch/arm/boot/dts/stm32f769-disco.dts @@ -137,6 +137,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 6e42ca2dada2..2059593da21d 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -375,7 +375,7 @@ arm,primecell-periphid = <0x10153180>; reg = <0x52007000 0x1000>; interrupts = <49>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; @@ -389,7 +389,7 @@ arm,primecell-periphid = <0x10153180>; reg = <0x48022400 0x400>; interrupts = <124>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; @@ -583,7 +583,7 @@ status = "disabled"; }; - pinctrl: pin-controller@58020000 { + pinctrl: pinctrl@58020000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32h743-pinctrl"; diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts index 59e01ce10318..2b452883a708 100644 --- a/arch/arm/boot/dts/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/stm32h743i-disco.dts @@ -77,10 +77,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts index 38cc7faf6884..5c5d8059bdc7 100644 --- a/arch/arm/boot/dts/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/stm32h743i-eval.dts @@ -115,10 +115,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts index 9bb73bb61901..f3e70d3b65ac 100644 --- a/arch/arm/boot/dts/stm32h750i-art-pi.dts +++ b/arch/arm/boot/dts/stm32h750i-art-pi.dts @@ -126,10 +126,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index 069f95f2b628..efdd163eba30 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -6,8 +6,42 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + i2c1_pins_a: i2c1-0 { + pins { + pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_sleep_pins_a: i2c1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */ + }; + }; + + i2c5_pins_a: i2c5-0 { + pins { + pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ + <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_a: i2c5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ + <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins1 { + pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ @@ -17,12 +51,6 @@ drive-push-pull; bias-disable; }; - pins2 { - pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; }; sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { @@ -36,16 +64,104 @@ bias-disable; }; pins2 { + pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_clk_pins_a: sdmmc1-clk-0 { + pins { pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ - slew-rate = <2>; + slew-rate = <1>; drive-push-pull; bias-disable; }; - pins3 { - pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */ + <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ slew-rate = <1>; drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ + <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ + <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ + }; + }; + + sdmmc2_clk_pins_a: sdmmc2-clk-0 { + pins { + pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + spi5_pins_a: spi5-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */ + <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */ bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */ + bias-disable; + }; + }; + + spi5_sleep_pins_a: spi5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */ + <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */ + <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */ }; }; diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 86126dc0d898..dd35a607073d 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -4,6 +4,8 @@ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/stm32mp13-clks.h> +#include <dt-bindings/reset/stm32mp13-resets.h> / { #address-cells = <1>; @@ -27,53 +29,28 @@ interrupt-parent = <&intc>; }; - clocks { - clk_axi: clk-axi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <266500000>; + firmware { + optee { + method = "smc"; + compatible = "linaro,optee-tz"; }; - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clk_hsi: clk-hsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_pclk3: clk-pclk3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104438965>; - }; - - clk_pclk4: clk-pclk4 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <133250000>; - }; + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + shmem = <&scmi_shm>; - clk_pll4_p: clk-pll4_p { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; - clk_pll4_r: clk-pll4_r { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <99000000>; + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; }; }; @@ -92,10 +69,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; interrupt-parent = <&intc>; always-on; }; @@ -107,42 +84,319 @@ interrupt-parent = <&intc>; ranges; + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + }; + + spi2: spi@4000b000 { + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi3: spi@4000c000 { + compatible = "st,stm32h7-spi"; + reg = <0x4000c000 0x400>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_hsi>; + clocks = <&rcc UART4_K>; + resets = <&rcc UART4_R>; + status = "disabled"; + }; + + i2c1: i2c@40012000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x40012000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C1_K>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 33 0x400 0x1>, + <&dmamux1 34 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x1>; + i2c-analog-filter; status = "disabled"; }; + i2c2: i2c@40013000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x40013000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C2_K>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 35 0x400 0x1>, + <&dmamux1 36 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x2>; + i2c-analog-filter; + status = "disabled"; + }; + + spi1: spi@44004000 { + compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + dma1: dma-controller@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc DMA1>; + resets = <&rcc DMA1_R>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dma2: dma-controller@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc DMA2>; + resets = <&rcc DMA2_R>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; + reg = <0x48002000 0x40>; + clocks = <&rcc DMAMUX1>; + resets = <&rcc DMAMUX1_R>; + #dma-cells = <3>; + dma-masters = <&dma1 &dma2>; + dma-requests = <128>; + dma-channels = <16>; + }; + + spi4: spi@4c002000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c002000 0x400>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi5: spi@4c003000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c003000 0x400>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 85 0x400 0x01>, + <&dmamux1 86 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c3: i2c@4c004000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c004000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x1>, + <&dmamux1 74 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c4: i2c@4c005000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c005000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 75 0x400 0x1>, + <&dmamux1 76 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c5: i2c@4c006000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c006000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x1>, + <&dmamux1 116 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; + status = "disabled"; + }; + + rcc: rcc@50000000 { + compatible = "st,stm32mp13-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; + }; + + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp13-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + }; + syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; - clocks = <&clk_pclk3>; + clocks = <&rcc SYSCFG>; + }; + + mdma: dma-controller@58000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x58000000 0x1000>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc MDMA>; + #dma-cells = <5>; + dma-channels = <32>; + dma-requests = <48>; }; sdmmc1: mmc@58005000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; reg = <0x58005000 0x1000>, <0x58006000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cmd_irq"; - clocks = <&clk_pll4_p>; + clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <120000000>; + max-frequency = <130000000>; + status = "disabled"; + }; + + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; status = "disabled"; }; iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; - clocks = <&clk_pclk4>, <&clk_lsi>; + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; clock-names = "pclk", "lsi"; status = "disabled"; }; + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk CK_SCMI_RTCAPB>, + <&scmi_clk CK_SCMI_RTC>; + clock-names = "pclk", "rtc_ck"; + status = "disabled"; + }; + bsec: efuse@5c005000 { compatible = "st,stm32mp15-bsec"; reg = <0x5c005000 0x400>; @@ -164,11 +418,13 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp135-pinctrl"; ranges = <0 0x50002000 0x8400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; pins-are-numbered; gpioa: gpio@50002000 { @@ -177,7 +433,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOA>; st,bank-name = "GPIOA"; ngpios = <16>; gpio-ranges = <&pinctrl 0 0 16>; @@ -189,7 +445,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOB>; st,bank-name = "GPIOB"; ngpios = <16>; gpio-ranges = <&pinctrl 0 16 16>; @@ -201,7 +457,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOC>; st,bank-name = "GPIOC"; ngpios = <16>; gpio-ranges = <&pinctrl 0 32 16>; @@ -213,7 +469,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOD>; st,bank-name = "GPIOD"; ngpios = <16>; gpio-ranges = <&pinctrl 0 48 16>; @@ -225,7 +481,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOE>; st,bank-name = "GPIOE"; ngpios = <16>; gpio-ranges = <&pinctrl 0 64 16>; @@ -237,7 +493,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOF>; st,bank-name = "GPIOF"; ngpios = <16>; gpio-ranges = <&pinctrl 0 80 16>; @@ -249,7 +505,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x6000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOG>; st,bank-name = "GPIOG"; ngpios = <16>; gpio-ranges = <&pinctrl 0 96 16>; @@ -261,7 +517,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x7000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOH>; st,bank-name = "GPIOH"; ngpios = <15>; gpio-ranges = <&pinctrl 0 112 15>; @@ -273,7 +529,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x8000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOI>; st,bank-name = "GPIOI"; ngpios = <8>; gpio-ranges = <&pinctrl 0 128 8>; diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi index 0fb1386257cf..531c263c9f46 100644 --- a/arch/arm/boot/dts/stm32mp133.dtsi +++ b/arch/arm/boot/dts/stm32mp133.dtsi @@ -15,7 +15,7 @@ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; - clocks = <&clk_hse>, <&clk_pll4_r>; + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; status = "disabled"; @@ -28,7 +28,7 @@ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; - clocks = <&clk_hse>, <&clk_pll4_r>; + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index 7e96d9e36217..de341d17e87d 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -6,6 +6,9 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include "stm32mp135.dtsi" #include "stm32mp13xf.dtsi" #include "stm32mp13-pinctrl.dtsi" @@ -23,6 +26,39 @@ reg = <0xc0000000 0x20000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@dd000000 { + reg = <0xdd000000 0x3000000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pa13 { + label = "User-PA13"; + linux,code = <BTN_1>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; @@ -32,15 +68,46 @@ }; }; +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <1000000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <170>; + i2c-scl-falling-time-ns = <5>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; }; +&rtc { + status = "okay"; +}; + &sdmmc1 { - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; broken-cd; disable-wp; st,neg-edge; @@ -49,6 +116,13 @@ status = "okay"; }; +&spi5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_pins_a>; + pinctrl-1 = <&spi5_sleep_pins_a>; + status = "disabled"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi index fa6889e30591..4d00e7592882 100644 --- a/arch/arm/boot/dts/stm32mp13xc.dtsi +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi @@ -10,7 +10,8 @@ compatible = "st,stm32mp1-cryp"; reg = <0x54002000 0x400>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_axi>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi index fa6889e30591..4d00e7592882 100644 --- a/arch/arm/boot/dts/stm32mp13xf.dtsi +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi @@ -10,7 +10,8 @@ compatible = "st,stm32mp1-cryp"; reg = <0x54002000 0x400>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_axi>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 3b65130affec..a9d2bec99014 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -151,6 +151,43 @@ }; }; + dcmi_pins_c: dcmi-2 { + pins { + pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ + <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ + <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ + <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ + <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ + <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ + <STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */ + bias-pull-up; + }; + }; + + dcmi_sleep_pins_c: dcmi-sleep-2 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ + <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ + <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ + <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ + <STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ + <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ + <STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ @@ -338,6 +375,81 @@ }; }; + ethernet0_rmii_pins_b: rmii-1 { + pins1 { + pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */ + <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */ + <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */ + <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */ + bias-disable; + }; + pins4 { + pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */ + }; + }; + + ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ + <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */ + <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */ + <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */ + }; + }; + + ethernet0_rmii_pins_c: rmii-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ @@ -848,6 +960,36 @@ }; }; + mco1_pins_a: mco1-0 { + pins { + pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + mco1_sleep_pins_a: mco1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */ + }; + }; + + mco2_pins_a: mco2-0 { + pins { + pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + mco2_sleep_pins_a: mco2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ @@ -888,6 +1030,26 @@ }; }; + m_can1_pins_c: m-can1-2 { + pins1 { + pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_c: m_can1-sleep-2 { + pins { + pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ + <STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */ + }; + }; + m_can2_pins_a: m-can2-0 { pins1 { pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ @@ -927,6 +1089,21 @@ }; }; + pwm1_pins_b: pwm1-1 { + pins { + pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_b: pwm1-sleep-1 { + pins { + pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */ + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ @@ -1084,7 +1261,7 @@ }; qspi_bk1_pins_a: qspi-bk1-0 { - pins1 { + pins { pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ @@ -1093,12 +1270,6 @@ drive-push-pull; slew-rate = <1>; }; - pins2 { - pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; }; qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { @@ -1106,13 +1277,12 @@ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ - <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ - <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ + <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */ }; }; qspi_bk2_pins_a: qspi-bk2-0 { - pins1 { + pins { pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ @@ -1121,7 +1291,34 @@ drive-push-pull; slew-rate = <1>; }; - pins2 { + }; + + qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ + <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ + <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ + <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */ + }; + }; + + qspi_cs1_pins_a: qspi-cs1-0 { + pins { + pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ + }; + }; + + qspi_cs2_pins_a: qspi-cs2-0 { + pins { pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ bias-pull-up; drive-push-pull; @@ -1129,13 +1326,9 @@ }; }; - qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 { pins { - pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ - <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ - <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ - <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */ - <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ + pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ }; }; @@ -1190,7 +1383,7 @@ }; }; - sai2a_sleep_pins_c: sai2a-2 { + sai2a_sleep_pins_c: sai2a-sleep-2 { pins { pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */ <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */ @@ -1689,15 +1882,30 @@ spi2_pins_a: spi2-0 { pins1 { - pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */ - <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */ + pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ + <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ + bias-disable; + }; + }; + + spi2_pins_b: spi2-1 { + pins1 { + pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */ + <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { - pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */ + pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ bias-disable; }; }; @@ -1779,6 +1987,49 @@ }; }; + uart4_pins_d: uart4-3 { + pins1 { + pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_idle_pins_d: uart4-idle-3 { + pins1 { + pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_d: uart4-sleep-3 { + pins { + pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ + }; + }; + + uart5_pins_a: uart5-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 5, AF12)>; /* UART5_RX */ + bias-disable; + }; + }; + uart7_pins_a: uart7-0 { pins1 { pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ @@ -2042,6 +2293,83 @@ }; }; + usart3_pins_d: usart3-3 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */ + <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usart3_idle_pins_d: usart3-idle-3 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_d: usart3-sleep-3 { + pins { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ + <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */ + }; + }; + + usart3_pins_e: usart3-4 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */ + <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ + bias-pull-up; + }; + }; + + usart3_idle_pins_e: usart3-idle-4 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */ + bias-pull-up; + }; + }; + + usart3_sleep_pins_e: usart3-sleep-4 { + pins { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ + <STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */ + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ @@ -2120,4 +2448,19 @@ bias-disable; }; }; + + spi1_pins_b: spi1-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ + <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */ + bias-disable; + }; + }; }; diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-scmi.dtsi new file mode 100644 index 000000000000..543f24c2f4f6 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15-scmi.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + shmem = <&scmi_shm>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_reguls: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_reg11: reg11@0 { + reg = <0>; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + scmi_reg18: reg18@1 { + voltd-name = "reg18"; + reg = <1>; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + scmi_usb33: usb33@2 { + reg = <2>; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + }; + }; + + soc { + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + }; + }; +}; + +®11 { + status = "disabled"; +}; + +®18 { + status = "disabled"; +}; + +&usb33 { + status = "disabled"; +}; + +&usbotg_hs { + usb33d-supply = <&scmi_usb33>; +}; + +&usbphyc { + vdda1v1-supply = <&scmi_reg11>; + vdda1v8-supply = <&scmi_reg18>; +}; + +/delete-node/ &clk_hse; +/delete-node/ &clk_hsi; +/delete-node/ &clk_lse; +/delete-node/ &clk_lsi; +/delete-node/ &clk_csi; diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 1cfc2f011e70..e02b3f5d44cb 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -45,10 +45,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; interrupt-parent = <&intc>; }; @@ -127,6 +127,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40000000 0x400>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM2_K>; clock-names = "int"; dmas = <&dmamux1 18 0x400 0x1>, @@ -160,6 +162,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001000 0x400>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM3_K>; clock-names = "int"; dmas = <&dmamux1 23 0x400 0x1>, @@ -194,6 +198,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM4_K>; clock-names = "int"; dmas = <&dmamux1 29 0x400 0x1>, @@ -226,6 +232,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40003000 0x400>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM5_K>; clock-names = "int"; dmas = <&dmamux1 55 0x400 0x1>, @@ -260,6 +268,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40004000 0x400>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM6_K>; clock-names = "int"; dmas = <&dmamux1 69 0x400 0x1>; @@ -278,6 +288,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40005000 0x400>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM7_K>; clock-names = "int"; dmas = <&dmamux1 70 0x400 0x1>; @@ -296,6 +308,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40006000 0x400>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM12_K>; clock-names = "int"; status = "disabled"; @@ -318,6 +332,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40007000 0x400>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM13_K>; clock-names = "int"; status = "disabled"; @@ -340,6 +356,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40008000 0x400>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM14_K>; clock-names = "int"; status = "disabled"; @@ -455,6 +473,9 @@ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART2_K>; wakeup-source; + dmas = <&dmamux1 43 0x400 0x15>, + <&dmamux1 44 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -464,6 +485,9 @@ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART3_K>; wakeup-source; + dmas = <&dmamux1 45 0x400 0x15>, + <&dmamux1 46 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -473,6 +497,9 @@ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART4_K>; wakeup-source; + dmas = <&dmamux1 63 0x400 0x15>, + <&dmamux1 64 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -482,6 +509,9 @@ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART5_K>; wakeup-source; + dmas = <&dmamux1 65 0x400 0x15>, + <&dmamux1 66 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -553,7 +583,7 @@ compatible = "st,stm32-cec"; reg = <0x40016000 0x400>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CEC_K>, <&clk_lse>; + clocks = <&rcc CEC_K>, <&rcc CEC>; clock-names = "cec", "hdmi-cec"; status = "disabled"; }; @@ -588,6 +618,9 @@ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART7_K>; wakeup-source; + dmas = <&dmamux1 79 0x400 0x15>, + <&dmamux1 80 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -597,6 +630,9 @@ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART8_K>; wakeup-source; + dmas = <&dmamux1 81 0x400 0x15>, + <&dmamux1 82 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -605,6 +641,11 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x44000000 0x400>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "brk", "up", "trg-com", "cc"; clocks = <&rcc TIM1_K>; clock-names = "int"; dmas = <&dmamux1 11 0x400 0x1>, @@ -641,6 +682,11 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x44001000 0x400>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "brk", "up", "trg-com", "cc"; clocks = <&rcc TIM8_K>; clock-names = "int"; dmas = <&dmamux1 47 0x400 0x1>, @@ -678,6 +724,9 @@ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART6_K>; wakeup-source; + dmas = <&dmamux1 71 0x400 0x15>, + <&dmamux1 72 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -725,6 +774,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x44006000 0x400>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM15_K>; clock-names = "int"; dmas = <&dmamux1 105 0x400 0x1>, @@ -752,6 +803,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x44007000 0x400>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM16_K>; clock-names = "int"; dmas = <&dmamux1 109 0x400 0x1>, @@ -776,6 +829,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x44008000 0x400>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM17_K>; clock-names = "int"; dmas = <&dmamux1 111 0x400 0x1>, @@ -1059,7 +1114,7 @@ }; sdmmc3: mmc@48004000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; @@ -1096,10 +1151,9 @@ reg = <0x4c001000 0x400>; st,proc-id = <0>; interrupts-extended = - <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <&exti 61 1>; - interrupt-names = "rx", "tx", "wakeup"; + <&exti 61 1>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; clocks = <&rcc IPCC>; wakeup-source; status = "disabled"; @@ -1381,7 +1435,7 @@ }; sdmmc1: mmc@58005000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; @@ -1396,7 +1450,7 @@ }; sdmmc2: mmc@58007000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; @@ -1453,7 +1507,7 @@ usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; - clocks = <&rcc USBH>, <&usbphyc>; + clocks = <&usbphyc>, <&rcc USBH>; resets = <&rcc USBH_R>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1462,7 +1516,7 @@ usbh_ehci: usb@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; - clocks = <&rcc USBH>; + clocks = <&usbphyc>, <&rcc USBH>; resets = <&rcc USBH_R>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; companion = <&usbh_ohci>; @@ -1560,7 +1614,7 @@ reg = <0x5c004000 0x400>; clocks = <&rcc RTCAPB>, <&rcc RTC>; clock-names = "pclk", "rtc_ck"; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -1602,7 +1656,7 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-pinctrl"; @@ -1733,7 +1787,7 @@ }; }; - pinctrl_z: pin-controller-z@54004000 { + pinctrl_z: pinctrl@54004000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1a.dts b/arch/arm/boot/dts/stm32mp151a-prtt1a.dts new file mode 100644 index 000000000000..75874eafde11 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1a.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander <david@protonic.nl> + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1A"; + compatible = "prt,prtt1a", "st,stm32mp151"; +}; + +ðernet0 { + phy-handle = <&phy0>; +}; + +&mdio0 { + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; +}; + +&pwm5_pins_a { + pins { + pinmux = <STM32_PINMUX('A', 0, AF2)>; /* TIM5_CH1 */ + }; +}; + +&pwm5_sleep_pins_a { + pins { + pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* TIM5_CH1 */ + }; +}; + +&timers5 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1c.dts b/arch/arm/boot/dts/stm32mp151a-prtt1c.dts new file mode 100644 index 000000000000..7ecf31263abc --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1c.dts @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander <david@protonic.nl> + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1C"; + compatible = "prt,prtt1c", "st,stm32mp151"; + + clock_ksz9031: clock-ksz9031 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clock_sja1105: clock-sja1105 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpioc 1 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; + }; +}; + +ðernet0 { + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&gpioa { + gpio-line-names = + "", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "", + "", "", "", "", "", "", "", "SPI1_nSS"; +}; + +&gpiod { + gpio-line-names = + "", "", "", "", "", "", "", "", + "WFM_RESET", "", "", "", "", "", "", ""; +}; + +&gpioe { + gpio-line-names = + "SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "", + "", "", "", "", "WFM_nIRQ", "", "", ""; +}; + +&gpiog { + gpio-line-names = + "", "", "", "", "", "", "", "PHY3_nINT", + "PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET", + "PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", ""; +}; + +&mdio0 { + /* All this DP83TD510E PHYs can't be probed before switch@0 is + * probed so we need to use compatible with PHYid + */ + /* TI DP83TD510E */ + t1l0_phy: ethernet-phy@6 { + compatible = "ethernet-phy-id2000.0181"; + reg = <6>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TD510E */ + t1l1_phy: ethernet-phy@7 { + compatible = "ethernet-phy-id2000.0181"; + reg = <7>; + interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TD510E */ + t1l2_phy: ethernet-phy@10 { + compatible = "ethernet-phy-id2000.0181"; + reg = <10>; + interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* Micrel KSZ9031 */ + rj45_phy: ethernet-phy@2 { + reg = <2>; + interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + + clocks = <&clock_ksz9031>; + }; +}; + +&qspi { + status = "disabled"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc2_b4_od_pins_a { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ + }; +}; + +&sdmmc2_b4_pins_a { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ + <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + }; +}; + +&sdmmc2_b4_sleep_pins_a { + pins { + pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ + <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ + <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ + }; +}; + +&sdmmc2_d47_pins_a { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + }; +}; + +&sdmmc2_d47_sleep_pins_a { + pins { + pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ + }; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_b>; + pinctrl-1 = <&sdmmc3_b4_od_pins_b>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; + non-removable; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mmc@1 { + compatible = "prt,prtt1c-wfm200", "silabs,wf200"; + reg = <1>; + }; +}; + +&sdmmc3_b4_od_pins_b { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ + }; +}; + +&sdmmc3_b4_pins_b { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ + <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ + }; +}; + +&sdmmc3_b4_sleep_pins_b { + pins { + pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ + <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ + <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins_b>; + pinctrl-names = "default"; + cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + switch@0 { + compatible = "nxp,sja1105q"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + spi-cpha; + + reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>; + + clocks = <&clock_sja1105>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "t1l0"; + phy-mode = "rmii"; + phy-handle = <&t1l0_phy>; + }; + + port@1 { + reg = <1>; + label = "t1l1"; + phy-mode = "rmii"; + phy-handle = <&t1l1_phy>; + }; + + port@2 { + reg = <2>; + label = "t1l2"; + phy-mode = "rmii"; + phy-handle = <&t1l2_phy>; + }; + + port@3 { + reg = <3>; + label = "rj45"; + phy-handle = <&rj45_phy>; + phy-mode = "rgmii-id"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <ðernet0>; + phy-mode = "rmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi new file mode 100644 index 000000000000..d865ab5d866b --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander <david@protonic.nl> + */ +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxad-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + aliases { + ethernet0 = ðernet0; + mdio-gpio0 = &mdio0; + serial0 = &uart4; + }; + + led-controller-0 { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + + /* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce + * stmmac MDC clock without reducing system bus rate, we need to use + * gpio based MDIO bus. + */ + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpioc 1 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + status = "okay"; +}; + +ðernet0_rmii_pins_a { + pins1 { + pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>; /* ETH1_RMII_TX_EN */ + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK input */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + }; +}; + +ðernet0_rmii_sleep_pins_a { + pins1 { + pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('B', 13, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; +}; + +&iwdg2 { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <104000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&qspi_bk1_pins_a { + pins1 { + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc1_b4_od_pins_a { + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + +&sdmmc1_b4_pins_a { + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart4_idle_pins_a { + pins1 { + pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-pull-up; + }; +}; + +&uart4_pins_a { + pins1 { + pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-pull-up; + }; +}; + +&uart4_sleep_pins_a { + pins { + pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ + }; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <®_3v3>; +}; + +&usbphyc_port1 { + phy-supply = <®_3v3>; +}; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1s.dts b/arch/arm/boot/dts/stm32mp151a-prtt1s.dts new file mode 100644 index 000000000000..ad25929e64e6 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-prtt1s.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander <david@protonic.nl> + */ +/dts-v1/; + +#include "stm32mp151a-prtt1l.dtsi" + +/ { + model = "Protonic PRTT1S"; + compatible = "prt,prtt1s", "st,stm32mp151"; +}; + +ðernet0 { + phy-handle = <&phy0>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + clock-frequency = <100000>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + humidity-sensor@40 { + compatible = "ti,hdc1080"; + reg = <0x40>; + }; + + co2-sensor@62 { + compatible = "sensirion,scd41"; + reg = <0x62>; + }; +}; + +&i2c1_pins_a { + pins { + pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('D', 13, AF5)>; /* I2C1_SDA */ + }; +}; + +&i2c1_sleep_pins_a { + pins { + pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('D', 13, ANALOG)>; /* I2C1_SDA */ + }; +}; + +&mdio0 { + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi index 1c1889b194cf..486084e0b80b 100644 --- a/arch/arm/boot/dts/stm32mp153.dtsi +++ b/arch/arm/boot/dts/stm32mp153.dtsi @@ -22,6 +22,13 @@ interrupt-affinity = <&cpu0>, <&cpu1>; }; + timer { + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + soc { m_can1: can@4400e000 { compatible = "bosch,m_can"; diff --git a/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts b/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts new file mode 100644 index 000000000000..c8b9818499ea --- /dev/null +++ b/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + * + * DHCOR STM32MP1 variant: + * DHCR-STM32MP153C-C065-R051-V33-SPI-I-01LG + * DHCOR PCB number: 586-100 or newer + * DRC Compact PCB number: 627-100 or newer + */ + +/dts-v1/; + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-drc-compact.dtsi" + +/ { + model = "DH electronics STM32MP153C DHCOR DRC Compact"; + compatible = "dh,stm32mp153c-dhcor-drc-compact", + "dh,stm32mp153c-dhcor-som", + "st,stm32mp153"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_c>; + pinctrl-1 = <&m_can1_sleep_pins_c>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts new file mode 100644 index 000000000000..e539cc80bef8 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157a-dk1.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board"; + compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts index 2a2829283456..9a2a4bc7d079 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ /dts-v1/; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts index d3058a036c74..60ce4425a7fd 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ /dts-v1/; @@ -43,5 +43,7 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts index a797eaa917b7..390ee8c05754 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ /dts-v1/; @@ -128,5 +128,7 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi index 01166ccacf2b..9de893101b40 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ / { diff --git a/arch/arm/boot/dts/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/stm32mp157a-iot-box.dts index 70f394b4d3c0..6a5a4af25bd9 100644 --- a/arch/arm/boot/dts/stm32mp157a-iot-box.dts +++ b/arch/arm/boot/dts/stm32mp157a-iot-box.dts @@ -58,6 +58,8 @@ /delete-property/st,hw-flow-ctrl; cts-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; rts-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; bluetooth { diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 5670b23812a2..0d7560ba2950 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ /dts-v1/; @@ -143,6 +143,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -150,5 +152,7 @@ &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts index 7a75868164dc..d949559be020 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ /dts-v1/; @@ -44,6 +44,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -51,5 +53,7 @@ &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi index 0b85175f151e..fb4600a59869 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ / { diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi index a4b14ef3caee..3a36f7fe0a2c 100644 --- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi @@ -288,6 +288,8 @@ pinctrl-0 = <&usart2_pins_b>; pinctrl-1 = <&usart2_sleep_pins_b>; st,hw-flow-ctrl; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -296,6 +298,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_c>; st,hw-flow-ctrl; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -303,6 +307,8 @@ &uart7 { pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts new file mode 100644 index 000000000000..97e4f94b0a24 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-dk2.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board"; + compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + phy-dsi-supply = <&scmi_reg18>; + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts new file mode 100644 index 000000000000..9cf0a44d2f47 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ed1.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter"; + compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 46b471d09c50..b1eb688a278a 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -384,6 +384,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts b/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts new file mode 100644 index 000000000000..33b3f11d24bb --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (c) 2021 emtrion GmbH +// Author: Reinhold Müller <reinhold.mueller@emtrion.de>. +// + +/dts-v1/; + +#include "stm32mp157c-emstamp-argon.dtsi" + +/ { + model = "emtrion STM32MP157C emSBC-Argon Developer Board"; + compatible = "emtrion,stm32mp157c-emsbc-argon", "emtrion,stm32mp157c-emstamp-argon", + "st,stm32mp157"; + + led: gpio_leds { + compatible = "gpio-leds"; + led-2 { + label = "red"; + gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + led-3 { + label = "green"; + gpios = <&gpioe 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + }; +}; + +&dac { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi new file mode 100644 index 000000000000..30156b7546ed --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi @@ -0,0 +1,546 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (c) 2021 emtrion GmbH +// Author: Reinhold Müller <reinhold.mueller@emtrion.de>. +// + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/st,stpmic1.h> + +/ { + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + serial1 = &usart2; + serial2 = &usart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x2000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x2000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10044000 { + compatible = "shared-dma-pool"; + reg = <0x10044000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + gpu_reserved: gpu@dc000000 { + reg = <0xdc000000 0x4000000>; + no-map; + }; + }; + + led: gpio_leds { + compatible = "gpio-leds"; + led-0 { + label = "panic"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + led-1 { + label = "heartbeat"; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; +}; + +&adc { + vdd-supply = <&vdd>; + vdda-supply = <&vdd>; + vref-supply = <&vrefbuf>; + status = "okay"; + + adc1: adc@0 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_in6_pins_a>; + st,min-sample-time-nsecs = <5000>; + st,adc-channels = <6>; + status = "disabled"; + }; + + adc2: adc@100 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + channel@12 { + reg = <12>; + label = "sense_temp"; + st,min-sample-time-ns = <9000>; + }; + channel@15 { + reg = <15>; + label = "vbat"; + st,min-sample-time-ns = <9000>; + }; + channel@16 { + reg = <16>; + label = "dac_out1"; + st,min-sample-time-ns = <9000>; + }; + channel@17 { + reg = <17>; + label = "dac_out1"; + st,min-sample-time-ns = <9000>; + }; + }; +}; + +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&dac { + pinctrl-names = "default"; + pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; + vref-supply = <&vdda>; + status = "disabled"; + + dac1: dac@1 { + status = "okay"; + }; + dac2: dac@2 { + status = "okay"; + }; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + status = "okay"; + snps,reset-gpio = <&gpioa 1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 30000 50000>; + pinctrl-0 = <ðernet0_rmii_pins_b>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth-ref-clk-sel; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; +}; + +&hash1 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO1 0>; + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO2 0>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO4 0>; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO5 0>; + regulator-always-on; + }; + + vdda: ldo6 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO6 0>; + regulator-boot-on; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + regulator-active-discharge; + }; + + vbus_usbh: pwr_sw2 { + regulator-name = "usbh_vbus"; + interrupts = <IT_OCP_SWOUT 0>; + regulator-always-on; + regulator-boot-on; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + interrupt-names = "wdg"; + recovery; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <133000000>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc2 { + arm,primecell-periphid = <0x10153180>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + cs-gpios = <&gpioz 3 0>; + status = "disabled"; +}; + +&timers1 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm { + pinctrl-0 = <&pwm1_pins_b>; + pinctrl-1 = <&pwm1_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@0 { + status = "okay"; + }; +}; + +&timers4 { + /delete-property/dmas; + /delete-property/dma-names; + pwm { + pinctrl-0 = <&pwm4_pins_b>; + pinctrl-1 = <&pwm4_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@3 { + status = "okay"; + }; +}; + +&timers5 { + /delete-property/dmas; + /delete-property/dma-names; + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@4 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + status = "okay"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_d>; + pinctrl-1 = <&usart3_sleep_pins_d>; + pinctrl-2 = <&usart3_idle_pins_d>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_hs_pins_a>; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts new file mode 100644 index 000000000000..3b9dd6f4ccc9 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ev1.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother"; + compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", + "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + phy-dsi-supply = <&scmi_reg18>; + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&m_can1 { + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index e222d2d2cb44..050c3c27a420 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -255,14 +255,22 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a + &qspi_bk2_pins_a + &qspi_cs2_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a + &qspi_bk2_sleep_pins_a + &qspi_cs2_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; status = "okay"; - flash0: mx66l51235l@0 { + flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; @@ -271,7 +279,7 @@ #size-cells = <1>; }; - flash1: mx66l51235l@1 { + flash1: flash@1 { compatible = "jedec,spi-nor"; reg = <1>; spi-rx-bus-width = <4>; diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index 1e9bf7eea0f1..e8d2ec41d537 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -248,5 +248,7 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts index 554f5d3bcdc3..ed66d25b8bf3 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts @@ -81,6 +81,8 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi index 4b10b013ffd5..35b1034aa3cf 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi @@ -131,6 +131,8 @@ &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -144,6 +146,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index fbf3826933e4..5f586f024060 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -287,6 +287,8 @@ &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -294,6 +296,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi index ba816ef8b9b2..abc595350e71 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi @@ -105,12 +105,16 @@ &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 8c41f819f776..238a611192e7 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -118,13 +118,12 @@ ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rmii"; max-speed = <100>; phy-handle = <&phy0>; - st,eth-ref-clk-sel; mdio0 { #address-cells = <1>; @@ -136,7 +135,7 @@ /* LAN8710Ai */ compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; - clocks = <&rcc ETHCK_K>; + clocks = <&rcc CK_MCO2>; reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; reset-assert-us = <500>; reset-deassert-us = <500>; @@ -196,7 +195,6 @@ "", "", "DHCOM-E", "", "", "", "", "", "", "", "", ""; - status = "okay"; }; &gpiod { @@ -447,6 +445,21 @@ }; }; +&rcc { + /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ + clocks = <&rcc CK_MCO2>; + clock-names = "ETH_RX_CLK/ETH_REF_CLK"; + + /* + * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, + * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, + * so that MCO2 behaves as a divider for the ETHRX clock here. + */ + assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <50000000>, <100000000>; +}; + &rng1 { status = "okay"; }; @@ -521,5 +534,7 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 6885948f3024..90933077d66d 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -126,6 +126,22 @@ }; }; +&dcmi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmi_pins_c>; + pinctrl-1 = <&dcmi_sleep_pins_c>; + status = "disabled"; + + port { + dcmi_0: endpoint { + remote-endpoint = <&stmipi_2>; + bus-type = <5>; + bus-width = <8>; + pclk-sample = <0>; + }; + }; +}; + ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_c>; @@ -141,6 +157,7 @@ compatible = "snps,dwmac-mdio"; reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; reset-delay-us = <1000>; + reset-post-delay-us = <1000>; phy0: ethernet-phy@7 { reg = <7>; @@ -218,6 +235,45 @@ }; &i2c4 { + stmipi: stmipi@14 { + compatible = "st,st-mipid02"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mco1_pins_a>; + pinctrl-1 = <&mco1_sleep_pins_a>; + reg = <0x14>; + clocks = <&rcc CK_MCO1>; + clock-names = "xclk"; + assigned-clocks = <&rcc CK_MCO1>; + assigned-clock-parents = <&rcc CK_HSE>; + assigned-clock-rates = <24000000>; + VDDE-supply = <&v1v8>; + VDDIN-supply = <&v1v8>; + reset-gpios = <&gpioz 0 GPIO_ACTIVE_LOW>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + stmipi_0: endpoint { + }; + }; + + port@2 { + reg = <2>; + stmipi_2: endpoint { + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; + remote-endpoint = <&dcmi_0>; + }; + }; + }; + }; + hdmi-transmitter@3d { compatible = "adi,adv7513"; reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; @@ -376,6 +432,8 @@ label = "LS-UART1"; pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -385,6 +443,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_a>; uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -394,6 +454,8 @@ pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_sleep_pins_a>; st,hw-flow-ctrl; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; bluetooth { diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi new file mode 100644 index 000000000000..27477bb219de --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = &ksz8851; + mmc0 = &sdmmc1; + rtc0 = &hwrtc; + rtc1 = &rtc; + serial0 = &uart4; + serial1 = &uart8; + serial2 = &usart3; + serial3 = &uart5; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + led1 { + label = "yellow:user0"; + gpios = <&gpioz 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + label = "red:user1"; + gpios = <&gpioz 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpioh 2 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; +}; + +&adc { /* X11 ADC inputs */ + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + reset-post-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_b>; + pinctrl-1 = <&fmc_sleep_pins_b>; + status = "okay"; + + ksz8851: ethernet@1,0 { + compatible = "micrel,ks8851-mll"; + reg = <1 0x0 0x2>, <1 0x2 0x20000>; + interrupt-parent = <&gpioc>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + bank-width = <2>; + + /* Timing values are in nS */ + st,fmc2-ebi-cs-mux-enable; + st,fmc2-ebi-cs-transaction-type = <4>; + st,fmc2-ebi-cs-buswidth = <16>; + st,fmc2-ebi-cs-address-setup-ns = <5>; + st,fmc2-ebi-cs-address-hold-ns = <5>; + st,fmc2-ebi-cs-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-data-setup-ns = <45>; + st,fmc2-ebi-cs-data-hold-ns = <1>; + st,fmc2-ebi-cs-write-address-setup-ns = <5>; + st,fmc2-ebi-cs-write-address-hold-ns = <5>; + st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-write-data-setup-ns = <45>; + st,fmc2-ebi-cs-write-data-hold-ns = <1>; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", + "DRCC-VAR2", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpioe { + gpio-line-names = "", "", "", "", + "", "DRCC-GPIO0", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiog { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "DRCC-GPIO5", "", "", ""; +}; + +&gpioh { + gpio-line-names = "", "", "", "DRCC-HW2", + "DRCC-GPIO4", "", "", "", + "DRCC-HW1", "DRCC-HW0", "", "DRCC-VAR1", + "DRCC-VAR0", "", "", "DRCC-GPIO6"; +}; + +&gpioi { + gpio-line-names = "", "", "", "", + "", "", "", "DRCC-GPIO2", + "", "DRCC-GPIO1", "", "", + "", "", "", ""; +}; + +&i2c1 { /* X11 I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + hwrtc: rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&sdmmc1 { /* MicroSD */ + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd>; + vqmmc-supply = <&vdd>; + status = "okay"; +}; + +&sdmmc2 { /* eMMC */ + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; + status = "okay"; +}; + +&sdmmc3 { /* SDIO Wi-Fi */ + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + bus-width = <4>; + mmc-ddr-3_3v; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + status = "okay"; +}; + +&spi2 { /* X11 SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_b>; + cs-gpios = <&gpioi 0 0>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&uart4 { + label = "UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_d>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart5 { /* X11 UART */ + label = "X11-UART5"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + label = "RS485-1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart3 { /* RS485 or RS232 */ + label = "RS485-2"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart3_pins_e>; + pinctrl-1 = <&usart3_sleep_pins_e>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + connector { + compatible = "usb-a-connector"; + vbus-supply = <&vbus_sw>; + }; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi index 75172314d7af..9937b28548c2 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi @@ -18,6 +18,11 @@ }; }; +&vdd { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; +}; + &pwr_regulators { vdd-supply = <&vdd_io>; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index 44ecc4708587..134a798ad3f2 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -19,6 +19,48 @@ device_type = "memory"; reg = <0xc0000000 0x40000000>; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; }; &crc1 { @@ -77,8 +119,8 @@ vdd: buck3 { regulator-name = "vdd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; regulator-initial-mode = <0>; regulator-over-current-protection; @@ -179,11 +221,25 @@ }; }; +&ipcc { + status = "okay"; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; }; +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + &pwr_regulators { vdd-supply = <&vdd>; vdd_3v3_usbfs-supply = <&vdd_usb>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 6caeb448c190..8b48d3c89a04 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -650,6 +650,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -658,6 +660,8 @@ pinctrl-0 = <&uart7_pins_c>; pinctrl-1 = <&uart7_sleep_pins_c>; pinctrl-2 = <&uart7_idle_pins_c>; + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; }; @@ -673,6 +677,14 @@ &usbh_ehci { phys = <&usbphyc_port0>; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3>; + }; }; &usbotg_hs { diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi index 6706d8311a66..935b7084b5a2 100644 --- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi @@ -50,12 +50,6 @@ no-map; }; }; - - reg_sip_eeprom: regulator_eeprom { - compatible = "regulator-fixed"; - regulator-name = "sip_eeprom"; - regulator-always-on; - }; }; &i2c4 { @@ -78,6 +72,7 @@ compatible = "st,stpmic1-regulators"; ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; ldo6-supply = <&v3v3>; pwr_sw1-supply = <&bst_out>; @@ -203,7 +198,7 @@ sip_eeprom: eeprom@50 { compatible = "atmel,24c32"; - vcc-supply = <®_sip_eeprom>; + vcc-supply = <&vdd>; reg = <0x50>; }; }; diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts index 0a562b2cc5bc..62e7aa587f89 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts @@ -63,7 +63,7 @@ compatible = "gpio-keys-polled"; poll-interval = <20>; - left-joystick-left { + event-left-joystick-left { label = "Left Joystick Left"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -71,7 +71,7 @@ gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */ }; - left-joystick-right { + event-left-joystick-right { label = "Left Joystick Right"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -79,7 +79,7 @@ gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */ }; - left-joystick-up { + event-left-joystick-up { label = "Left Joystick Up"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -87,7 +87,7 @@ gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */ }; - left-joystick-down { + event-left-joystick-down { label = "Left Joystick Down"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -95,7 +95,7 @@ gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */ }; - right-joystick-left { + event-right-joystick-left { label = "Right Joystick Left"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -103,7 +103,7 @@ gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */ }; - right-joystick-right { + event-right-joystick-right { label = "Right Joystick Right"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -111,7 +111,7 @@ gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */ }; - right-joystick-up { + event-right-joystick-up { label = "Right Joystick Up"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -119,7 +119,7 @@ gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */ }; - right-joystick-down { + event-right-joystick-down { label = "Right Joystick Down"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -127,7 +127,7 @@ gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */ }; - dpad-left { + event-dpad-left { label = "DPad Left"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -135,7 +135,7 @@ gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */ }; - dpad-right { + event-dpad-right { label = "DPad Right"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -143,7 +143,7 @@ gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */ }; - dpad-up { + event-dpad-up { label = "DPad Up"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -151,7 +151,7 @@ gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */ }; - dpad-down { + event-dpad-down { label = "DPad Down"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -159,49 +159,49 @@ gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */ }; - x { + event-x { label = "Button X"; linux,code = <BTN_X>; gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */ }; - y { + event-y { label = "Button Y"; linux,code = <BTN_Y>; gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */ }; - a { + event-a { label = "Button A"; linux,code = <BTN_A>; gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */ }; - b { + event-b { label = "Button B"; linux,code = <BTN_B>; gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */ }; - select { + event-select { label = "Select Button"; linux,code = <BTN_SELECT>; gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */ }; - start { + event-start { label = "Start Button"; linux,code = <BTN_START>; gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */ }; - top-left { + event-top-left { label = "Top Left Button"; linux,code = <BTN_TL>; gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */ }; - top-right { + event-top-right { label = "Top Right Button"; linux,code = <BTN_TR>; gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */ diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 1ac82376baef..a332d61fd561 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -77,19 +77,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Key Back"; linux,code = <KEY_BACK>; gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; }; - home { + key-home { label = "Key Home"; linux,code = <KEY_HOME>; gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; }; - menu { + key-menu { label = "Key Menu"; linux,code = <KEY_MENU>; gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts index 2ce361f8fede..3a6c4bd0a44f 100644 --- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts +++ b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts @@ -67,18 +67,18 @@ compatible = "gpio-leds"; led-0 { - label ="licheepi:red:usr"; + label = "licheepi:red:usr"; gpios = <&pio 2 5 GPIO_ACTIVE_LOW>; }; led-1 { - label ="licheepi:green:usr"; + label = "licheepi:green:usr"; gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; default-state = "on"; }; led-2 { - label ="licheepi:blue:usr"; + label = "licheepi:blue:usr"; gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 715d74854449..6cdadba6a3ac 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -46,6 +46,7 @@ #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/clock/sun6i-a31-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/reset/sun6i-a31-ccu.h> / { @@ -598,7 +599,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun6i-a31-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -612,7 +613,8 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -1319,7 +1321,7 @@ ar100: ar100_clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; - clocks = <&rtc 0>, <&osc24M>, + clocks = <&rtc CLK_OSC32K>, <&osc24M>, <&ccu CLK_PLL_PERIPH>, <&ccu CLK_PLL_PERIPH>; clock-output-names = "ar100"; @@ -1354,7 +1356,7 @@ ir_clk: ir_clk { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&rtc 0>, <&osc24M>; + clocks = <&rtc CLK_OSC32K>, <&osc24M>; clock-output-names = "ir"; }; @@ -1385,9 +1387,8 @@ interrupt-parent = <&r_intc>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; - resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts b/arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts new file mode 100644 index 000000000000..097e479c2772 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Conley Lee + * Conley Lee <conleylee@foxmail.com> + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "HAOYU Electronics Marsboard A20"; + compatible = "haoyu,a20-marsboard", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>; + phy-handle = <&phy0>; + phy-mode = "mii"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ + status = "okay"; +}; + +&gmac_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + gmac_txerr: gmac-txerr-pin { + pins = "PA17"; + function = "gmac"; + }; +}; + +®_ahci_5v { + status = "okay"; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index 4f8d55d3ba79..928b86a95f34 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -78,19 +78,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Key Back"; linux,code = <KEY_BACK>; gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; }; - home { + key-home { label = "Key Home"; linux,code = <KEY_HOME>; gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; }; - menu { + key-menu { label = "Key Menu"; linux,code = <KEY_MENU>; gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 4461d5098b20..f630ab55bb6a 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -44,6 +44,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> @@ -329,7 +330,7 @@ ccu: clock@1c20000 { reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -340,7 +341,8 @@ reg = <0x01c20800 0x400>; interrupt-parent = <&r_intc>; /* interrupts get set in SoC specific dtsi file */ - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -810,9 +812,8 @@ reg = <0x01f02c00 0x400>; interrupt-parent = <&r_intc>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; - resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index d5c7b7984d85..d729b7c705db 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -47,10 +47,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -106,7 +106,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -181,7 +181,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <1500000>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index f19ed981da9d..3706216ffb40 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -169,7 +169,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "winbond,w25q128"; + compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; }; diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index cd9f655e4f92..27a0d51289dd 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -93,10 +93,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -125,7 +125,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts index ff0a7a952e0c..f5c8ccc5b872 100644 --- a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts +++ b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts @@ -39,16 +39,16 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ }; - user { + key-user { label = "user"; linux,code = <BTN_0>; gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts index 8e7dfcffe1fb..43641cb82398 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts @@ -37,10 +37,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - k1 { + key-0 { label = "k1"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ @@ -90,7 +90,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; @@ -151,7 +151,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts index be49eabbff94..9e1a33f94cad 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts @@ -103,12 +103,40 @@ }; }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ + host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ + shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + }; +}; + &usbphy { /* USB VBUS is always on */ status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts index 9f33f6fae595..df71fab3cf4e 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -45,6 +45,10 @@ / { model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + }; }; &ehci0 { diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts index 26e2e6172e0d..42cd1131adf3 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts @@ -46,7 +46,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; @@ -147,7 +147,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index fc45d5aaa67f..cf8413fba6c1 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -73,11 +73,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - input-name = "k1"; - k1 { + key-0 { label = "k1"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 9daffd90c12f..f1f9dbead32a 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -88,16 +88,16 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw2 { + switch-2 { label = "sw2"; linux,code = <BTN_1>; gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; }; - sw4 { + switch-4 { label = "sw4"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts index 6f9c97add54e..305b34a321f5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts @@ -87,10 +87,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 4759ba3f2986..59f6f6d5e7ca 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -86,10 +86,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index 90f75fa85e68..b96e015f54ee 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -86,10 +86,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "sw4"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 845f25235407..eac2349a2380 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -245,7 +245,7 @@ cpu_thermal: cpu-thermal { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&ths 0>; + thermal-sensors = <&ths>; trips { cpu_hot_trip: cpu-hot { diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts index bf5b5e2f6168..bc394686fedb 100644 --- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts @@ -91,7 +91,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -283,7 +283,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_dldo1>; vddio-supply = <®_aldo3>; diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index a6a1087a0c9b..28197bbcb1d5 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -43,6 +43,7 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -113,6 +114,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi b/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi new file mode 100644 index 000000000000..649928b361af --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi @@ -0,0 +1,52 @@ +/{ + cpu0_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1000000 1000000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1100000 1100000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1160000 1160000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1240000 1240000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <2000000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu0_opp_table>; +}; diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi index 265e0fa57a32..9f39b5a2bb35 100644 --- a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi +++ b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi @@ -5,6 +5,11 @@ // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; &i2c0 { status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 03d3e5f45a09..4ef26d8f5340 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -42,6 +42,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r40-ccu.h> #include <dt-bindings/clock/sun8i-tcon-top.h> @@ -84,24 +85,36 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; }; @@ -117,6 +130,30 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 0>; + + trips { + cpu_hot_trip: cpu-hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_very_hot_trip: cpu-very-hot { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + cpu-hot-limit { + trip = <&cpu_hot_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpu_thermal: gpu-thermal { @@ -485,7 +522,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -504,7 +541,8 @@ compatible = "allwinner,sun8i-r40-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -1231,7 +1269,7 @@ reg-io-width = <1>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>, <&rtc 0>; + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; diff --git a/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts b/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts index 6931aaab2382..9f472521f4a4 100644 --- a/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts +++ b/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts @@ -45,6 +45,7 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -88,6 +89,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index b30bc1a25ebb..db194c606fdc 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -42,6 +42,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-v3s-ccu.h> #include <dt-bindings/reset/sun8i-v3s-ccu.h> #include <dt-bindings/clock/sun8i-de2.h> @@ -321,7 +322,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -342,7 +343,8 @@ reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -593,6 +595,17 @@ #size-cells = <0>; }; + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + csi1: camera@1cb4000 { compatible = "allwinner,sun8i-v3s-csi"; reg = <0x01cb4000 0x3000>; @@ -604,16 +617,5 @@ resets = <&ccu RST_BUS_CSI>; status = "disabled"; }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; }; }; diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index 47954551f573..434871040aca 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -42,6 +42,7 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -107,6 +108,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index ce4fa6706d06..7d3f3300f431 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -1218,7 +1218,6 @@ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; - resets = <&apbs_rst 0>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts index a1154e6c7cb5..04e59b8381cb 100644 --- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts @@ -11,12 +11,43 @@ compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; aliases { + mmc0 = &mmc0; serial0 = &uart0; + spi0 = &spi0; }; chosen { stdout-path = "serial0:115200n8"; }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + status = "okay"; + vmmc-supply = <®_vcc3v3>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pc_pins>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; }; &uart0 { diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 6100d3b75f61..0edc1724407b 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -4,6 +4,9 @@ * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com> */ +#include <dt-bindings/clock/suniv-ccu-f1c100s.h> +#include <dt-bindings/reset/suniv-ccu-f1c100s.h> + / { #address-cells = <1>; #size-cells = <1>; @@ -26,9 +29,13 @@ }; cpus { - cpu { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0x0>; }; }; @@ -62,6 +69,70 @@ }; }; + spi0: spi@1c05000 { + compatible = "allwinner,suniv-f1c100s-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <10>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,suniv-f1c100s-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <11>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <23>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,suniv-f1c100s-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <24>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ccu: clock@1c20000 { compatible = "allwinner,suniv-f1c100s-ccu"; reg = <0x01c20000 0x400>; @@ -82,13 +153,24 @@ compatible = "allwinner,suniv-f1c100s-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <38>, <39>, <40>; - clocks = <&ccu 37>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + }; + + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + uart0_pe_pins: uart0-pe-pins { pins = "PE0", "PE1"; function = "uart0"; @@ -98,14 +180,16 @@ timer@1c20c00 { compatible = "allwinner,suniv-f1c100s-timer"; reg = <0x01c20c00 0x90>; - interrupts = <13>; + interrupts = <13>, <14>, <15>; clocks = <&osc24M>; }; wdt: watchdog@1c20ca0 { compatible = "allwinner,suniv-f1c100s-wdt", - "allwinner,sun4i-a10-wdt"; + "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; + interrupts = <16>; + clocks = <&osc32k>; }; uart0: serial@1c25000 { @@ -114,8 +198,8 @@ interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 38>; - resets = <&ccu 24>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -125,8 +209,8 @@ interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 39>; - resets = <&ccu 25>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -136,8 +220,8 @@ interrupts = <3>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 40>; - resets = <&ccu 26>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi b/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi new file mode 100644 index 000000000000..493d32357e4e --- /dev/null +++ b/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Sunplus SP7021 + * + * Copyright (C) 2021 Sunplus Technology Co. + */ + +#include "sunplus-sp7021.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "sunplus,sp7021-achip", "sunplus,sp7021"; + model = "Sunplus SP7021 (CA7)"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clock-frequency = <931000000>; + }; + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clock-frequency = <931000000>; + }; + cpu2: cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + clock-frequency = <931000000>; + }; + cpu3: cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + clock-frequency = <931000000>; + }; + }; + + gic: interrupt-controller@9f101000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x9f101000 0x1000>, + <0x9f102000 0x2000>, + <0x9f104000 0x2000>, + <0x9f106000 0x2000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <XTAL>; + arm,cpu-registers-not-fw-configured; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + soc@9c000000 { + intc: interrupt-controller@780 { + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */ + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */ + }; + }; +}; diff --git a/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts b/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts new file mode 100644 index 000000000000..d5c5ffc20565 --- /dev/null +++ b/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Sunplus SP7021 Demo V3 SBC board + * + * Copyright (C) Sunplus Technology Co. + */ + +/dts-v1/; + +#include "sunplus-sp7021-achip.dtsi" + +/ { + compatible = "sunplus,sp7021-demo-v3", "sunplus,sp7021"; + model = "Sunplus SP7021/CA7/Demo_V3"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/sunplus-sp7021.dtsi b/arch/arm/boot/dts/sunplus-sp7021.dtsi new file mode 100644 index 000000000000..7dc4ce3619c7 --- /dev/null +++ b/arch/arm/boot/dts/sunplus-sp7021.dtsi @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Sunplus SP7021 + * + * Copyright (C) 2021 Sunplus Technology Co. + */ + +#include <dt-bindings/clock/sunplus,sp7021-clkc.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/reset/sunplus,sp7021-reset.h> +#include <dt-bindings/pinctrl/sppctl-sp7021.h> +#include <dt-bindings/gpio/gpio.h> + +#define XTAL 27000000 + +/ { + compatible = "sunplus,sp7021"; + model = "Sunplus SP7021"; + + clocks { + extclk: osc0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <XTAL>; + clock-output-names = "extclk"; + }; + }; + + soc@9c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x9c000000 0x400000>; + interrupt-parent = <&intc>; + + clkc: clock-controller@4 { + compatible = "sunplus,sp7021-clkc"; + reg = <0x4 0x28>, + <0x200 0x44>, + <0x268 0x04>; + clocks = <&extclk>; + #clock-cells = <1>; + }; + + intc: interrupt-controller@780 { + compatible = "sunplus,sp7021-intc"; + reg = <0x780 0x80>, <0xa80 0x80>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + otp: otp@af00 { + compatible = "sunplus,sp7021-ocotp"; + reg = <0xaf00 0x34>, <0xaf80 0x58>; + reg-names = "hb_gpio", "otprx"; + clocks = <&clkc CLK_OTPRX>; + resets = <&rstc RST_OTPRX>; + #address-cells = <1>; + #size-cells = <1>; + + therm_calib: thermal-calibration@14 { + reg = <0x14 0x3>; + }; + disc_vol: disconnect-voltage@18 { + reg = <0x18 0x2>; + }; + mac_addr0: mac-address0@34 { + reg = <0x34 0x6>; + }; + mac_addr1: mac-address1@3a { + reg = <0x3a 0x6>; + }; + }; + + pctl: pinctrl@100 { + compatible = "sunplus,sp7021-pctl"; + reg = <0x100 0x100>, + <0x300 0x100>, + <0x32e4 0x1C>, + <0x80 0x20>; + reg-names = "moon2", "gpioxt", "first", "moon1"; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clkc CLK_GPIO>; + resets = <&rstc RST_GPIO>; + + emac_pins: pinmux-emac-pins { + sunplus,pins = < + SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0) + SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0) + SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0) + SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0) + SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0) + SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0) + SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0) + SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0) + SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0) + SPPCTL_IOPAD(45,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXER,0) + SPPCTL_IOPAD(59,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXEN,0) + SPPCTL_IOPAD(57,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD0,0) + SPPCTL_IOPAD(58,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD1,0) + SPPCTL_IOPAD(54,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_CRSDV,0) + SPPCTL_IOPAD(55,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD0,0) + SPPCTL_IOPAD(56,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD1,0) + SPPCTL_IOPAD(53,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXER,0) + >; + sunplus,zerofunc = < + MUXF_L2SW_LED_FLASH0 + MUXF_L2SW_LED_FLASH1 + MUXF_L2SW_LED_ON0 + MUXF_L2SW_LED_ON1 + MUXF_DAISY_MODE + >; + }; + + emmc_pins: pinmux-emmc-pins { + function = "CARD0_EMMC"; + groups = "CARD0_EMMC"; + }; + + leds_pins: pinmux-leds-pins { + sunplus,pins = < SPPCTL_IOPAD(0,SPPCTL_PCTL_G_GPIO,0,SPPCTL_PCTL_L_OUT) >; + }; + + sdcard_pins: pinmux-sdcard-pins { + function = "SD_CARD"; + groups = "SD_CARD"; + sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >; + }; + + spi0_pins: pinmux-spi0-pins { + sunplus,pins = < + SPPCTL_IOPAD(26,SPPCTL_PCTL_G_GPIO,0,0) + SPPCTL_IOPAD(28,SPPCTL_PCTL_G_GPIO,0,0) + SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DO,0) + SPPCTL_IOPAD(25,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DI,0) + SPPCTL_IOPAD(27,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_CLK,0) + >; + }; + + uart0_pins: pinmux-uart0-pins { + function = "UA0"; + groups = "UA0"; + }; + + uart1_pins: pinmux-uart1-pins { + sunplus,pins = < + SPPCTL_IOPAD(14,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0) + SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0) + >; + }; + + uart2_pins: pinmux-uart2-pins { + sunplus,pins = < + SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA2_TX,0) + SPPCTL_IOPAD(17,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RX,0) + SPPCTL_IOPAD(18,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RTS,0) + SPPCTL_IOPAD(19,SPPCTL_PCTL_G_PMUX,MUXF_UA2_CTS,0) + >; + }; + + uart4_pins: pinmux-uart4-pins { + sunplus,pins = < + SPPCTL_IOPAD(22,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0) + SPPCTL_IOPAD(20,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0) + SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RTS,0) + SPPCTL_IOPAD(21,SPPCTL_PCTL_G_PMUX,MUXF_UA4_CTS,0) + >; + }; + }; + + rstc: reset@54 { + compatible = "sunplus,sp7021-reset"; + reg = <0x54 0x28>; + #reset-cells = <1>; + }; + + rtc: rtc@3a00 { + compatible = "sunplus,sp7021-rtc"; + reg = <0x3a00 0x80>; + reg-names = "rtc"; + clocks = <&clkc CLK_RTC>; + resets = <&rstc RST_RTC>; + interrupts = <163 IRQ_TYPE_EDGE_RISING>; + }; + + spi_controller0: spi@2d80 { + compatible = "sunplus,sp7021-spi"; + reg = <0x2d80 0x80>, <0x2e00 0x80>; + reg-names = "master", "slave"; + interrupts = <144 IRQ_TYPE_LEVEL_HIGH>, + <146 IRQ_TYPE_LEVEL_HIGH>, + <145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma_w", "master_risc", "slave_risc"; + clocks = <&clkc CLK_SPI_COMBO_0>; + resets = <&rstc RST_SPI_COMBO_0>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + cs-gpios = <&pctl 26 GPIO_ACTIVE_LOW>, + <&pctl 28 GPIO_ACTIVE_LOW>; + }; + + spi_controller1: spi@f480 { + compatible = "sunplus,sp7021-spi"; + reg = <0xf480 0x80>, <0xf500 0x80>; + reg-names = "master", "slave"; + interrupts = <67 IRQ_TYPE_LEVEL_HIGH>, + <69 IRQ_TYPE_LEVEL_HIGH>, + <68 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma_w", "master_risc", "slave_risc"; + clocks = <&clkc CLK_SPI_COMBO_1>; + resets = <&rstc RST_SPI_COMBO_1>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + + spi_controller2: spi@f600 { + compatible = "sunplus,sp7021-spi"; + reg = <0xf600 0x80>, <0xf680 0x80>; + reg-names = "master", "slave"; + interrupts = <70 IRQ_TYPE_LEVEL_HIGH>, + <72 IRQ_TYPE_LEVEL_HIGH>, + <71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma_w", "master_risc", "slave_risc"; + clocks = <&clkc CLK_SPI_COMBO_2>; + resets = <&rstc RST_SPI_COMBO_2>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + + spi_controller3: spi@f780 { + compatible = "sunplus,sp7021-spi"; + reg = <0xf780 0x80>, <0xf800 0x80>; + reg-names = "master", "slave"; + interrupts = <73 IRQ_TYPE_LEVEL_HIGH>, + <75 IRQ_TYPE_LEVEL_HIGH>, + <74 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma_w", "master_risc", "slave_risc"; + clocks = <&clkc CLK_SPI_COMBO_3>; + resets = <&rstc RST_SPI_COMBO_3>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + + uart0: serial@900 { + compatible = "sunplus,sp7021-uart"; + reg = <0x900 0x80>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLK_UA0>; + resets = <&rstc RST_UA0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + }; + + uart1: serial@980 { + compatible = "sunplus,sp7021-uart"; + reg = <0x980 0x80>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLK_UA1>; + resets = <&rstc RST_UA1>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; + }; + + uart2: serial@800 { + compatible = "sunplus,sp7021-uart"; + reg = <0x800 0x80>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLK_UA2>; + resets = <&rstc RST_UA2>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; + }; + + uart3: serial@880 { + compatible = "sunplus,sp7021-uart"; + reg = <0x880 0x80>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLK_UA3>; + resets = <&rstc RST_UA3>; + status = "disabled"; + }; + + uart4: serial@8780 { + compatible = "sunplus,sp7021-uart"; + reg = <0x8780 0x80>; + interrupts = <134 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLK_UA4>; + resets = <&rstc RST_UA4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "disabled"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + system-led { + label = "system-led"; + gpios = <&pctl 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi index d03f5853ef7b..e899d14f38c3 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi @@ -77,10 +77,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -101,7 +101,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -221,7 +221,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <1500000>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi index fc67e30fe212..60804b0e6c56 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi @@ -22,7 +22,7 @@ compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ post-power-on-delay-ms = <200>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -124,7 +124,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 4aeca9e7e30d..09aefb4e90f8 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -40,6 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-h3-ccu.h> #include <dt-bindings/clock/sun8i-r-ccu.h> @@ -386,7 +387,7 @@ ccu: clock@1c20000 { /* compatible is in per SoC .dtsi file */ reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -398,7 +399,8 @@ interrupt-parent = <&r_intc>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -818,7 +820,7 @@ reg-io-width = <1>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>, <&rtc 0>; + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; @@ -878,7 +880,7 @@ r_ccu: clock@1f01400 { compatible = "allwinner,sun8i-h3-r-ccu"; reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; @@ -913,12 +915,26 @@ #size-cells = <0>; }; + r_uart: serial@1f02800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01f02800 0x400>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&r_ccu CLK_APB0_UART>; + resets = <&r_ccu RST_APB0_UART>; + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins>; + status = "disabled"; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupt-parent = <&r_intc>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -939,6 +955,11 @@ pins = "PL10"; function = "s_pwm"; }; + + r_uart_pins: r-uart-pins { + pins = "PL2", "PL3"; + function = "s_uart"; + }; }; r_pwm: pwm@1f03800 { diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi index 9e14fe5fdcde..89731bb34c6b 100644 --- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi +++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi @@ -42,10 +42,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/tegra114-asus-tf701t.dts index b791ce97424b..284209b0bd96 100644 --- a/arch/arm/boot/dts/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/tegra114-asus-tf701t.dts @@ -684,7 +684,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_default>; - power { + button-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -692,14 +692,14 @@ wakeup-source; }; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; debounce-interval = <10>; }; - volume-down { + button-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -715,7 +715,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_hall_sensor_default>; - hall-sensor { + switch-hall-sensor { label = "Hall Effect Sensor"; gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 658edfb8d7fa..fffd62bcea6a 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1161,26 +1161,26 @@ gpio-keys { compatible = "gpio-keys"; - home { + key-home { label = "Home"; gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; }; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - volume_down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; }; - volume_up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 2498cf18fd39..b9d00009d1f4 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1025,19 +1025,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Back"; gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; }; - home { + key-home { label = "Home"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; }; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index ef8f722dd9cb..f02d8c79eee7 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -282,20 +282,20 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - volume_down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; }; - volume_up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index 3209554ec7e6..bce12b3411fc 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -191,7 +191,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "WAKE1_MICO"; gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 814257c79bf1..800283ad6bdc 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -193,7 +193,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "WAKE1_MICO"; gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 28b889e4e33b..f41dd4039c07 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1886,7 +1886,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts b/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts index d35fb79d2f51..4db43324dafa 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts @@ -5,7 +5,13 @@ / { /* Version of Nyan Big with 1080p panel */ - panel { - compatible = "auo,b133htn01"; + host1x@50000000 { + dpaux@545c0000 { + aux-bus { + panel: panel { + compatible = "auo,b133htn01"; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index 1d2aac2cb6d0..fdc1d64dfff9 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -13,12 +13,15 @@ "google,nyan-big-rev1", "google,nyan-big-rev0", "google,nyan-big", "google,nyan", "nvidia,tegra124"; - panel: panel { - compatible = "auo,b133xtn01"; - - power-supply = <&vdd_3v3_panel>; - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; + host1x@50000000 { + dpaux@545c0000 { + aux-bus { + panel: panel { + compatible = "auo,b133xtn01"; + backlight = <&backlight>; + }; + }; + }; }; mmc@700b0400 { /* SD Card on this bus */ diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts index 677babde6460..abdf4456826f 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts +++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts @@ -15,12 +15,15 @@ "google,nyan-blaze-rev0", "google,nyan-blaze", "google,nyan", "nvidia,tegra124"; - panel: panel { - compatible = "samsung,ltn140at29-301"; - - power-supply = <&vdd_3v3_panel>; - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; + host1x@50000000 { + dpaux@545c0000 { + aux-bus { + panel: panel { + compatible = "samsung,ltn140at29-301"; + backlight = <&backlight>; + }; + }; + }; }; sound { diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index a93cfb492ba1..13061ab5247b 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -603,7 +603,7 @@ gpio-keys { compatible = "gpio-keys"; - lid { + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; linux,input-type = <5>; @@ -612,7 +612,7 @@ wakeup-source; }; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 232c90604df9..8f40fcfc11b0 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -48,6 +48,13 @@ dpaux@545c0000 { vdd-supply = <&vdd_3v3_panel>; status = "okay"; + + aux-bus { + panel: panel { + compatible = "lg,lp129qe"; + backlight = <&backlight>; + }; + }; }; }; @@ -1071,7 +1078,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -1080,13 +1087,6 @@ }; }; - panel: panel { - compatible = "lg,lp129qe"; - power-supply = <&vdd_3v3_panel>; - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; - }; - vdd_mux: regulator-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index a170a4ba36c1..dac6d02a1b15 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -417,7 +417,7 @@ vddio-supply = <&vdd_1v8_sys>; device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; }; }; @@ -905,7 +905,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; linux,code = <KEY_POWER>; @@ -914,7 +914,7 @@ wakeup-source; }; - rotation-lock { + key-rotation-lock { label = "Rotate-lock"; gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; linux,code = <SW_ROTATE_LOCK>; @@ -922,7 +922,7 @@ debounce-interval = <10>; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -931,7 +931,7 @@ wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts index 020172ee7340..bf797a1f27ea 100644 --- a/arch/arm/boot/dts/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts @@ -436,17 +436,27 @@ }; }; + spdif@70002400 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + i2s@70002800 { status = "okay"; + + nvidia,fixed-parent-rate; }; serial@70006040 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; /* GPS BCM4751 */ }; serial@70006200 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; status = "okay"; /* Azurewave AW-NH615 BCM4329B1 */ @@ -467,7 +477,7 @@ vddio-supply = <&vdd_1v8_sys>; device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; }; }; @@ -756,7 +766,7 @@ lpddr2 { compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; - revision-id1 = <1>; + revision-id = <1 0>; density = <2048>; io-width = <16>; }; @@ -970,7 +980,7 @@ gpio-keys { compatible = "gpio-keys"; - dock-hall-sensor { + switch-dock-hall-sensor { label = "Lid"; gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -980,7 +990,7 @@ wakeup-source; }; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -989,7 +999,7 @@ wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -998,7 +1008,7 @@ wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts index d2a3bf9d28bd..cb1190b77db3 100644 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -209,7 +209,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "SODIMM pin 45 wakeup"; gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 00ecbbd5e9e1..53487cc21513 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -191,7 +191,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "SODIMM pin 45 wakeup"; gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 1eefb9ee4ac8..8ebd8afc857d 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -691,7 +691,7 @@ #address-cells = <1>; #size-cells = <0>; - asix@1 { + ethernet@1 { compatible = "usbb95,772b"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 79b6b79fab65..11f21aeba8e9 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -648,7 +648,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index d53a175dc17a..48fe628c6d87 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -13,6 +13,8 @@ compatible = "compal,paz00", "nvidia,tegra20"; aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* MicroSD */ rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; serial0 = &uarta; @@ -558,7 +560,7 @@ status = "okay"; }; - mmc@c8000000 { + sdmmc1: mmc@c8000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -566,7 +568,7 @@ bus-width = <4>; }; - mmc@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; @@ -594,7 +596,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "Wakeup"; gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index c4a6a6a94559..5b4c5ef30996 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -800,14 +800,14 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - lid { + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; linux,input-type = <5>; /* EV_SW */ diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index de39c5465c0a..0e19bd0a847c 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -183,8 +183,8 @@ }; conf_ata { nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "cdev2", "dap1", "dtb", "gma", - "gmb", "gmc", "gmd", "gme", "gpu7", + "cdev1", "cdev2", "dap1", "dtb", "dtf", + "gma", "gmb", "gmc", "gmd", "gme", "gpu7", "gpv", "i2cp", "irrx", "irtx", "pta", "rm", "slxa", "slxk", "spia", "spib", "uac"; @@ -203,7 +203,7 @@ }; conf_crtp { nvidia,pins = "crtp", "dap2", "dap3", "dap4", - "dtc", "dte", "dtf", "gpu", "sdio1", + "dtc", "dte", "gpu", "sdio1", "slxc", "slxd", "spdi", "spdo", "spig", "uda"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 9d0c86711de2..dc51835423a9 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -388,7 +388,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index b0a00970b61c..caa17e876e41 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -628,7 +628,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 93b83b3c5655..ad968ff968d7 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -181,7 +181,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "WAKE1_MICO"; gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index fbfa75e53f32..c172fdb5e1ae 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -182,7 +182,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "WAKE1_MICO"; gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 380f22a35821..a1bcd67fa505 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -993,7 +993,7 @@ touchscreen@41 { compatible = "st,stmpe811"; reg = <0x41>; - irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; + irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; interrupt-controller; id = <0>; blocks = <0x5>; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 9bdc4cb71449..99d7dad72d29 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -976,7 +976,7 @@ touchscreen@41 { compatible = "st,stmpe811"; reg = <0x41>; - irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; + irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; interrupt-controller; id = <0>; blocks = <0x5>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 2c2ad2a38f04..ee683c5a9c62 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -63,7 +63,7 @@ gpio@6000d000 { init-mode-hog { gpio-hog; - gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>, + gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>, <TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>, <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; output-low; @@ -820,7 +820,7 @@ vddio-supply = <&vdd_1v8>; device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; }; }; @@ -833,7 +833,7 @@ status = "okay"; touchscreen@10 { - compatible ="elan,ektf3624"; + compatible = "elan,ektf3624"; reg = <0x10>; interrupt-parent = <&gpio>; @@ -1124,7 +1124,7 @@ gpio-keys { compatible = "gpio-keys"; - hall-sensor { + switch-hall-sensor { label = "Lid"; gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -1134,7 +1134,7 @@ wakeup-source; }; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -1143,7 +1143,7 @@ wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -1152,7 +1152,7 @@ wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi index cd63e0ef7445..1b241f0542b8 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi @@ -25,7 +25,7 @@ gpio@6000d000 { init-mode-3g-hog { gpio-hog; - gpios = <TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>, + gpios = <TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>, <TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>, <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>, <TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>, diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/tegra30-asus-tf700t.dts index 18a9bfa5e97b..1a331dec3cfe 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf700t.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf700t.dts @@ -742,7 +742,7 @@ #address-cells = <1>; #size-cells = <0>; - dsi-bridge@7 { + dsi@7 { compatible = "toshiba,tc358768"; reg = <0x7>; diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi index 85b43a86a26d..c27e70d8bf2b 100644 --- a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi @@ -1080,6 +1080,7 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; /* Broadcom GPS BCM47511 */ @@ -1087,6 +1088,7 @@ serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; nvidia,adjust-baud-rates = <0 9600 100>, @@ -1509,7 +1511,7 @@ compatible = "gpio-keys"; interrupt-parent = <&gpio>; - dock-hall-sensor { + switch-dock-hall-sensor { label = "Lid sensor"; gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -1519,7 +1521,7 @@ wakeup-source; }; - lineout-detect { + switch-lineout-detect { label = "Audio dock line-out detect"; gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -1542,7 +1544,7 @@ compatible = "gpio-keys"; interrupt-parent = <&gpio>; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -1551,7 +1553,7 @@ wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -1560,7 +1562,7 @@ wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index ba257ed36d9c..540530c983ff 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -685,7 +685,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; interrupt-parent = <&pmic>; interrupts = <2 0>; @@ -694,14 +694,14 @@ wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <10>; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 7d4a6ca4936a..8dbc15f9a9e4 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -145,7 +145,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "SODIMM pin 45 wakeup"; gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index be691a1c33a1..2867a138e011 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -239,7 +239,7 @@ nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; spdif-in-pk6 { - nvidia,pins = "spdif_in_pk6"; + nvidia,pins = "spdif_in_pk6"; nvidia,function = "hda"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; @@ -364,7 +364,7 @@ }; /* Multiplexed and therefore disabled */ cam-mclk-pcc0 { - nvidia,pins = "cam_mclk_pcc0"; + nvidia,pins = "cam_mclk_pcc0"; nvidia,function = "vi_alt3"; nvidia,pull = <TEGRA_PIN_PULL_DOWN>; nvidia,tristate = <TEGRA_PIN_ENABLE>; @@ -511,7 +511,7 @@ /* Colibri USBC_DET */ spdif-out-pk5 { - nvidia,pins = "spdif_out_pk5"; + nvidia,pins = "spdif_out_pk5"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; @@ -849,7 +849,7 @@ touchscreen@41 { compatible = "st,stmpe811"; reg = <0x41>; - irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; + irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; interrupt-controller; id = <0>; blocks = <0x5>; @@ -960,7 +960,7 @@ #address-cells = <1>; #size-cells = <0>; - asix@1 { + ethernet@1 { compatible = "usbb95,772b"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index a5cfbab5f565..b7acea39b942 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -4553,7 +4553,7 @@ #address-cells = <1>; #size-cells = <0>; - smsc@2 { /* SMSC 10/100T Ethernet Controller */ + ethernet@2 { /* SMSC 10/100T Ethernet Controller */ compatible = "usb424,9e00"; reg = <2>; local-mac-address = [00 11 22 33 44 55]; @@ -4764,7 +4764,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; debounce-interval = <10>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts index f4b2d4218849..7c81f0205549 100644 --- a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts +++ b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts @@ -1103,6 +1103,7 @@ uartb: serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; /* Broadcom GPS BCM47511 */ @@ -1110,6 +1111,7 @@ uartc: serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; nvidia,adjust-baud-rates = <0 9600 100>, @@ -2653,7 +2655,7 @@ compatible = "gpio-keys"; interrupt-parent = <&gpio>; - dock-insert { + switch-dock-insert { label = "Chagall Dock"; gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -2663,7 +2665,7 @@ wakeup-source; }; - lineout-detect { + switch-lineout-detect { label = "Audio dock line-out detect"; gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -2686,7 +2688,7 @@ compatible = "gpio-keys"; interrupt-parent = <&gpio>; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -2695,7 +2697,7 @@ wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -2704,7 +2706,7 @@ wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts index c46c2e8a10a7..e007db084787 100644 --- a/arch/arm/boot/dts/uniphier-ld4-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts @@ -36,11 +36,11 @@ }; ðsc { - interrupts = <1 8>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; }; &serialsc { - interrupts = <1 8>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; }; &serial0 { @@ -56,7 +56,7 @@ }; &gpio { - xirq1 { + xirq1-hog { gpio-hog; gpios = <UNIPHIER_GPIO_IRQ(1) 0>; input; diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index b52957ccda0d..9dceff12a633 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -6,6 +6,7 @@ // Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/uniphier-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "socionext,uniphier-ld4"; @@ -55,7 +56,8 @@ compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-size = <(512 * 1024)>; cache-sets = <256>; @@ -69,7 +71,7 @@ reg = <0x54006000 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 39 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; @@ -80,7 +82,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006800 0x40>; - interrupts = <0 33 4>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; @@ -91,7 +93,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006900 0x40>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; @@ -102,7 +104,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; @@ -113,7 +115,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006b00 0x40>; - interrupts = <0 29 4>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; @@ -140,7 +142,7 @@ reg = <0x58400000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 41 1>; + interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; @@ -154,7 +156,7 @@ reg = <0x58480000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 42 1>; + interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; @@ -168,7 +170,7 @@ reg = <0x58500000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 43 1>; + interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; @@ -182,7 +184,7 @@ reg = <0x58580000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 44 1>; + interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; @@ -240,8 +242,13 @@ dmac: dma-controller@5a000000 { compatible = "socionext,uniphier-mio-dmac"; reg = <0x5a000000 0x1000>; - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, - <0 71 4>, <0 72 4>, <0 73 4>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mio_clk 7>; resets = <&mio_rst 7>; #dma-cells = <1>; @@ -251,7 +258,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default", "uhs"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_uhs>; @@ -271,7 +278,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a500000 0x200>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&mio_clk 1>; @@ -289,7 +296,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, @@ -303,7 +310,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, @@ -317,7 +324,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, @@ -358,14 +365,16 @@ timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; + interrupts = <GIC_PPI 11 + (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; timer@60000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; @@ -407,7 +416,7 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 65 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts index 5bc7fe11b517..223a78b4a761 100644 --- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts @@ -40,11 +40,11 @@ }; ðsc { - interrupts = <4 8>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; }; &serialsc { - interrupts = <4 8>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; }; &serial0 { @@ -60,7 +60,7 @@ }; &gpio { - xirq4 { + xirq4-hog { gpio-hog; gpios = <UNIPHIER_GPIO_IRQ(4) 0>; input; diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi index c0fd029b37e5..f909ec2e5333 100644 --- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi @@ -196,11 +196,21 @@ function = "usb0"; }; + pinctrl_usb0_device: usb0-device { + groups = "usb0_device"; + function = "usb0"; + }; + pinctrl_usb1: usb1 { groups = "usb1"; function = "usb1"; }; + pinctrl_usb1_device: usb1-device { + groups = "usb1_device"; + function = "usb1"; + }; + pinctrl_usb2: usb2 { groups = "usb2"; function = "usb2"; diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts index 27ff2b7b9d0e..6baee4410d9c 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ace.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts @@ -99,3 +99,11 @@ &usb1 { status = "okay"; }; + +&ahci0 { + status = "okay"; +}; + +&ahci1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts index 3b9b61314d01..d2ce5c039865 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ref.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts @@ -39,11 +39,11 @@ }; ðsc { - interrupts = <2 8>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; }; &serialsc { - interrupts = <2 8>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; }; &serial0 { @@ -59,7 +59,7 @@ }; &gpio { - xirq2 { + xirq2-hog { gpio-hog; gpios = <UNIPHIER_GPIO_IRQ(2) 0>; input; @@ -108,3 +108,11 @@ reg = <0>; }; }; + +&ahci0 { + status = "okay"; +}; + +&ahci1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index a53b73ee93e9..a309e64c57c8 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -6,6 +6,7 @@ // Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/uniphier-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "socionext,uniphier-pro4"; @@ -63,7 +64,8 @@ compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-size = <(768 * 1024)>; cache-sets = <256>; @@ -77,7 +79,7 @@ reg = <0x54006000 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 39 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; @@ -88,7 +90,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006800 0x40>; - interrupts = <0 33 4>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; @@ -99,7 +101,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006900 0x40>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; @@ -110,7 +112,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; @@ -121,7 +123,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; @@ -148,7 +150,7 @@ reg = <0x58780000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 41 4>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; @@ -162,7 +164,7 @@ reg = <0x58781000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 42 4>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; @@ -176,7 +178,7 @@ reg = <0x58782000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 43 4>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; @@ -190,7 +192,7 @@ reg = <0x58783000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 44 4>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; @@ -206,7 +208,7 @@ reg = <0x58785000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 25 4>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 9>; resets = <&peri_rst 9>; clock-frequency = <400000>; @@ -218,7 +220,7 @@ reg = <0x58786000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 26 4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 10>; resets = <&peri_rst 10>; clock-frequency = <400000>; @@ -274,8 +276,14 @@ dmac: dma-controller@5a000000 { compatible = "socionext,uniphier-mio-dmac"; reg = <0x5a000000 0x1000>; - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, - <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mio_clk 7>; resets = <&mio_rst 7>; #dma-cells = <1>; @@ -285,7 +293,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default", "uhs"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_uhs>; @@ -305,7 +313,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a500000 0x200>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&mio_clk 1>; @@ -323,7 +331,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a600000 0x200>; - interrupts = <0 85 4>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sd1>; clocks = <&mio_clk 2>; @@ -339,7 +347,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, @@ -355,7 +363,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, @@ -376,7 +384,7 @@ compatible = "socionext,uniphier-pro4-pinctrl"; }; - usb-phy { + usb-controller { compatible = "socionext,uniphier-pro4-usb2-phy"; #address-cells = <1>; #size-cells = <0>; @@ -403,6 +411,11 @@ vbus-supply = <&usb1_vbus>; }; }; + + sg_clk: clock { + compatible = "socionext,uniphier-pro4-sg-clock"; + #clock-cells = <1>; + }; }; soc-glue@5f900000 { @@ -431,7 +444,7 @@ xdmac: dma-controller@5fc10000 { compatible = "socionext,uniphier-xdmac"; reg = <0x5fc10000 0x5300>; - interrupts = <0 188 4>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <16>; #dma-cells = <2>; }; @@ -446,14 +459,16 @@ timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; - interrupts = <1 11 0x304>; + interrupts = <GIC_PPI 11 + (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; timer@60000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x60000600 0x20>; - interrupts = <1 13 0x304>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; @@ -485,7 +500,7 @@ compatible = "socionext,uniphier-pro4-ave4"; status = "disabled"; reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ether_rgmii>; clock-names = "gio", "ether", "ether-gb", "ether-phy"; @@ -503,12 +518,105 @@ }; }; + ahci0: sata@65600000 { + compatible = "socionext,uniphier-pro4-ahci", + "generic-ahci"; + status = "disabled"; + reg = <0x65600000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sys_clk 12>, <&sys_clk 28>; + resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>; + ports-implemented = <1>; + phys = <&ahci0_phy>; + assigned-clocks = <&sg_clk 0>; + assigned-clock-rates = <25000000>; + }; + + sata-controller@65700000 { + compatible = "socionext,uniphier-pxs2-ahci-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65700000 0x100>; + + ahci0_rst: reset-controller@0 { + compatible = "socionext,uniphier-pro4-ahci-reset"; + reg = <0x0 0x4>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 28>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 28>; + #reset-cells = <1>; + }; + + ahci0_phy: sata-phy@10 { + compatible = "socionext,uniphier-pro4-ahci-phy"; + reg = <0x10 0x40>; + clock-names = "link", "gio"; + clocks = <&sys_clk 28>, <&sys_clk 12>; + reset-names = "link", "gio", "phy", + "pm", "tx", "rx"; + resets = <&sys_rst 28>, <&sys_rst 12>, + <&sys_rst 30>, + <&ahci0_rst 0>, <&ahci0_rst 1>, + <&ahci0_rst 2>; + #phy-cells = <0>; + }; + }; + + ahci1: sata@65800000 { + compatible = "socionext,uniphier-pro4-ahci", + "generic-ahci"; + status = "disabled"; + reg = <0x65800000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sys_clk 12>, <&sys_clk 29>; + resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>; + ports-implemented = <1>; + phys = <&ahci1_phy>; + assigned-clocks = <&sg_clk 0>; + assigned-clock-rates = <25000000>; + }; + + sata-controller@65900000 { + compatible = "socionext,uniphier-pro4-ahci-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65900000 0x100>; + + ahci1_rst: reset-controller@0 { + compatible = "socionext,uniphier-pro4-ahci-reset"; + reg = <0x0 0x4>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 29>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 29>; + #reset-cells = <1>; + }; + + ahci1_phy: sata-phy@10 { + compatible = "socionext,uniphier-pro4-ahci-phy"; + reg = <0x10 0x40>; + clock-names = "link", "gio"; + clocks = <&sys_clk 29>, <&sys_clk 12>; + reset-names = "link", "gio", "phy", + "pm", "tx", "rx"; + resets = <&sys_rst 29>, <&sys_rst 12>, + <&sys_rst 30>, + <&ahci1_rst 0>, <&ahci1_rst 1>, + <&ahci1_rst 2>; + #phy-cells = <0>; + }; + }; + usb0: usb@65a00000 { compatible = "socionext,uniphier-dwc3", "snps,dwc3"; status = "disabled"; reg = <0x65a00000 0xcd00>; interrupt-names = "host", "peripheral"; - interrupts = <0 134 4>, <0 135 4>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clock-names = "ref", "bus_early", "suspend"; @@ -518,7 +626,7 @@ dr_mode = "host"; }; - usb-glue@65b00000 { + usb-controller@65b00000 { compatible = "socionext,uniphier-pro4-dwc3-glue", "simple-mfd"; #address-cells = <1>; @@ -561,7 +669,8 @@ status = "disabled"; reg = <0x65c00000 0xcd00>; interrupt-names = "host", "peripheral"; - interrupts = <0 137 4>, <0 138 4>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; clock-names = "ref", "bus_early", "suspend"; @@ -571,7 +680,7 @@ dr_mode = "host"; }; - usb-glue@65d00000 { + usb-controller@65d00000 { compatible = "socionext,uniphier-pro4-dwc3-glue", "simple-mfd"; #address-cells = <1>; @@ -605,7 +714,7 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 65 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 3525125832dd..100edd7438d8 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -5,6 +5,8 @@ // Copyright (C) 2015-2016 Socionext Inc. // Author: Masahiro Yamada <yamada.masahiro@socionext.com> +#include <dt-bindings/interrupt-controller/arm-gic.h> + / { compatible = "socionext,uniphier-pro5"; #address-cells = <1>; @@ -135,7 +137,8 @@ compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; - interrupts = <0 190 4>, <0 191 4>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-size = <(2 * 1024 * 1024)>; cache-sets = <512>; @@ -148,7 +151,8 @@ compatible = "socionext,uniphier-system-cache"; reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; - interrupts = <0 174 4>, <0 175 4>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-size = <(2 * 1024 * 1024)>; cache-sets = <512>; @@ -162,7 +166,7 @@ reg = <0x54006000 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 39 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; @@ -175,7 +179,7 @@ reg = <0x54006100 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 216 4>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; clocks = <&peri_clk 11>; /* common with spi0 */ @@ -186,7 +190,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006800 0x40>; - interrupts = <0 33 4>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; @@ -197,7 +201,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006900 0x40>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; @@ -208,7 +212,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; @@ -219,7 +223,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; @@ -246,7 +250,7 @@ reg = <0x58780000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 41 4>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; @@ -260,7 +264,7 @@ reg = <0x58781000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 42 4>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; @@ -274,7 +278,7 @@ reg = <0x58782000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 43 4>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; @@ -288,7 +292,7 @@ reg = <0x58783000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 44 4>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; @@ -304,7 +308,7 @@ reg = <0x58785000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 25 4>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 9>; resets = <&peri_rst 9>; clock-frequency = <400000>; @@ -316,7 +320,7 @@ reg = <0x58786000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 26 4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 10>; resets = <&peri_rst 10>; clock-frequency = <400000>; @@ -415,7 +419,7 @@ xdmac: dma-controller@5fc10000 { compatible = "socionext,uniphier-xdmac"; reg = <0x5fc10000 0x5300>; - interrupts = <0 188 4>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <16>; #dma-cells = <2>; }; @@ -430,14 +434,16 @@ timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; - interrupts = <1 11 0x304>; + interrupts = <GIC_PPI 11 + (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; timer@60000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x60000600 0x20>; - interrupts = <1 13 0x304>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; @@ -470,7 +476,7 @@ status = "disabled"; reg = <0x65a00000 0xcd00>; interrupt-names = "host"; - interrupts = <0 134 4>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clock-names = "ref", "bus_early", "suspend"; @@ -480,7 +486,7 @@ dr_mode = "host"; }; - usb-glue@65b00000 { + usb-controller@65b00000 { compatible = "socionext,uniphier-pro5-dwc3-glue", "simple-mfd"; #address-cells = <1>; @@ -534,7 +540,7 @@ status = "disabled"; reg = <0x65c00000 0xcd00>; interrupt-names = "host"; - interrupts = <0 137 4>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; clock-names = "ref", "bus_early", "suspend"; @@ -544,7 +550,7 @@ dr_mode = "host"; }; - usb-glue@65d00000 { + usb-controller@65d00000 { compatible = "socionext,uniphier-pro5-dwc3-glue", "simple-mfd"; #address-cells = <1>; @@ -614,8 +620,7 @@ }; pcie_ep: pcie-ep@66000000 { - compatible = "socionext,uniphier-pro5-pcie-ep", - "snps,dw-pcie-ep"; + compatible = "socionext,uniphier-pro5-pcie-ep"; status = "disabled"; reg-names = "dbi", "dbi2", "link", "addr_space"; reg = <0x66000000 0x1000>, <0x66001000 0x1000>, @@ -650,7 +655,7 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 65 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; @@ -663,7 +668,7 @@ compatible = "socionext,uniphier-sd-v3.1"; status = "disabled"; reg = <0x68400000 0x800>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&sd_clk 1>; @@ -679,7 +684,7 @@ compatible = "socionext,uniphier-sd-v3.1"; status = "disabled"; reg = <0x68800000 0x800>; - interrupts = <0 76 4>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default", "uhs"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_uhs>; diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts index 759384b60663..5f18b926c50a 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts @@ -99,3 +99,7 @@ &usb1 { status = "okay"; }; + +&ahci { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index e81e5937a60a..ca4dccf56a67 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -6,6 +6,7 @@ // Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/uniphier-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> / { @@ -161,7 +162,10 @@ compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-size = <(1280 * 1024)>; cache-sets = <512>; @@ -175,7 +179,7 @@ reg = <0x54006000 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 39 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; @@ -188,7 +192,7 @@ reg = <0x54006100 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 216 4>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; clocks = <&peri_clk 12>; @@ -199,7 +203,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006800 0x40>; - interrupts = <0 33 4>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; @@ -210,7 +214,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006900 0x40>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; @@ -221,7 +225,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; @@ -232,7 +236,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; @@ -259,7 +263,7 @@ audio@56000000 { compatible = "socionext,uniphier-pxs2-aio"; reg = <0x56000000 0x80000>; - interrupts = <0 144 4>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ain1>, <&pinctrl_ain2>, @@ -317,7 +321,7 @@ reg = <0x58780000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 41 4>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; @@ -331,7 +335,7 @@ reg = <0x58781000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 42 4>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; @@ -345,7 +349,7 @@ reg = <0x58782000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 43 4>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; @@ -359,7 +363,7 @@ reg = <0x58783000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 44 4>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; @@ -373,7 +377,7 @@ reg = <0x58784000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 45 4>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 8>; resets = <&peri_rst 8>; clock-frequency = <400000>; @@ -385,7 +389,7 @@ reg = <0x58785000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 25 4>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 9>; resets = <&peri_rst 9>; clock-frequency = <400000>; @@ -397,7 +401,7 @@ reg = <0x58786000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 26 4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 10>; resets = <&peri_rst 10>; clock-frequency = <400000>; @@ -454,7 +458,7 @@ compatible = "socionext,uniphier-sd-v3.1.1"; status = "disabled"; reg = <0x5a000000 0x800>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&sd_clk 1>; @@ -470,7 +474,7 @@ compatible = "socionext,uniphier-sd-v3.1.1"; status = "disabled"; reg = <0x5a400000 0x800>; - interrupts = <0 76 4>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default", "uhs"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_uhs>; @@ -515,7 +519,7 @@ xdmac: dma-controller@5fc10000 { compatible = "socionext,uniphier-xdmac"; reg = <0x5fc10000 0x5300>; - interrupts = <0 188 4>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <16>; #dma-cells = <2>; }; @@ -530,14 +534,16 @@ timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; - interrupts = <1 11 0xf04>; + interrupts = <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; timer@60000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x60000600 0x20>; - interrupts = <1 13 0xf04>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; @@ -564,9 +570,9 @@ #reset-cells = <1>; }; - pvtctl: pvtctl { + pvtctl: thermal-sensor { compatible = "socionext,uniphier-pxs2-thermal"; - interrupts = <0 3 4>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <0>; socionext,tmod-calibration = <0x0f86 0x6844>; }; @@ -576,7 +582,7 @@ compatible = "socionext,uniphier-pxs2-ave4"; status = "disabled"; reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ether_rgmii>; clock-names = "ether"; @@ -593,12 +599,52 @@ }; }; + ahci: sata@65600000 { + compatible = "socionext,uniphier-pxs2-ahci", + "generic-ahci"; + status = "disabled"; + reg = <0x65600000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sys_clk 28>; + resets = <&sys_rst 28>, <&ahci_rst 0>; + ports-implemented = <1>; + phys = <&ahci_phy>; + }; + + sata-controller@65700000 { + compatible = "socionext,uniphier-pxs2-ahci-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65700000 0x100>; + + ahci_rst: reset-controller@0 { + compatible = "socionext,uniphier-pxs2-ahci-reset"; + reg = <0x0 0x4>; + clock-names = "link"; + clocks = <&sys_clk 28>; + reset-names = "link"; + resets = <&sys_rst 28>; + #reset-cells = <1>; + }; + + ahci_phy: sata-phy@10 { + compatible = "socionext,uniphier-pxs2-ahci-phy"; + reg = <0x10 0x10>; + clock-names = "link"; + clocks = <&sys_clk 28>; + reset-names = "link", "phy"; + resets = <&sys_rst 28>, <&sys_rst 30>; + #phy-cells = <0>; + }; + }; + usb0: usb@65a00000 { compatible = "socionext,uniphier-dwc3", "snps,dwc3"; status = "disabled"; reg = <0x65a00000 0xcd00>; - interrupt-names = "host", "peripheral"; - interrupts = <0 134 4>, <0 135 4>; + interrupt-names = "dwc_usb3"; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; clock-names = "ref", "bus_early", "suspend"; @@ -609,7 +655,7 @@ dr_mode = "host"; }; - usb-glue@65b00000 { + usb-controller@65b00000 { compatible = "socionext,uniphier-pxs2-dwc3-glue", "simple-mfd"; #address-cells = <1>; @@ -693,8 +739,8 @@ compatible = "socionext,uniphier-dwc3", "snps,dwc3"; status = "disabled"; reg = <0x65c00000 0xcd00>; - interrupt-names = "host", "peripheral"; - interrupts = <0 137 4>, <0 138 4>; + interrupt-names = "dwc_usb3"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; clock-names = "ref", "bus_early", "suspend"; @@ -704,7 +750,7 @@ dr_mode = "host"; }; - usb-glue@65d00000 { + usb-controller@65d00000 { compatible = "socionext,uniphier-pxs2-dwc3-glue", "simple-mfd"; #address-cells = <1>; @@ -780,7 +826,7 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 65 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts index 6db949ec7411..2446f9e15360 100644 --- a/arch/arm/boot/dts/uniphier-sld8-ref.dts +++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts @@ -36,11 +36,11 @@ }; ðsc { - interrupts = <0 8>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; &serialsc { - interrupts = <0 8>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; &serial0 { @@ -56,7 +56,7 @@ }; &gpio { - xirq0 { + xirq0-hog { gpio-hog; gpios = <UNIPHIER_GPIO_IRQ(0) 0>; input; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index 96a766deb8d1..67b12dfe513b 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -6,6 +6,7 @@ // Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/uniphier-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "socionext,uniphier-sld8"; @@ -55,7 +56,8 @@ compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-size = <(256 * 1024)>; cache-sets = <256>; @@ -69,7 +71,7 @@ reg = <0x54006000 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 39 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; @@ -80,7 +82,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006800 0x40>; - interrupts = <0 33 4>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; @@ -91,7 +93,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006900 0x40>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; @@ -102,7 +104,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; @@ -113,7 +115,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006b00 0x40>; - interrupts = <0 29 4>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; @@ -144,7 +146,7 @@ reg = <0x58400000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 41 1>; + interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; @@ -158,7 +160,7 @@ reg = <0x58480000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 42 1>; + interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; @@ -172,7 +174,7 @@ reg = <0x58500000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 43 1>; + interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; @@ -186,7 +188,7 @@ reg = <0x58580000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 44 1>; + interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; @@ -244,8 +246,13 @@ dmac: dma-controller@5a000000 { compatible = "socionext,uniphier-mio-dmac"; reg = <0x5a000000 0x1000>; - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, - <0 71 4>, <0 72 4>, <0 73 4>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mio_clk 7>; resets = <&mio_rst 7>; #dma-cells = <1>; @@ -255,7 +262,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default", "uhs"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_uhs>; @@ -275,7 +282,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a500000 0x200>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&mio_clk 1>; @@ -293,7 +300,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, @@ -307,7 +314,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, @@ -321,7 +328,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, @@ -362,14 +369,16 @@ timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; + interrupts = <GIC_PPI 11 + (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; timer@60000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; @@ -411,7 +420,7 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 65 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi index 444802fee9fb..97e7d5db8eb8 100644 --- a/arch/arm/boot/dts/uniphier-support-card.dtsi +++ b/arch/arm/boot/dts/uniphier-support-card.dtsi @@ -8,13 +8,13 @@ &system_bus { status = "okay"; ranges = <1 0x00000000 0x42000000 0x02000000>; - interrupt-parent = <&gpio>; ethsc: ethernet@1,1f00000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <1 0x01f00000 0x1000>; phy-mode = "mii"; reg-io-width = <4>; + interrupt-parent = <&gpio>; }; serialsc: serial@1,1fb0000 { @@ -22,5 +22,6 @@ reg = <1 0x01fb0000 0x20>; clock-frequency = <12288000>; reg-shift = <1>; + interrupt-parent = <&gpio>; }; }; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index 8a0cfbfd0c45..b6cb9cdf8197 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -60,7 +60,7 @@ spi0: spi@fffa4000 { cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; status = "okay"; - mtd_dataflash@0 { + flash@0 { compatible = "atmel,at45", "atmel,dataflash"; reg = <0>; spi-max-frequency = <15000000>; diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index 79f7cc241282..a520615f4d8d 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts @@ -391,7 +391,7 @@ reg = <0x101f4000 0x1000>; interrupts = <11>; clocks = <&xtal24mhz>, <&pclk>; - clock-names = "SSPCLK", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; }; fpga { diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi index c12a1b8bc086..14c411f146f5 100644 --- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi @@ -103,7 +103,7 @@ status = "okay"; /* M41T0M6 real time clock on carrier board */ - rtc: m41t0m6@68 { + rtc: rtc@68 { compatible = "st,m41t0"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/vf610-bk4.dts b/arch/arm/boot/dts/vf610-bk4.dts index 830c85476b3d..551a4c3ff4fa 100644 --- a/arch/arm/boot/dts/vf610-bk4.dts +++ b/arch/arm/boot/dts/vf610-bk4.dts @@ -61,7 +61,7 @@ regulator-max-microvolt = <3300000>; }; - spi-gpio { + spi { compatible = "spi-gpio"; pinctrl-0 = <&pinctrl_gpio_spi>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/vf610-pinfunc.h b/arch/arm/boot/dts/vf610-pinfunc.h index f1e5a7cf58a9..b7b7322a2d1b 100644 --- a/arch/arm/boot/dts/vf610-pinfunc.h +++ b/arch/arm/boot/dts/vf610-pinfunc.h @@ -420,7 +420,7 @@ #define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 #define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 #define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 -#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 +#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 #define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 #define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 #define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 @@ -802,5 +802,55 @@ #define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 #define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 #define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 +#define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A15__DDR_A_15 0x220 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A14__DDR_A_14 0x224 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A13__DDR_A_13 0x228 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A12__DDR_A_12 0x22c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A11__DDR_A_11 0x230 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A10__DDR_A_10 0x234 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A9__DDR_A_9 0x238 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A8__DDR_A_8 0x23c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A7__DDR_A_7 0x240 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A6__DDR_A_6 0x244 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A5__DDR_A_5 0x248 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A4__DDR_A_4 0x24c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A3__DDR_A_3 0x250 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A2__DDR_A_2 0x254 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A1__DDR_A_1 0x258 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A0__DDR_A_0 0x25c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA2__DDR_BA_2 0x260 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA1__DDR_BA_1 0x264 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA0__DDR_BA_0 0x268 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CAS__DDR_CAS_B 0x26c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CKE__DDR_CKE_0 0x270 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CLK__DDR_CLK_0 0x274 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CS__DDR_CS_B_0 0x278 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D15__DDR_D_15 0x27c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D14__DDR_D_14 0x280 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D13__DDR_D_13 0x284 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D12__DDR_D_12 0x288 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D11__DDR_D_11 0x28c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D10__DDR_D_10 0x290 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D9__DDR_D_9 0x294 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D8__DDR_D_8 0x298 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D7__DDR_D_7 0x29c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D6__DDR_D_6 0x2a0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D5__DDR_D_5 0x2a4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D4__DDR_D_4 0x2a8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D3__DDR_D_3 0x2ac 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D2__DDR_D_2 0x2b0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D1__DDR_D_1 0x2b4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D0__DDR_D_0 0x2b8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQM1__DDR_DQM_1 0x2bc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQM0__DDR_DQM_0 0x2c0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQS1__DDR_DQS_1 0x2c4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQS0__DDR_DQS_0 0x2c8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_RAS__DDR_RAS_B 0x2cc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_WE__DDR_WE_B 0x2d0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_ODT1__DDR_ODT_0 0x2d4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x2d8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x2e0 0x000 ALT0 0x0 #endif diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index dbb5ffcdcec4..6c246d5aa032 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -169,7 +169,7 @@ VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; clocks = <&clks VF610_CLK_SAI2>; - }; + }; }; &iomuxc { diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 1f9686c33a84..42ed4a04a12e 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -288,7 +288,7 @@ }; }; - spi0 { + spi-0 { compatible = "spi-gpio"; pinctrl-0 = <&pinctrl_gpio_spi0>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index 956182d08e74..2fba923821d0 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -2,7 +2,6 @@ // // Copyright 2013 Freescale Semiconductor, Inc. - #include "vf500.dtsi" &a5_cpu { diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 47c2a4b14c06..c193264a86ff 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -343,8 +343,6 @@ <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index cf70aff26c66..d23201ba8cd7 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -30,14 +30,14 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw14 { + switch-14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; - sw13 { + switch-13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ diff --git a/arch/arm/boot/dts/zynq-zturn-common.dtsi b/arch/arm/boot/dts/zynq-zturn-common.dtsi index bf5d1c4568b0..dfb1fbafe3aa 100644 --- a/arch/arm/boot/dts/zynq-zturn-common.dtsi +++ b/arch/arm/boot/dts/zynq-zturn-common.dtsi @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - K1 { + key { label = "K1"; gpios = <&gpio0 0x32 0x1>; linux,code = <0x66>; diff --git a/arch/arm/boot/install.sh b/arch/arm/boot/install.sh index 2a45092a40e3..9ec11fac7d8d 100644..100755 --- a/arch/arm/boot/install.sh +++ b/arch/arm/boot/install.sh @@ -1,7 +1,5 @@ #!/bin/sh # -# arch/arm/boot/install.sh -# # This file is subject to the terms and conditions of the GNU General Public # License. See the file "COPYING" in the main directory of this archive # for more details. @@ -18,25 +16,6 @@ # $2 - kernel image file # $3 - kernel map file # $4 - default install path (blank if root directory) -# - -verify () { - if [ ! -f "$1" ]; then - echo "" 1>&2 - echo " *** Missing file: $1" 1>&2 - echo ' *** You need to run "make" before "make install".' 1>&2 - echo "" 1>&2 - exit 1 - fi -} - -# Make sure the files actually exist -verify "$2" -verify "$3" - -# User may have a custom install script -if [ -x ~/bin/${INSTALLKERNEL} ]; then exec ~/bin/${INSTALLKERNEL} "$@"; fi -if [ -x /sbin/${INSTALLKERNEL} ]; then exec /sbin/${INSTALLKERNEL} "$@"; fi if [ "$(basename $2)" = "zImage" ]; then # Compressed install |