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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-08-25drm/i915: Nuke intel_prepare_shared_dpll()Ville Syrjälä1-28/+0
2021-08-25drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable()Ville Syrjälä1-10/+3
2021-08-12Merge tag 'drm-intel-next-2021-08-10-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-nextDave Airlie1-494/+131
2021-08-03drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabledImre Deak1-1/+33
2021-07-30drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.cLucas De Marchi1-492/+94
2021-07-22drm/i915/dg2: Skip shared DPLL handlingMatt Roper1-1/+4
2021-07-14Merge branch 'topic/revid_steppings' into drm-intel-gt-nextMatt Roper1-1/+1
2021-07-14drm/i915/jsl_ehl: Use revid->stepping tablesMatt Roper1-1/+1
2021-06-15drm/i915/adl_p: Add initial ADL_P WorkaroundsClint Taylor1-2/+2
2021-05-19drm/i915/adl_p: Add PLL SupportAnusha Srivatsa1-17/+52
2021-05-05drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä1-0/+1
2021-04-28drm/i915/display: move crtc and dpll declarations where they belongJani Nikula1-0/+1
2021-04-14drm/i915/display: rename display version macrosLucas De Marchi1-1/+1
2021-04-14drm/i915/display: Eliminate IS_GEN9_{BC,LP}Matt Roper1-3/+3
2021-03-23drm/i915/display: Eliminate most usage of INTEL_GEN()Matt Roper1-10/+10
2021-03-19drm/i915/display: Fix a typoBhaskar Chowdhury1-1/+1
2021-03-08drm/i915: Use pipes instead crtc indices in PLL state trackingVille Syrjälä1-23/+25
2021-03-08drm/i915: Do intel_dpll_readout_hw_state() after encoder readoutVille Syrjälä1-3/+6
2021-01-26drm/i915/adl_s: Configure DPLL for ADL-SAditya Swarup1-4/+34
2020-12-03Merge tag 'drm-intel-next-queued-2020-11-27' of git://anongit.freedesktop.org/drm/drm-intel into drm-nextDave Airlie1-41/+70
2020-11-16drm: fix some kernel-doc markupsMauro Carvalho Chehab1-1/+1
2020-11-16drm/i915: Use actual readout results for .get_freq()Ville Syrjälä1-33/+45
2020-11-16drm/i915: Introduce intel_dpll_get_hw_state()Ville Syrjälä1-3/+17
2020-11-05drm/i915/ehl: Implement W/A 22010492432Tejas Upadhyay1-5/+8
2020-10-15drm/i915/dg1: Enable DPLL for DG1Lucas De Marchi1-4/+4
2020-10-15drm/i915/dg1: Add and setup DPLLs for DG1Aditya Swarup1-4/+38
2020-10-14drm/i915/jsl: Split EHL/JSL platform info and PCI idsTejas Upadhyay1-8/+8
2020-10-06drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clockImre Deak1-16/+25
2020-10-06drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programmingImre Deak1-0/+13
2020-09-15drm/i915/pll: Centralize PLL_ENABLE register lookupAnusha Srivatsa1-17/+18
2020-09-08Merge tag 'v5.9-rc4' into drm-nextDave Airlie1-4/+4
2020-08-23treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva1-4/+4
2020-08-17drm/i915/rkl: Handle HTIMatt Roper1-0/+11
2020-08-17drm/i915/rkl: Add DPLL4 supportMatt Roper1-5/+36
2020-07-01drm/i915/icl+: Simplify combo/TBT PLL calculation call-chainImre Deak1-37/+27
2020-07-01drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clockImre Deak1-1/+12
2020-04-21drm/i915/display/dpll_mgr: Prefer drm_WARN_ON over WARN_ONPankaj Bharadiya1-4/+4
2020-03-09drm/i915: Fix documentation for intel_dpll_get_freq()Imre Deak1-0/+7
2020-03-02drm/i915: Unify the DPLL ref clock frequency trackingImre Deak1-56/+119
2020-03-02drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out againImre Deak1-5/+2
2020-03-02drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculationImre Deak1-139/+130
2020-03-02drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculationImre Deak1-35/+56
2020-03-02drm/i915/hsw: Split out the SPLL parameter calculationImre Deak1-14/+22
2020-03-02drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLLImre Deak1-5/+5
2020-03-02drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding itImre Deak1-9/+12
2020-03-02drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.cImre Deak1-0/+418
2020-03-02drm/i915: Move the DPLL vfunc inits after the func definesImre Deak1-60/+60
2020-03-02drm/i915: Keep the global DPLL state in a DPLL specific structImre Deak1-30/+30
2020-03-02drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.cImre Deak1-0/+59
2020-03-02drm/i915: Fix bounds check in intel_get_shared_dpll_id()Imre Deak1-3/+6
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